DE60102425D1 - Optimierte Erzeugung von Hardware aus Quellprogrammen mit Multiplikationen - Google Patents

Optimierte Erzeugung von Hardware aus Quellprogrammen mit Multiplikationen

Info

Publication number
DE60102425D1
DE60102425D1 DE60102425T DE60102425T DE60102425D1 DE 60102425 D1 DE60102425 D1 DE 60102425D1 DE 60102425 T DE60102425 T DE 60102425T DE 60102425 T DE60102425 T DE 60102425T DE 60102425 D1 DE60102425 D1 DE 60102425D1
Authority
DE
Germany
Prior art keywords
multiplications
hardware
source programs
optimized generation
optimized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
DE60102425T
Other languages
English (en)
Other versions
DE60102425T2 (de
Inventor
Paul Philip Boca
Andrew Kay
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Publication of DE60102425D1 publication Critical patent/DE60102425D1/de
Application granted granted Critical
Publication of DE60102425T2 publication Critical patent/DE60102425T2/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Devices For Executing Special Programs (AREA)
  • Complex Calculations (AREA)
DE60102425T 2000-08-30 2001-08-23 Optimierte Erzeugung von Hardware aus Quellprogrammen mit Multiplikationen Expired - Lifetime DE60102425T2 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0021222 2000-08-30
GB0021222A GB2366404A (en) 2000-08-30 2000-08-30 A method for improving the high-level synthesis of expressions involving multiplications

Publications (2)

Publication Number Publication Date
DE60102425D1 true DE60102425D1 (de) 2004-04-29
DE60102425T2 DE60102425T2 (de) 2005-02-24

Family

ID=9898471

Family Applications (1)

Application Number Title Priority Date Filing Date
DE60102425T Expired - Lifetime DE60102425T2 (de) 2000-08-30 2001-08-23 Optimierte Erzeugung von Hardware aus Quellprogrammen mit Multiplikationen

Country Status (5)

Country Link
US (1) US6820257B2 (de)
EP (1) EP1187044B1 (de)
JP (1) JP2002149728A (de)
DE (1) DE60102425T2 (de)
GB (1) GB2366404A (de)

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6925628B2 (en) * 2002-10-22 2005-08-02 Matsushita Electric Industrial Co., Ltd. High-level synthesis method
JP5109764B2 (ja) * 2008-03-31 2012-12-26 日本電気株式会社 記述処理装置、記述処理方法およびプログラム
US8136063B2 (en) * 2008-11-14 2012-03-13 Synopsys, Inc. Unfolding algorithm in multirate system folding
US10268798B2 (en) 2015-09-22 2019-04-23 International Business Machines Corporation Condition analysis

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5541849A (en) * 1990-04-06 1996-07-30 Lsi Logic Corporation Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of timing parameters
US5910898A (en) * 1995-12-14 1999-06-08 Viewlogic Systems, Inc. Circuit design methods and tools

Also Published As

Publication number Publication date
GB2366404A (en) 2002-03-06
US20020026305A1 (en) 2002-02-28
US6820257B2 (en) 2004-11-16
JP2002149728A (ja) 2002-05-24
EP1187044B1 (de) 2004-03-24
EP1187044A3 (de) 2002-07-03
GB0021222D0 (en) 2000-10-18
EP1187044A2 (de) 2002-03-13
DE60102425T2 (de) 2005-02-24

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Legal Events

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