DE69415393D1 - Struktur zur Verwendung eines teilweise funktionsfähigen Cachespeichers - Google Patents

Struktur zur Verwendung eines teilweise funktionsfähigen Cachespeichers

Info

Publication number
DE69415393D1
DE69415393D1 DE69415393T DE69415393T DE69415393D1 DE 69415393 D1 DE69415393 D1 DE 69415393D1 DE 69415393 T DE69415393 T DE 69415393T DE 69415393 T DE69415393 T DE 69415393T DE 69415393 D1 DE69415393 D1 DE 69415393D1
Authority
DE
Germany
Prior art keywords
partially functional
functional cache
cache
partially
functional
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69415393T
Other languages
English (en)
Other versions
DE69415393T2 (de
Inventor
David Charles Mcclure
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics lnc USA
Original Assignee
STMicroelectronics lnc USA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics lnc USA filed Critical STMicroelectronics lnc USA
Publication of DE69415393D1 publication Critical patent/DE69415393D1/de
Application granted granted Critical
Publication of DE69415393T2 publication Critical patent/DE69415393T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/70—Masking faults in memories by using spares or by reconfiguring
    • G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0888—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches using selective caching, e.g. bypass

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)
DE69415393T 1993-05-28 1994-05-19 Struktur zur Verwendung eines teilweise funktionsfähigen Cachespeichers Expired - Fee Related DE69415393T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US08/069,024 US5551004A (en) 1993-05-28 1993-05-28 Structure which renders faulty data of a cache memory uncacheable in order that a partially functional cache memory may be utilized

Publications (2)

Publication Number Publication Date
DE69415393D1 true DE69415393D1 (de) 1999-02-04
DE69415393T2 DE69415393T2 (de) 1999-05-12

Family

ID=22086227

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69415393T Expired - Fee Related DE69415393T2 (de) 1993-05-28 1994-05-19 Struktur zur Verwendung eines teilweise funktionsfähigen Cachespeichers

Country Status (4)

Country Link
US (1) US5551004A (de)
EP (1) EP0626644B1 (de)
JP (1) JPH07121439A (de)
DE (1) DE69415393T2 (de)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07182238A (ja) * 1993-11-01 1995-07-21 Sgs Thomson Microelectron Inc 欠陥データ無効化回路及び方法
EP0675436B1 (de) * 1994-03-31 1999-10-27 STMicroelectronics, Inc. Wiederverwendbarer Mehrwegsatz assoziativer Cache-Speicher
US5664148A (en) * 1995-08-17 1997-09-02 Institute For The Development Of Emerging Architectures L.L.C. Cache arrangement including coalescing buffer queue for non-cacheable data
US5765194A (en) * 1996-05-01 1998-06-09 Hewlett-Packard Company Timing consistent dynamic compare with force miss circuit
EP0851343B1 (de) * 1996-12-31 2005-08-31 Metaflow Technologies, Inc. System zur Ausführung von Gleitkommaoperationen
US5805606A (en) * 1997-03-13 1998-09-08 International Business Machines Corporation Cache module fault isolation techniques
US5958068A (en) * 1997-04-14 1999-09-28 International Business Machines Corporation Cache array defect functional bypassing using repair mask
US5835504A (en) * 1997-04-17 1998-11-10 International Business Machines Corporation Soft fuses using bist for cache self test
US5889414A (en) * 1997-04-28 1999-03-30 Mosel Vitelic Corporation Programmable circuits
US6289438B1 (en) 1998-07-29 2001-09-11 Kabushiki Kaisha Toshiba Microprocessor cache redundancy scheme using store buffer
FR2785135B1 (fr) 1998-10-22 2000-12-29 Sfr Sa Procede de lancement d'une application par un terminal, sous commande d'un module d'identification d'abonne, module d'identification d'abonne et terminal correspondants
US6397301B1 (en) * 1999-12-29 2002-05-28 Intel Corporation Preventing access to secure area of a cache
KR100481849B1 (ko) * 2001-12-04 2005-04-11 삼성전자주식회사 용량 변경이 가능한 캐쉬 메모리 및 이를 구비한 프로세서칩
US7809890B2 (en) * 2005-07-06 2010-10-05 Kabushiki Kaisha Toshiba Systems and methods for increasing yield of devices having cache memories by inhibiting use of defective cache entries
US7856576B2 (en) * 2007-04-25 2010-12-21 Hewlett-Packard Development Company, L.P. Method and system for managing memory transactions for memory repair
US10541044B2 (en) * 2016-10-31 2020-01-21 Qualcomm Incorporated Providing efficient handling of memory array failures in processor-based systems

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4357656A (en) * 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
US4335459A (en) * 1980-05-20 1982-06-15 Miller Richard L Single chip random access memory with increased yield and reliability
US4633429A (en) * 1982-12-27 1986-12-30 Motorola, Inc. Partial memory selection using a programmable decoder
US4538247A (en) * 1983-01-14 1985-08-27 Fairchild Research Center Redundant rows in integrated circuit memories
EP0346915A3 (de) * 1988-06-17 1991-03-13 Modular Computer Systems Inc. Cache-Speicherhaltepunktanordnung für Rechner
US5070502A (en) * 1989-06-23 1991-12-03 Digital Equipment Corporation Defect tolerant set associative cache
US5357521A (en) * 1990-02-14 1994-10-18 International Business Machines Corporation Address sensitive memory testing
US5204836A (en) * 1990-10-30 1993-04-20 Sun Microsystems, Inc. Method and apparatus for implementing redundancy in parallel memory structures
US5317711A (en) * 1991-06-14 1994-05-31 Integrated Device Technology, Inc. Structure and method for monitoring an internal cache

Also Published As

Publication number Publication date
JPH07121439A (ja) 1995-05-12
DE69415393T2 (de) 1999-05-12
US5551004A (en) 1996-08-27
EP0626644B1 (de) 1998-12-23
EP0626644A1 (de) 1994-11-30

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee