DE69615940D1 - Schaltkreis zum Setzen des Testmodus bei einem Halbleiterspeicher - Google Patents

Schaltkreis zum Setzen des Testmodus bei einem Halbleiterspeicher

Info

Publication number
DE69615940D1
DE69615940D1 DE69615940T DE69615940T DE69615940D1 DE 69615940 D1 DE69615940 D1 DE 69615940D1 DE 69615940 T DE69615940 T DE 69615940T DE 69615940 T DE69615940 T DE 69615940T DE 69615940 D1 DE69615940 D1 DE 69615940D1
Authority
DE
Germany
Prior art keywords
row address
uppermost
address buffer
high voltage
stage transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
DE69615940T
Other languages
English (en)
Other versions
DE69615940T2 (de
Inventor
Akihiko Kagami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Application granted granted Critical
Publication of DE69615940D1 publication Critical patent/DE69615940D1/de
Publication of DE69615940T2 publication Critical patent/DE69615940T2/de
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/46—Test trigger logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00—Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Dram (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
DE69615940T 1995-06-30 1996-06-21 Schaltkreis zum Setzen des Testmodus bei einem Halbleiterspeicher Expired - Fee Related DE69615940T2 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7166253A JPH0917196A (ja) 1995-06-30 1995-06-30 テストモード設定回路

Publications (2)

Publication Number Publication Date
DE69615940D1 true DE69615940D1 (de) 2001-11-22
DE69615940T2 DE69615940T2 (de) 2002-04-25

Family

ID=15827961

Family Applications (1)

Application Number Title Priority Date Filing Date
DE69615940T Expired - Fee Related DE69615940T2 (de) 1995-06-30 1996-06-21 Schaltkreis zum Setzen des Testmodus bei einem Halbleiterspeicher

Country Status (5)

Country Link
US (1) US5629944A (de)
EP (1) EP0751397B1 (de)
JP (1) JPH0917196A (de)
KR (1) KR0180449B1 (de)
DE (1) DE69615940T2 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480568B1 (ko) * 1997-10-27 2005-09-30 삼성전자주식회사 고전압검출부,및이를구비한반도체메모리장치와반도체메모리장치의모드구별방법
US5956280A (en) * 1998-03-02 1999-09-21 Tanisys Technology, Inc. Contact test method and system for memory testers
KR100286101B1 (ko) * 1999-04-17 2001-03-15 윤종용 반도체 장치의 신호 발생회로
JP2003016800A (ja) * 2001-07-03 2003-01-17 Mitsubishi Electric Corp 半導体装置
JP3943890B2 (ja) * 2001-10-18 2007-07-11 富士通株式会社 半導体装置
US7298656B2 (en) * 2004-04-30 2007-11-20 Infineon Technologies Ag Process monitoring by comparing delays proportional to test voltages and reference voltages
KR100851550B1 (ko) * 2007-02-27 2008-08-11 삼성전자주식회사 테스트 시스템 및 그것의 고전압 측정 방법
JP2018032981A (ja) * 2016-08-24 2018-03-01 株式会社東芝 半導体集積回路
CN113325292B (zh) * 2021-07-09 2022-11-22 华北电力大学 功率半导体器件栅氧性能参数测量电路及其测量方法

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5051995A (en) * 1988-03-14 1991-09-24 Mitsubishi Denki Kabushiki Kaisha Semiconductor memory device having a test mode setting circuit
JPH02213779A (ja) * 1989-02-15 1990-08-24 Hitachi Ltd 半導体集積回路装置
JPH0314238A (ja) * 1989-06-13 1991-01-22 Oki Electric Ind Co Ltd バイポーラ型半導体集積回路装置の製造方法
US5155704A (en) * 1990-10-16 1992-10-13 Micron Technology, Inc. Memory integrated circuit test mode switching
KR960002006B1 (ko) * 1991-03-12 1996-02-09 가부시끼가이샤 도시바 2개의 기준 레벨을 사용하는 기록 검증 제어기를 갖는 전기적으로 소거 가능하고 프로그램 가능한 불휘발성 메모리 장치
JP2894068B2 (ja) * 1992-01-30 1999-05-24 日本電気株式会社 半導体集積回路
JPH0757484A (ja) * 1993-08-11 1995-03-03 Sony Corp Ｎｏｒ型不揮発性メモリ制御回路
US5544175A (en) * 1994-03-15 1996-08-06 Hewlett-Packard Company Method and apparatus for the capturing and characterization of high-speed digital information

Also Published As

Publication number Publication date
EP0751397B1 (de) 2001-10-17
US5629944A (en) 1997-05-13
DE69615940T2 (de) 2002-04-25
EP0751397A3 (de) 1999-01-27
KR0180449B1 (ko) 1999-04-01
KR970002371A (ko) 1997-01-24
EP0751397A2 (de) 1997-01-02
JPH0917196A (ja) 1997-01-17

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Legal Events

Date Code Title Description
8364 No opposition during term of opposition
8339 Ceased/non-payment of the annual fee