DK150796A - Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise - Google Patents

Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise

Info

Publication number
DK150796A
DK150796A DK150796A DK150796A DK150796A DK 150796 A DK150796 A DK 150796A DK 150796 A DK150796 A DK 150796A DK 150796 A DK150796 A DK 150796A DK 150796 A DK150796 A DK 150796A
Authority
DK
Denmark
Prior art keywords
desynchronization
controlling
well
locked loop
digital phase
Prior art date
Application number
DK150796A
Other languages
English (en)
Inventor
Per H Thomsen
Original Assignee
Dsc Communications As
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Dsc Communications As filed Critical Dsc Communications As
Priority to DK150796A priority Critical patent/DK150796A/da
Priority to DK97950004T priority patent/DK0947050T3/da
Priority to EP97950004A priority patent/EP0947050B1/en
Priority to DE69721563T priority patent/DE69721563T2/de
Priority to PCT/DK1997/000594 priority patent/WO1998028849A1/en
Priority to AU53115/98A priority patent/AU5311598A/en
Publication of DK150796A publication Critical patent/DK150796A/da

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/093—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using special filtering or amplification characteristics in the loop

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
DK150796A 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise DK150796A (da)

Priority Applications (6)

Application Number Priority Date Filing Date Title
DK150796A DK150796A (da) 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise
DK97950004T DK0947050T3 (da) 1996-12-23 1997-12-22 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem
EP97950004A EP0947050B1 (en) 1996-12-23 1997-12-22 A digital phase-locked loop and a method of controlling it, as well as a method and receiver circuit for desynchronization in a digital transmission system
DE69721563T DE69721563T2 (de) 1996-12-23 1997-12-22 Digitale phasenregelschleife und verfahren zu ihrer steuerung sowie methode und empfangsschaltung zur desynchronisation in einem digitalen übertragungssystem
PCT/DK1997/000594 WO1998028849A1 (en) 1996-12-23 1997-12-22 A digital phase-locked loop and a method of controlling it, as well as a method and receiver circuit for desynchronization in a digital transmission system
AU53115/98A AU5311598A (en) 1996-12-23 1997-12-22 A digital phase-locked loop and a method of controlling it, as well as a method and receiver circuit for desynchronization in a digital transmission system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DK150796A DK150796A (da) 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise

Publications (1)

Publication Number Publication Date
DK150796A true DK150796A (da) 1998-06-24

Family

ID=8105562

Family Applications (2)

Application Number Title Priority Date Filing Date
DK150796A DK150796A (da) 1996-12-23 1996-12-23 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise
DK97950004T DK0947050T3 (da) 1996-12-23 1997-12-22 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem

Family Applications After (1)

Application Number Title Priority Date Filing Date
DK97950004T DK0947050T3 (da) 1996-12-23 1997-12-22 Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronisering i et digitalt transmissionssystem

Country Status (5)

Country Link
EP (1) EP0947050B1 (da)
AU (1) AU5311598A (da)
DE (1) DE69721563T2 (da)
DK (2) DK150796A (da)
WO (1) WO1998028849A1 (da)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3296297B2 (ja) * 1998-07-23 2002-06-24 ヤマハ株式会社 同期制御方式
DE19941445A1 (de) * 1999-08-30 2001-03-01 Thomson Brandt Gmbh Phasendetektor für eine Phasenregelschleife
US7262645B2 (en) 2002-12-19 2007-08-28 Broadcom Corporation System and method for adjusting the phase of a frequency-locked clock

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4947407A (en) * 1989-08-08 1990-08-07 Siemens-Pacesetter, Inc. Sample-and-hold digital phase-locked loop for ask signals
DE69227820T2 (de) * 1991-10-10 1999-05-12 Nec Corp., Tokio/Tokyo Sonet DS-N-Desynchronisiereinrichtung
US5479457A (en) * 1993-08-27 1995-12-26 Vlsi Technology Inc. Method and apparatus for attenuating jitter in a digital transmission line
US5563891A (en) * 1995-09-05 1996-10-08 Industrial Technology Research Institute Waiting time jitter reduction by synchronizer stuffing threshold modulation

Also Published As

Publication number Publication date
DE69721563D1 (de) 2003-06-05
AU5311598A (en) 1998-07-17
DE69721563T2 (de) 2004-04-08
DK0947050T3 (da) 2003-08-18
WO1998028849A1 (en) 1998-07-02
EP0947050B1 (en) 2003-05-02
EP0947050A1 (en) 1999-10-06

Similar Documents

Publication Publication Date Title
AU2369097A (en) Digital delay-locked loop (DLL) circuit
DK132097A (da) Indretning og fremgangsmåde til udførelse af borehulsfunktioner.
FI954624A7 (fi) Digitaalinen vaihelukittu sisäsilmukka
DK0600776T3 (da) Fremgangsmåde til varmegenvinding, navnlig for kombinerede kredsløb, og anlæg til udøvelse af fremgangsmåden
GB2308759B (en) Digital delay locked loop circuit using synchronous delay line
GB9715131D0 (en) Semiconductor device,semiconductor system and digital delay circuit
HUP9903929A3 (en) Substituted 2(2,6-dioxopiperidin-3-yl)phthalimides and -1-oxoisoindolines-and method of reducing tnf-alpha levels
FI973654A7 (fi) Suoralla digitaalisella syntetisaattorilla ohjattu PLL-taajuussyntetisaattori, johon kuuluu tyhjennys PLL
DK0828692T3 (da) Ny fremgangsmåde til styring af biologisk nedbrydning
EP0669722A3 (en) PLL circuit with reduced locking time.
KR920003707A (ko) 무선에 의한 채널 및 비밀코드 변경과 상호기억방식을 채용한 무선전화시스템 및 비밀코드 변경방법
HUP9701625A3 (en) Method for synchronising transfers of permanent bit rate in atm networks, as well as circuit arrangement for implementing said method
GB2311178B (en) Phase-locked loop circuit
ZA200000410B (en) Method and apparatus for the reproduction of digital data streams.
NO950174D0 (no) PLL syntetiserer og fremgangsmåte for styring av samme
DK0909496T3 (da) System og fremgangsmåde til integration af SNMP og CMIP
NO990569D0 (no) FremgangsmÕte for signalering, samt digitalt radiosystem
EP0610990A3 (en) Digital phase-locked loop.
DK0811748T3 (da) Automatisk, i borehullet placeret pumpe og fremgangsmåde til anvendelse af denne
EP0734124A3 (en) Filter circuit for a phase locked loop
DK0874992T3 (da) Forbindelser og fremgangsmåder til påvisning og forebyggelse af T. cruzi-infektioner
GB2315955B (en) Subscriber authentication for radio local loop system
DK150796A (da) Digital faselåst sløjfe og fremgangsmåde til regulering af en sådan, samt fremgangsmåde og modtagekredsløb til desynkronise
DK0946108T3 (da) Fremgangsmåde til fremstilling af et levnedsmiddeladditiv, levnedsmiddeladditiv, og anvendelse af samme
IL138870A (en) Synchronizing, switching and editing mpeg files

Legal Events

Date Code Title Description
AHB Application shelved due to non-payment