EP0000743A1 - Procédé pour la fabrication des contacts de tantale sur un substrat semi-conducteur de silicium à conductibilité du type N - Google Patents

Procédé pour la fabrication des contacts de tantale sur un substrat semi-conducteur de silicium à conductibilité du type N Download PDF

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Publication number
EP0000743A1
EP0000743A1 EP7878100525A EP78100525A EP0000743A1 EP 0000743 A1 EP0000743 A1 EP 0000743A1 EP 7878100525 A EP7878100525 A EP 7878100525A EP 78100525 A EP78100525 A EP 78100525A EP 0000743 A1 EP0000743 A1 EP 0000743A1
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European Patent Office
Prior art keywords
tantalum
layer
substrate
aluminum
deposited
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EP7878100525A
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German (de)
English (en)
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EP0000743B1 (fr
Inventor
Hormazdyar Minocher Dalal
Majid Ghafghaichi
Lucian Alexander Kasprzak
Hans Wimpfheimer
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International Business Machines Corp
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/62—Electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/061—Manufacture or treatment of FETs having Schottky gates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/80—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials
    • H10D62/83—Semiconductor bodies, or regions thereof, of devices having potential barriers characterised by the materials being Group IV materials, e.g. B-doped Si or undoped Ge
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H10D64/0111—Manufacture or treatment of electrodes ohmically coupled to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/012—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor
    • H10D64/0121—Manufacture or treatment of electrodes comprising a Schottky barrier to a semiconductor to Group IV semiconductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/60—Electrodes characterised by their materials
    • H10D64/64—Electrodes comprising a Schottky barrier to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/019—Manufacture or treatment of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/948—Radiation resist
    • Y10S438/951—Lift-off
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/974—Substrate surface preparation

Definitions

  • the invention relates to a method of tantalum contacts in the production of metallizations in the contacting of silicon semiconductors for the representation of ohmic contacts and Schottky barrier layer contacts.
  • the literature contains a large number of other metallurgical systems that perform one or more functions of metallic contacts.
  • the most successful system of this type is a titanium-tungsten alloy, which has been widely used in industry as a barrier between aluminum and silicon.
  • DTL diode transistor logic
  • the potential threshold of the input diodes is approximately 0.5 eV.
  • the DTL circuit known under the short designation C 3 L is particularly useful when Schottk diodes, which operate as an AND gate on the input side, have this potential threshold.
  • the C 3 L circuit is, for example, in a publication by AW Peltier entitled "Advances in Solid-State Logic - A New Approach to Bipolar LSI: C 3 L" in the 1975 IEEE International Solid-State Circuits Conference, Digest of Technical Papers , Pages 168-169. Peltier states that either titanium, tungsten or titanium-tungsten alloys meet this requirement.
  • the object of the invention is therefore to provide semiconductor circuits which have improved contacts and connecting lines, which in particular consist of an improved single metallurgical system which is suitable both for ohmic contacts and for Schottky blocking contacts with high and low potential thresholds.
  • the process used for the precipitation of tantalum layers should preferably be suitable for the formation of Schottky junction contacts with a precisely controlled potential threshold, while at the same time ensuring compatibility with the connecting lines made of aluminum.
  • This object on which the invention is based is achieved by a novel method for depositing tantalum on silicon, as a result of which a diode structure with a low potential threshold can be precisely controlled.
  • tantalum is directly deposited on N-conducting silicon, and a potential threshold of 0.5 eV is achieved.
  • the diode remains exceptionally stable during extensive voltage tests.
  • a tantalum layer deposited in this way is suitable as an ohmic contact when it is applied to the top of a metal-silicon layer formed in N + -conducting silicon and also as a Schottky barrier diode (SBD) with a high potential threshold, if the layer is deposited on top of a metallic silicide layer formed in N-type silicon.
  • SBD Schottky barrier diode
  • chrome layer must be deposited between the tantalum layer and the aluminum layer.
  • the chrome layer is formed by introducing water vapor during the evaporation or sputtering of elemental chromium. The long-term reliability of this metallurgical system is exceptionally good.
  • the part-Fig. 1A shows the part of a semiconductor die which is to contain the Schottky junction diodes constructed according to the invention. It is obvious that normally within the same die Thousands of such diodes and other semiconductor devices, such as transistors, resistors, etc., can be arranged.
  • the substrate of the semiconductor die consists, for example, of P-type silicon, which has a resistivity of 10 ohm-cm.
  • an N - -type layer 3 is attached, preferably having a conductivity ke it from 1 x 10 16 to 8 x 10 16 atoms / cm 3.
  • two buried zones 4 and 6 are easily seen, which are led out via connection zones 5 and 7 to the surface of the substrate.
  • the substrate also contains a P + -conducting sub-isolation zone 2 which, in conjunction with a P + -conductive isolation zone 8, separates the N + -conducting zones from one another.
  • Zones 2, 4 and 6 are advantageously produced by diffusing these zones through openings provided in the layer covering the surface of the substrate.
  • An interference element causing an N line is arsenic or phosphorus
  • a interference element causing a P + conductivity is boron.
  • the mask layer is then removed from the substrate 1 by conventional etching methods, and a layer 3 is grown epitaxially, the zones 2, 4 and 6 penetrating into the layer 3 by diffusion.
  • a mask layer which is normally composed of a silicon dioxide layer 9 and a silicon nitride layer 10, is then formed on the surface of the layer 3, and openings are then produced in this mask layer, through which openings the N + conductivity or P + - Conducting interference elements to form the contact zones 5 and 7 or the isolation zone 8 are diffused.
  • a platinum layer 15 preferably by evaporation or sputtering, applied to a thickness of 40 nm.
  • the silicon dioxide layer 9 lying in the opening 13 prevents the platinum in this opening from coming into contact with the substrate.
  • the semiconductor die is then sintered for about 20 minutes at a temperature of 550 ° C. in a nitrogen atmosphere, as a result of which the platinum reacts with the silicon and forms platinum-silicide layers 15 ′ in the openings 12, 13 and 14.
  • the unreacted platinum, including the platinum layer overlying the silicon dioxide layer 10 is then removed by etching with aqua regia.
  • other metals such as palladium, nickel or hafnium can also be used instead of platinum.
  • the part of the silicon dioxide layer 9 lying in the opening 13 is removed by a wet or dry etching process, whereby this part of the substrate is exposed, which is then to form the anode of a Schottky junction diode with a low potential threshold.
  • the new metallization system is then deposited in openings 11 to 14.
  • the preferred detachment method is described in detail in applicant's U.S. Patent 4,004,044. This method is intended to be abbreviated based on the partial fig. 1D - 1F.
  • Other methods of forming the metallization are wet or reactive ion (plasma) etching methods that are generally available to those skilled in the art.
  • plasma reactive ion
  • polyether sulphone is now applied, which facilitates the detachment process.
  • the use of polyether sulphone, or polysulphone for short, is a modification of the method mentioned in the above-mentioned patent and was described in IBM Technical Disclosure Bulletin, Volume 19, No. 4, September 1976, on page 1226.
  • a layer 22 of an organic polymer is applied over the polysulphone layer 20, such as positive photoresist based on Novalak resin, which is subsequently baked or cured at 210-230 ° C. so that the photoresist is no longer photosensitive .
  • a barrier layer 24 consisting of a methyl siloxane resin is applied over the photoresist layer 22 and then a layer 26 of a radiation-sensitive photoresist.
  • the photoresist layer 26 is then used to create a relief-like pattern corresponding to the openings 11, 12, 13 and 14 in the partial FIG. 1C exposed and developed.
  • the photoresist mask 26 is then used for the selective removal of the layers 20, 22 and 24 underneath to expose the openings 11 ', 12', 13 'and 14' in the part of FIG. 1D used, which the in Fig. 1C corresponding openings shown.
  • the exposed substrate including the platinum-silicide layer 15 is subjected to a pre-cleaning under closely monitored radiation conditions with a mixture of 15: 1 or less of water and hydrofluoric acid etchant. A mixing ratio of 5: 1 is most advantageous.
  • the out Pressure "closely monitored radiation conditions" is intended to mean that no noticeable amount of light with a wavelength shorter than 500 nm may be present during this etching process step.
  • the applicant has tried to clean the surface using chemical etching agents under white light in accordance with customary methods. With this known method, however, it was not possible to achieve such a low potential threshold; rather, a potential threshold of approximately 0.61 eV was reached. The applicant has also attempted to clean the semiconductor surface in situ in a sputtering chamber by sputtering. Although this method resulted in a potential threshold of about 0.5 eV, the ideality factor of 1.15 was too high. In addition, this potential threshold could not be repeated exactly.
  • a tantalum layer 28 is applied over the substrate and the release mask. So that a Schottky junction contact with a low potential threshold can actually be achieved, this precipitation of the tantalum layer must likewise be carried out using a very carefully carried out process.
  • the precipitation is best carried out with an electron beam evaporation source, such as that from Airco-Temescal Corp. is supplied as model FC1800. Similar embodiments of evaporation systems are described by others other manufacturers.
  • the highest pressure in the evaporation chamber during the process is 2.5 x 10 6 TORR, the initial pressure in the chamber being less than 4 x 10-7 TORR.
  • the maximum temperature of the substrate is 200 ° C.
  • the pressure specified here is important for the amount of moisture, hydrocarbons and other gaseous contaminants present in the chamber.
  • the precipitation process which runs at a speed of about 0.2 nm per second, continues until a layer thickness of 60 + 15 nm is reached.
  • the tantalum layer produced under these conditions consists of f body-centered cubic crystals.
  • tantalum can also be applied under high pressure and temperature conditions using high frequency sputtering.
  • DC voltage sputtering is not suitable, since tantalum layers applied with DC voltage sputtering consist of body-centered tetragonal crystals, while high-frequency sputtered tantalum is deposited as body-centered cubic crystals.
  • the chrome layer is preferably deposited to a thickness of 60-100 nm. Water vapor must be introduced into the chamber during this evaporation process.
  • the substrate is kept at a maximum temperature of 160 ° C, with no heat being supplied to the substrate.
  • a small amount of chromium is introduced into the boat and water vapor is introduced into the evaporation chamber, the pressure of which is kept at about 10 -5 TORR.
  • the pure chromium in the boat When heated by an electron beam, the pure chromium in the boat is evaporated and converted to commercially available chromium, which is critical for the formation of the barrier layer.
  • the chromium precipitated with the addition of water vapor has chromium oxide at the grain boundaries.
  • the aluminum is preferably deposited down to a layer thickness of 850-1000 nm. One with one. A small amount of copper-doped aluminum is preferable to pure aluminum.
  • the term aluminum is to be used here in such a way that it is also to be understood as meaning copper-doped aluminum and also copper-doped aluminum silicon. The resulting structure shows part-Fig. 1E.
  • the remaining release structure and the overlying metal layer are quickly lifted off using N-methylpyrrolidone or other suitable solvent so that a metallic pattern remains on the surface of the substrate or oxide layer 10 as shown in part-Fig. 1F shows.
  • this structure is sintered for about 1 hour at 400 ° C and then again for another 2 hours at 450 ° C.
  • This sintering process step is important because it at least reduces the interface charges and films between the silicon substrate and the tantalum, but mostly eliminates them. Although these times and temperatures are the most advantageous, other values can also be determined by normal experiments, which may be just as effective. This sintering is necessary in order to reach the potential threshold of 0.5 eV, even if only tantalum is used as the contact material, i.e. H. would have been used without chrome and aluminum.
  • the anode and cathode of the Schottky junction diode with high potential threshold are indicated by reference numerals 34 and 35 in part-Fig. 1F.
  • the anode and cathode of the Schottky junction diode with low potential threshold are denoted by reference numerals 36 and 37, respectively.
  • the cathodes of both diodes are the ohmic contacts leading to the N + -conducting zones 5 and 7 in layer 3.
  • the anode 34 of the Schottky junction diode with a high potential threshold uses a chromium-tantalum metallization between the platinum-silicide layer 15 and the aluminum layer 32, which acts as a diffusion barrier, while the platinum-silicide layer gives an increased potential threshold compared with the anode 36 of the Schottky junction diode with a low potential threshold, where there is no platinum-silicide layer.
  • zone 36 the tantalum layer directly contacts the N-type silicon substrate 3.
  • the tantalum layer is not required when manufacturing a Schottky junction diode with a high potential threshold.
  • a contact made of aluminum, chrome and platinum silicide is completely satisfactory.
  • the chromium layer 30 is critical in that it, as a barrier layer, prevents an interaction between aluminum and tantalum. It is well known that aluminum reacts in an unacceptable manner with silicon and also penetrates platinum silicide for interaction or reaction with silicon. Contrary to all expectations, tantalum and aluminum react with one another in such a way that a film of high resistance is formed during sintering. It is therefore necessary to provide a chrome barrier layer between the aluminum and tantalum layers. As a result, the series resistance is greatly reduced and decreases from about 1 megohm to about 100 ohms. It has also been found that platinum is not suitable as a barrier between aluminum and tantalum because platinum reacts with aluminum, with the result that the aluminum penetrates into the tantalum.
  • Fig. 2 The critical nature of the chromium barrier layer between tantalum and aluminum is very clearly shown in Fig. 2.
  • the diagrams show in percent the change in forward voltage (AVF%) over time for a Schottky barrier diode a composite layer of tantalum and copper-doped aluminum compared to a composite layer of tantalum, chrome and copper-doped aluminum. It can be seen that the latter metallization is four to six times more stable than the former.
  • FIG. 3 shows a diagram of the measured current-voltage characteristic in the forward direction of Schottky junction diodes with high or low potential thresholds, which are constructed according to the invention on the same semiconductor wafer.
  • the anode areas of both Schottky junction diodes are the same.
  • the potential threshold ⁇ B of the Schottky junction diode with a low potential threshold is approximately 0.5 eV.
  • the ideality factor n is approximately 1.10.
  • the potential threshold ⁇ B of the Schottky junction diode with a high potential threshold is approximately 0.8 eV.
  • the ideality factor n is approximately 1.06.
  • the invention is particularly advantageous for integrated circuits in which Schottky junction diodes with a low potential threshold are required.
  • a circuit shown in FIG. 4 is a DTL circuit according to the prior art, which represents a NAND gate.
  • This circuit does not form part of the invention per se and is well known to the person skilled in the art from semiconductor circuit technology. It should be noted here that the invention is in no way limited to this particular circuit or to the arrangement on a semiconductor die. Rather, the invention is applicable to various circuit systems, such as TTL, standard DTL, etc.
  • the circuit contains a single transistor T1 with two bias resistors, which are denoted by RB and RC, and are connected to the base and collector of the transistor T1, and a Schottky junction diode DO acting as a holding diode with a high potential threshold.
  • the circuit has six connectable outputs, in the form of Schottky junction diodes D1, D2, D3, D4, D5 and D6 with a low potential threshold and an ohmic contact on the collector electrode, which is denoted by C.
  • FIG. 5 shows a cross-sectional view of a DTL cell.
  • Each of these cells is present in the same form on a semiconductor wafer several hundred times, as is known to the person skilled in the art of semiconductor technology.
  • Transistor T1 consists of an elongated sub-collector zone 104, a base zone 123 and an emitter zone 124.
  • the Schottky junction diodes D1, D2 ... D6 are arranged symmetrically on each side of the transistor T1 in the epitaxial layer 103.
  • the collector contact C completes the transistor T1.
  • the resistors RB and RC are not shown. As shown in FIG. 5, only those diodes that are actually switched on in the circuit have the novel metallization required to represent these diodes. Therefore, the number of zones actually used, doped with interference elements, is smaller than the maximum number of possible diodes, and the locations of the unused diodes D2 and D6 are shown in broken lines.
  • Diodes D1, D3, D4 and D5 are Schottky junction diodes with a low potential threshold constructed according to the invention. They consist of N-conducting silicon 103, a tantalum layer 128, a chrome layer 130 and an aluminum-copper connection metallization 132 for a ⁇ B of approximately 0.5 eV.
  • the holding diode DO also contains a platinum-silicide layer 115 and delivers a ⁇ B of approximately 0.8 eV.
  • a positive pattern is defined by a positive photoresist, as it is marketed for example by Shipley under the names AZ1350 or AZ111.
  • the now exposed, unnecessary metal layers are removed by conventional wet etching processes for metals in a subtractive process or by placing the substrate in a plasma etching chamber which contains a gas mixture of CCl 4 -Ar for a plasma etching process.

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EP78100525A 1977-08-06 1978-07-27 Procédé pour la fabrication des contacts de tantale sur un substrat semi-conducteur de silicium à conductibilité du type N Expired EP0000743B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/827,912 US4215156A (en) 1977-08-26 1977-08-26 Method for fabricating tantalum semiconductor contacts
US827912 1997-02-20

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Publication Number Publication Date
EP0000743A1 true EP0000743A1 (fr) 1979-02-21
EP0000743B1 EP0000743B1 (fr) 1980-09-17

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US (1) US4215156A (fr)
EP (1) EP0000743B1 (fr)
JP (1) JPS5932069B2 (fr)
CA (1) CA1111570A (fr)
DE (1) DE2860169D1 (fr)
IT (1) IT1158954B (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0017021A1 (fr) * 1979-03-30 1980-10-15 International Business Machines Corporation Procédé de fabrication d'un dispositif semiconducteur comprenant des transistors complémentaires
EP0100999A3 (en) * 1982-08-12 1986-05-14 Siemens Aktiengesellschaft Integrated semiconductor circuit comprising bipolar elements, and method of producing the same
EP0194569A1 (fr) * 1985-03-13 1986-09-17 Siemens Aktiengesellschaft Structure à couche film mince avec une couche intermédiaire réactive pour circuits intégrés
US6183685B1 (en) 1990-06-26 2001-02-06 Littlefuse Inc. Varistor manufacturing method

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4307132A (en) * 1977-12-27 1981-12-22 International Business Machines Corp. Method for fabricating a contact on a semiconductor substrate by depositing an aluminum oxide diffusion barrier layer
US4412376A (en) * 1979-03-30 1983-11-01 Ibm Corporation Fabrication method for vertical PNP structure with Schottky barrier diode emitter utilizing ion implantation
CA1138795A (fr) * 1980-02-19 1983-01-04 Goodrich (B.F.) Company (The) Glissoire d'evacuation et embarcation de sauvetage gonflables combinees
US4425379A (en) 1981-02-11 1984-01-10 Fairchild Camera & Instrument Corporation Polycrystalline silicon Schottky diode array
US4379832A (en) * 1981-08-31 1983-04-12 International Business Machines Corporation Method for making low barrier Schottky devices of the electron beam evaporation of reactive metals
JPS59175763A (ja) * 1983-03-25 1984-10-04 Fujitsu Ltd 半導体装置
JPS6116568A (ja) * 1984-07-03 1986-01-24 Matsushita Electronics Corp シヨツトキ障壁形半導体装置
DE3751755T2 (de) * 1986-06-30 1997-04-03 Nihon Sinku Gijutsu K K Verfahren und Vorrichtung zum Abscheiden aus der Gasphase
DE3751756T2 (de) * 1986-06-30 1996-08-01 Ulvac Corp Verfahren zum Abscheiden aus der Gasphase
JP2620240B2 (ja) 1987-06-10 1997-06-11 株式会社日立製作所 液晶表示装置
US5155565A (en) * 1988-02-05 1992-10-13 Minnesota Mining And Manufacturing Company Method for manufacturing an amorphous silicon thin film solar cell and Schottky diode on a common substrate
US5116464A (en) * 1989-06-02 1992-05-26 Massachusetts Institute Of Technology Cesium hydroxide etch of a semiconductor crystal
US5402254B1 (en) * 1990-10-17 1998-09-22 Hitachi Ltd Liquid crystal display device with tfts in which pixel electrodes are formed in the same plane as the gate electrodes with anodized oxide films before the deposition of silicon
US5221638A (en) * 1991-09-10 1993-06-22 Sanken Electric Co., Ltd. Method of manufacturing a Schottky barrier semiconductor device
JP3562588B2 (ja) * 1993-02-15 2004-09-08 株式会社半導体エネルギー研究所 半導体装置の製造方法
US6997985B1 (en) 1993-02-15 2006-02-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor, semiconductor device, and method for fabricating the same
US6326601B1 (en) * 1999-07-19 2001-12-04 Agilent Technologies, Inc. Optical barrier
US7554829B2 (en) 1999-07-30 2009-06-30 Micron Technology, Inc. Transmission lines for CMOS integrated circuits
DE10011886A1 (de) * 2000-03-07 2001-09-20 Infineon Technologies Ag Verfahren zur Herstellung einer Leiterstruktur für einen integrierten Schaltkreis
US6271068B1 (en) * 2001-01-08 2001-08-07 Taiwan Semiconductor Manufacturing Company Method for making improved polysilicon emitters for bipolar transistors on BiCMOS integrated circuits
US6852167B2 (en) 2001-03-01 2005-02-08 Micron Technology, Inc. Methods, systems, and apparatus for uniform chemical-vapor depositions
US8026161B2 (en) 2001-08-30 2011-09-27 Micron Technology, Inc. Highly reliable amorphous high-K gate oxide ZrO2
US6844203B2 (en) 2001-08-30 2005-01-18 Micron Technology, Inc. Gate oxides, and methods of forming
US6953730B2 (en) 2001-12-20 2005-10-11 Micron Technology, Inc. Low-temperature grown high quality ultra-thin CoTiO3 gate dielectrics
US6900122B2 (en) * 2001-12-20 2005-05-31 Micron Technology, Inc. Low-temperature grown high-quality ultra-thin praseodymium gate dielectrics
US6767795B2 (en) * 2002-01-17 2004-07-27 Micron Technology, Inc. Highly reliable amorphous high-k gate dielectric ZrOXNY
US6812100B2 (en) * 2002-03-13 2004-11-02 Micron Technology, Inc. Evaporation of Y-Si-O films for medium-k dielectrics
US7045430B2 (en) 2002-05-02 2006-05-16 Micron Technology Inc. Atomic layer-deposited LaAlO3 films for gate dielectrics
US7589029B2 (en) 2002-05-02 2009-09-15 Micron Technology, Inc. Atomic layer deposition and conversion
US7160577B2 (en) 2002-05-02 2007-01-09 Micron Technology, Inc. Methods for atomic-layer deposition of aluminum oxides in integrated circuits
US7205218B2 (en) * 2002-06-05 2007-04-17 Micron Technology, Inc. Method including forming gate dielectrics having multiple lanthanide oxide layers
US7135421B2 (en) 2002-06-05 2006-11-14 Micron Technology, Inc. Atomic layer-deposited hafnium aluminum oxide
US6804136B2 (en) 2002-06-21 2004-10-12 Micron Technology, Inc. Write once read only memory employing charge trapping in insulators
US7193893B2 (en) 2002-06-21 2007-03-20 Micron Technology, Inc. Write once read only memory employing floating gates
US7221586B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide nanolaminates
US7221017B2 (en) 2002-07-08 2007-05-22 Micron Technology, Inc. Memory utilizing oxide-conductor nanolaminates
US6921702B2 (en) 2002-07-30 2005-07-26 Micron Technology Inc. Atomic layer deposited nanolaminates of HfO2/ZrO2 films as gate dielectrics
US6884739B2 (en) * 2002-08-15 2005-04-26 Micron Technology Inc. Lanthanide doped TiOx dielectric films by plasma oxidation
US6790791B2 (en) 2002-08-15 2004-09-14 Micron Technology, Inc. Lanthanide doped TiOx dielectric films
US20040036129A1 (en) * 2002-08-22 2004-02-26 Micron Technology, Inc. Atomic layer deposition of CMOS gates with variable work functions
US6967154B2 (en) 2002-08-26 2005-11-22 Micron Technology, Inc. Enhanced atomic layer deposition
US7199023B2 (en) 2002-08-28 2007-04-03 Micron Technology, Inc. Atomic layer deposited HfSiON dielectric films wherein each precursor is independendently pulsed
US7101813B2 (en) 2002-12-04 2006-09-05 Micron Technology Inc. Atomic layer deposited Zr-Sn-Ti-O films
US6958302B2 (en) * 2002-12-04 2005-10-25 Micron Technology, Inc. Atomic layer deposited Zr-Sn-Ti-O films using TiI4
US7192892B2 (en) 2003-03-04 2007-03-20 Micron Technology, Inc. Atomic layer deposited dielectric layers
US7220665B2 (en) * 2003-08-05 2007-05-22 Micron Technology, Inc. H2 plasma treatment
US6955932B2 (en) * 2003-10-29 2005-10-18 International Business Machines Corporation Single and double-gate pseudo-FET devices for semiconductor materials evaluation
US20050233477A1 (en) * 2004-03-05 2005-10-20 Tokyo Electron Limited Substrate processing apparatus, substrate processing method, and program for implementing the method
US7498247B2 (en) 2005-02-23 2009-03-03 Micron Technology, Inc. Atomic layer deposition of Hf3N4/HfO2 films as gate dielectrics
US7687409B2 (en) 2005-03-29 2010-03-30 Micron Technology, Inc. Atomic layer deposited titanium silicon oxide films
US7662729B2 (en) 2005-04-28 2010-02-16 Micron Technology, Inc. Atomic layer deposition of a ruthenium layer to a lanthanide oxide dielectric layer
US20070013014A1 (en) * 2005-05-03 2007-01-18 Shuwen Guo High temperature resistant solid state pressure sensor
US7400042B2 (en) * 2005-05-03 2008-07-15 Rosemount Aerospace Inc. Substrate with adhesive bonding metallization with diffusion barrier
US7628309B1 (en) * 2005-05-03 2009-12-08 Rosemount Aerospace Inc. Transient liquid phase eutectic bonding
US7538401B2 (en) * 2005-05-03 2009-05-26 Rosemount Aerospace Inc. Transducer for use in harsh environments
US7927948B2 (en) 2005-07-20 2011-04-19 Micron Technology, Inc. Devices with nanocrystals and methods of formation
JP2009514602A (ja) * 2005-11-02 2009-04-09 セカンド サイト メディカル プロダクツ インコーポレイテッド 植え込み型マイクロ電子デバイス及びその作製方法
US7709402B2 (en) 2006-02-16 2010-05-04 Micron Technology, Inc. Conductive layers for hafnium silicon oxynitride films
US7563730B2 (en) 2006-08-31 2009-07-21 Micron Technology, Inc. Hafnium lanthanide oxynitride films

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2029236A1 (de) * 1969-06-20 1971-01-07 Texas Instruments Ine , Dallas, Tex (V St A) Av alanche Diode mit Schottky Sperr schicht und Verfahren zu ihrer Herstellung
DE2104672A1 (de) * 1970-02-02 1971-08-19 Ibm Planare Halbleitervorrichtung, insbe sondere integrierte Halbleiterschaltung, mit am Halbleiterkörper oder am Halb leitersubstrat eingebauten metallischen Verbindungsleiterstreifen
US3662458A (en) * 1969-06-20 1972-05-16 Westinghouse Electric Corp Electrical contact for silicon carbide members
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
US3906540A (en) * 1973-04-02 1975-09-16 Nat Semiconductor Corp Metal-silicide Schottky diode employing an aluminum connector
FR2324124A1 (fr) * 1975-09-09 1977-04-08 Philips Nv Procede pour la realisation d'un dispositif de transmission de charge et dispositif de charge ainsi realise

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3442012A (en) * 1967-08-03 1969-05-06 Teledyne Inc Method of forming a flip-chip integrated circuit
US3567508A (en) * 1968-10-31 1971-03-02 Gen Electric Low temperature-high vacuum contact formation process
US3820236A (en) * 1969-06-20 1974-06-28 Texas Instruments Inc Method of making metal semiconductor diodes having plated heat sink members
US3663279A (en) * 1969-11-19 1972-05-16 Bell Telephone Labor Inc Passivated semiconductor devices
US3641402A (en) * 1969-12-30 1972-02-08 Ibm Semiconductor device with beta tantalum-gold composite conductor metallurgy
US3967371A (en) * 1970-01-06 1976-07-06 Sescosem- Societe Europeenne Des Semi-Conducteurs Et De Microelectronique Methods of manufacturing multilayer interconnections for integrated circuits and to integrated circuits utilizing said method
US3652905A (en) * 1970-05-26 1972-03-28 Westinghouse Electric Corp Schottky barrier power rectifier
DE2057204C3 (de) * 1970-11-20 1975-02-27 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung von Metall-Halbleiterkontakten
US3939047A (en) * 1971-11-15 1976-02-17 Nippon Electric Co., Ltd. Method for fabricating electrode structure for a semiconductor device having a shallow junction
JPS557020B2 (fr) * 1971-11-15 1980-02-21
NL163370C (nl) * 1972-04-28 1980-08-15 Philips Nv Werkwijze voor het vervaardigen van een halfgeleider- inrichting met een geleiderpatroon.
US3923975A (en) * 1973-10-09 1975-12-02 Cutler Hammer Inc Tantalum-gallium arsenide schottky barrier semiconductor device
US4035208A (en) * 1974-09-03 1977-07-12 Texas Instruments Incorporated Method of patterning Cr-Pt-Au metallization for silicon devices
JPS5136878A (en) * 1974-09-14 1976-03-27 Tokyo Shibaura Electric Co Handotaisochi no seizohoho

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2029236A1 (de) * 1969-06-20 1971-01-07 Texas Instruments Ine , Dallas, Tex (V St A) Av alanche Diode mit Schottky Sperr schicht und Verfahren zu ihrer Herstellung
US3662458A (en) * 1969-06-20 1972-05-16 Westinghouse Electric Corp Electrical contact for silicon carbide members
DE2104672A1 (de) * 1970-02-02 1971-08-19 Ibm Planare Halbleitervorrichtung, insbe sondere integrierte Halbleiterschaltung, mit am Halbleiterkörper oder am Halb leitersubstrat eingebauten metallischen Verbindungsleiterstreifen
US3906540A (en) * 1973-04-02 1975-09-16 Nat Semiconductor Corp Metal-silicide Schottky diode employing an aluminum connector
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
FR2324124A1 (fr) * 1975-09-09 1977-04-08 Philips Nv Procede pour la realisation d'un dispositif de transmission de charge et dispositif de charge ainsi realise

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 14, April 1972, New York: M. REVITZ et al: "Metallurgy barrier for Au and Pb", Seite 3358 *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, April 1974, New York: T.M. REITH et al.: "Al/Pt Si Schottky Barrier Diodes with a diffusion Barrier", Seite 3586 *

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0017021A1 (fr) * 1979-03-30 1980-10-15 International Business Machines Corporation Procédé de fabrication d'un dispositif semiconducteur comprenant des transistors complémentaires
EP0100999A3 (en) * 1982-08-12 1986-05-14 Siemens Aktiengesellschaft Integrated semiconductor circuit comprising bipolar elements, and method of producing the same
EP0194569A1 (fr) * 1985-03-13 1986-09-17 Siemens Aktiengesellschaft Structure à couche film mince avec une couche intermédiaire réactive pour circuits intégrés
US6183685B1 (en) 1990-06-26 2001-02-06 Littlefuse Inc. Varistor manufacturing method

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CA1111570A (fr) 1981-10-27
JPS5436178A (en) 1979-03-16
IT1158954B (it) 1987-02-25
JPS5932069B2 (ja) 1984-08-06
IT7826099A0 (it) 1978-07-26
EP0000743B1 (fr) 1980-09-17
DE2860169D1 (en) 1980-12-18
US4215156A (en) 1980-07-29

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