EP0031995B1 - Halbleiterspeicheranordnung mit matrixartig angeordneten statischen Speicherzellen - Google Patents

Halbleiterspeicheranordnung mit matrixartig angeordneten statischen Speicherzellen Download PDF

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Publication number
EP0031995B1
EP0031995B1 EP80304189A EP80304189A EP0031995B1 EP 0031995 B1 EP0031995 B1 EP 0031995B1 EP 80304189 A EP80304189 A EP 80304189A EP 80304189 A EP80304189 A EP 80304189A EP 0031995 B1 EP0031995 B1 EP 0031995B1
Authority
EP
European Patent Office
Prior art keywords
amplifier circuit
ram device
latch amplifier
memory cells
latch
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP80304189A
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English (en)
French (fr)
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EP0031995A2 (de
EP0031995A3 (en
Inventor
Setsuo Kurafuji
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Fujitsu Ltd
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Fujitsu Ltd
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Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of EP0031995A2 publication Critical patent/EP0031995A2/de
Publication of EP0031995A3 publication Critical patent/EP0031995A3/en
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Publication of EP0031995B1 publication Critical patent/EP0031995B1/de
Expired legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
    • G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
    • G11C11/419—Read-write [R-W] circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
    • G11C11/412—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger using field-effect transistors only

Definitions

  • the present invention relates to a semiconductor RAM (Random Access Memory) device, more particularly to a static-type RAM device.
  • a semiconductor RAM Random Access Memory
  • a semiconductor memory having a sense amplifier, or latch is disclosed in US-A-3879621, in which a plurality of row lines permits the selection of individual memory cells of a column of memory cells for read-out.
  • the sense amplifier is connected to bit lines of the column through gate circuits.
  • the bit lines are precharged and the gate circuits, in response to control signal, couple the sense amplifier to the bit lines, so that the sense amplifier .tracks the bit line potential when a bit line is discharged by the selection of a memory cell by a row line. Thereafter, the gate circuits disconnect the sense amplifier from the bit lines, and thereby isolate the bit lines.
  • the amplitude of a read-out signal from a memory cell becomes small, so that the reliability of the read-out data is decreased; and the time necessary to change the potential on each of the bit lines and the data bus lines becomes large, because it takes a long time to charge or discharge the stray capacitance of these lines by a memory cell having a small drive capacity. Therefore, the read-out time of the RAM device increases according to the increase in the integration degree of the RAM device.
  • the present invention consists in a semiconductor RAM device having a plurality of static-type memory cells which are disposed in a matrix of rows and columns and each of which is selected by an output from a row decoder and an output from a column decoder in response to input address signals and comprising a latch amplifier circuit coupled to the memory cells through gate circuits which are operated by a control pulse so that the latch amplifier circuit receives, through the gate circuits a data signal corresponding to the state of a selected memory cell, characterized in that a separate latch amplifier circuit is provided for each column and in that the device further comprises a control pulse generating circuit which, in response to a potential change of at least one of the input address signals, generates the control pulse after a predetermined delay, and in that the latch amplifier circuit is activated after the data signal has been fed to the latch amplifier circuit through the gate circuits under the control of the control pulse.
  • the amplifier circuits have a larger drive capacity than that of the memory cells, so as to prevent the slow down of the read-out speed of such a device
  • Fig. 1 illustrates a static type semiconductor RAM device in accordance with an embodiment of the present invention.
  • memory cells MC 00 through MC NN are disposed in a matrix of N rows by N columns and each of the memory cells consists mainly of a flip-flop, which will be explained later in detail.
  • Word lines W o through W N are connected to X address (or row address) decoders XD o through XD N respectively, and each of the word lines W o through W N is selected by corresponding one of the output signals X o through X N from the X address decoders XD o through XD N .
  • a plurality of bit line pairs B o , B o through B N , B N are crossed with a plurality of the word lines W o through W N to form the matrix.
  • one of the memory cells MC oo through MC NN is connected between a bit line pair and a word line.
  • These bit line pairs B 0 , B 0 through B N , B N are connected to latch circuits or amplifier circuits RA o through RA N respectively, according to the present invention. All the latch circuits RA 0 through RA N have the same structure, and therefore only the latch circuit RA 0 will be explained hereinafter.
  • the latch circuit RA 0 comprises load transistors Q 1 , Q 2 and driver transistors Q 3 , Q 4 which compose a flip-flop.
  • the latch circuit RA 0 further comprises gate transistors Q 5 and Q 6 connected between the bit line pair B o , B o and the flip-flop, and a switching transistor Q 7 .
  • the switching transistor Q 7 and the load transistors Q 1 and Q 2 are turned on and off by a signal Y 0D which is a delayed signal of an output signal Y o from a Y address (or column address) decoder, not shown in the drawing.
  • the gate transistors Q 5 and Q 6 are turned on and off by a delayed gate signal WDD produced in a gate signal generator, which will be explained later.
  • the latch circuits RA 0 through RA N are selected by the delayed gate signal WDD and the delayed output signal Y OD through Y ND of the output signal Y o through Y N from the Y address decoders, not shown in the drawing.
  • the flip-flop of each of the above-mentioned latch circuits RA 0 through RA N has the same structure as that of each of the memory cells MC oo through MC NN , which will be explained later.
  • the drive capacity of the driver transistors Q 3 and Q 4 of each of the latch circuits is larger than that of the driver transistors of the flip-flop contained in each of the memory cells MC oo through MC NN . Therefore, for example, the size of the driver transistors Q 3 and Q 4 of each of the latch circuits is larger than that of the driver transistors of each of the memory cells MC oo through MC NN .
  • Fig. 2 illustrates a memory cell for example MC oo , used in the circuit of Fig. 1.
  • the memory cell MC oo comprises load transistors Q 21 , Q 22 and driver transistors Q 23 , Q 24 which compose a flip-flop, and gate transistors Q 25 , Q 26 which are turned on and .off by the output signal, i.e., decoded address signal X o from the X address decoder XD 0 .
  • the gate transistors Q 25 and Q 26 are turned on due to the supply of a decoded address signal X o of high potential level, and transfer of information between the bit lines B o , B o and the flip-flop of the memory cell MC oo is effected.
  • Fig. 3 illustrates a gate signal generator which produces a delayed gate signal WDD and which comprises a detector circuit DXD consisting of trigger pulse generators TG 01 , TG 02 , ..., TG M1 , TG M2 , OR gates OG o , ..., OG M , OG oo and an inverter INV, and, a delay circuit TD.
  • Each of the trigger pulse generators TG 01 through TG M2 detects potential change, i.e.
  • OR gates OG 0 through OG M and an OR gate OG oo effect the logical "or" operation of the trigger pulses To, T' o , ..., T M , T' M .
  • the inverter INV inverts an output signal from the OR gate OG oo and produces a gate. signal T.
  • a delay circuit TD delays the gate signal T for a predetermined time period and produces the delayed gate signal WDD, which was mentioned before.
  • the delay time of the delay circuit TD is a time in which the output signal X o , ..., X N-1 or X N respectively reaches from the X address decoder XD 0 , ..., XD N-1 , or XD N to the farthest end of the word line W 0 , ..., W N-1 or W N , i.e., a portion of the word line to which the memory cell MC 0N , ..., MC N-1 N or MC NN is connected in the embodiment of Fig. 1.
  • the delay circuit TD can be constructed by using a dummy word line which has approximately the same length as that of each of the word lines W o through W N and which is disposed parallel to the word lines W o through W N .
  • each of the trigger pulse generators TG 01 , through TG M2 can be constructed by using, for example, a differentiation circuit and a wave shaping circuit.
  • a part of the address signals A o , A o , ..., A M , A M are applied to the X address decoders XD 0 through XD N and a part of the address signals are applied to Y address decoders, which are not shown in the drawings.
  • the output X o from the X address decoder XD 0 turns to high and the output Y o from the Y address decoder turns to high.
  • At least two of the address signals A o , A o , ..., AM, A M change their potential level, as illustrated by A of Fig. 4.
  • This change of the potential level may be of a potential rise or a potential fall.
  • the detector circuit DXD In response to the change of the potential level of at least one address signal, the detector circuit DXD generates a gate signal T as illustrated in Fig. 4.
  • the delay circuit TD delays the gate signal T and produces the delayed gate signal WDD, as illustrated in Fig. 4.
  • the delayed gate signal WDD is applied to the gate electrodes of the transistors Q 5 and Q 6 of the latch circuits RA 0 through RA N .
  • the potential of all portions of the selected word line W o has already risen to a high level. Therefore, the information from the memory cell MC oo , which is disposed in the nearest position from the X address decoder XD 0 in Fig. 1, has already been read out to the bit line pair B o , B o . That is, the potentials of the point A and the point B in the memory cell MC oo has already been transferred to the bit lines B o and B o respectively.
  • the gate transistors Q 5 and Q 6 are turned on by the delayed gate signal WDD and the information of the memory cell MC oo , i.e. the potentials of the point A and the point B of the memory cell MC oo , is input to the latch circuit RA o through the gate transistors Q 5 and Q 6 .
  • the delayed gate signal WDD is applied to the gate transistors Q 5 and Q 6
  • the delayed Y decoder signal Y 0D is applied to the gate electrodes of the switching transistor Q 7 and the load transistors Q 1 and Q 2 of the latch circuit RA o , so that the latch circuit RA o is activated, due to the supply of an operating voltage.
  • the latch circuit RA o is set to a condition determined by the input potentials, i.e. the potentials of the bit lines B o and B o , so that the transferring of information to the latch circuit RA o is effected.
  • the input potentials i.e. the potentials of the bit lines B o and B o
  • stray capacitances existing between the input circuit portion of the latch circuit RA 0 and the ground are charged by the potentials of the bit lines B o and B o . Therefore, even if the delayed Y decoder signal Y oo is applied to the latch circuit RA 0 a short time after the delayed gate signal WDD has changed from high potential to low potential, as illustrated in Fig.
  • the latch circuit RA 0 it is possible to set the latch circuit RA 0 to a condition determined by the potentials of the bit lines B o and B o . It should be noted that the delayed gate signal WDD and the delayed Y decoder signal Y 0D are needed in order to prevent the destruction of data in the memory cell MC oo .
  • the memory cell MC oo having a small drive capacity is written-in by the potentials of the bit lines B o and B o which are determined by the condition of the latch circuit RA 0 at the time the memory cell MC oo is selected.
  • Fig. 5 illustrates an example of a sense amplifier SA which is used in the memory device of Fig. 1.
  • the sense amplifier SA comprises a pair of transistors Q 50 and Q 51 composing a differential amplifier, a pair of load transistors Q 12 and Q 53 , and a transistor Q 54 composing a constant current source.
  • the gate electrodes of the transistors Q 50 and Q 51 are respectively connected to the output terminals of the latch circuits RA 0 through RA N through data bus lines which are not shown in the drawings. Therefore, the output signals D and D of the latch circuit, for example, RA 0 are respectively applied to the gate electrodes of the transistors Q 50 and Q 51 , and amplified by the sense amplifier SA.
  • the sense amplifier SA provides output signals O and O as the read-out signals from the memory device.
  • the data bus lines and the sense amplifier are driven by the latch circuits, whose driver transistors are big in size, so as to obtain a large drive capacity so that it is possible to increase the read-out speed and to improve the reliability of the read-out data of the static type RAM device. Therefore, it is not necessary to use memory cells having big sizes and a latch circuit is provided for every column, so that the integration degree of the RAM device is not so much decreased.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Static Random-Access Memory (AREA)
  • Dram (AREA)

Claims (7)

1. Halbletier-RAM-Vorrichtung mit einer Vielzahl von statischen Speicherzellen (MC), welche in einer Matrix aus Reihen und Spalten angeordnet sind und von denen jede durch einen Ausgang (Xo, Xn) eines Reihendecoders (XDo, XDn) und eines Ausgangs eines Spaltendecoders in Abhängigkeit von Eingangsdressensignalen (Ao, Ao; Am, Am; Fig. 3) ausgewählt wird, und mit einer Halteverstärkerschaltung (RAo, RAn), welche mit den Speicherzellen über Torschaltungen (Q5, Q6) verbunden ist, die durch einen Steuerimpuls (WDD) betätigt werden so daß die Halteverstärkerschaltung über die Torschaltungen ein Datensignal empfängt, welches dem Zustand einer ausgewählten Speicherzelle entspricht, dadurch gekennzeichnet, daß eine separate Halteverstärkerschaltung für jede Spalte vorgesehen ist und daß die Vorrichtung ferner eine Steuerimpulsgeneratorschaltung (DXD, TD) umfaßt, welche in Abhängigkeit von der Potentialänderung von wenigstens einem der genannten Adressensignale den genannten Steuerimpuls (WDD) nach einer vorbestimmten Verzögerung erzeugt, und daß die Halteverstärkerschaltung. aktiviert wird, nachdem das Datensignal über die Torschaltungen (Q5, Q6) unter der Steuerung des Steuerimpulses (WDD) der Halteverstärkerschaltung zugeführt worden ist.
2. Halbleiter-RAM-Vorrichtung nach Anspruch 1, bei welcher die vorbestimmte Verzögerung etwa gleich der Zeit ist, welche das Ausgangssignal (Xo, Xn) des Reihendecoders benötigt, um die Speicherzelle (MCon, MCnn) zu erreichen, welche mit dem entferntesten Ende einer Wortleitung (Wo, Wn) verbunden ist.
3. Halbleiter-RAM-Vorrichtung nach Anspruch 1 oder 2, bei welcher die Halteverstärkerschaltung (RAo, RAn) durch eine verzögertes (YOD, YND) Signal aktiviert wird, welches von dem Ausgangssignal des Spaltendecoders abgeleitet ist.
4. Halbleiter-RAM-Vorrichtung nach Anspruch 3, bei welcher die Halteverstärkerschaltung (RAo, RAn) umfaßt: eine Paar von Lasttransistoren (Q1, Q2), deren Basen beide zum Empfang des genannten vorzögerten Signals (Yoo) angeschlossen sind, welches von dem Ausgangssignal des Spaltendecoders abgeleitet ist; ein Flip-Flop, welches ein Paar von Treibertransistoren (Q3, Q4) umfaßt, die mit den genannten Lasttransistoren und mit den genannten Torschaltungen (Q5, Q6) und einem Schalttransistor (Q7) verbunden sind, dessen Basis zum Empfang des genannten verzögerten Signals (Yop) angeschlossen ist, um die Verbindung des Flip-Flops mit einem Referenzpotential (GND) und dadurch die Aktivierung der Halteverstärkerschaltung zu steuern.
5. Halbleiter-RAM-Vorrichtung nach Anspruch 4, bei welcher jeder der Treibertransistoren (Q3, Q4) der Halteverstärkerschaltung (RAo, RAn) eine größere Treiberkapazität als die Treibertransistoren (Q23, Q24) der Speicherzellen (MC) hat.
6. Halbleiter-RAM-Vorrichtung nach Anspruch 4 oder 5, bei welcher jeder der Treibertransistoren (Q3, Q4) der Halteverstärkerschaltung (RAo, RAn) eine größere Größe als die Treibertransistoren (Q23, Q24) der Speicherzellen (MC) hat.
7. Halbleiter-RAM-Vorrichtung nach einem der vorhergehenden Ansprüche, ferner mit einem Leseverstärker (SA), der mit jeder Halteverstärkerschaltung (RAo, RAn), verbunden ist und auf Datensignale (D, D) von den Halteverstärkerschaltungen anspricht, um Auslesesignale (O, Ö) zu erzeugen.
EP80304189A 1979-11-29 1980-11-21 Halbleiterspeicheranordnung mit matrixartig angeordneten statischen Speicherzellen Expired EP0031995B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP154578/79 1979-11-29
JP54154578A JPS59915B2 (ja) 1979-11-29 1979-11-29 メモリ回路

Publications (3)

Publication Number Publication Date
EP0031995A2 EP0031995A2 (de) 1981-07-15
EP0031995A3 EP0031995A3 (en) 1982-11-17
EP0031995B1 true EP0031995B1 (de) 1986-02-26

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Application Number Title Priority Date Filing Date
EP80304189A Expired EP0031995B1 (de) 1979-11-29 1980-11-21 Halbleiterspeicheranordnung mit matrixartig angeordneten statischen Speicherzellen

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US (1) US4400800A (de)
EP (1) EP0031995B1 (de)
JP (1) JPS59915B2 (de)
CA (1) CA1174762A (de)
DE (1) DE3071458D1 (de)
IE (1) IE51438B1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5838873B2 (ja) * 1980-10-15 1983-08-25 富士通株式会社 センス回路
JPS57141097A (en) * 1981-02-25 1982-09-01 Toshiba Corp Storage circuit
DE3582376D1 (de) * 1984-08-03 1991-05-08 Toshiba Kawasaki Kk Halbleiterspeicheranordnung.
US4636991A (en) * 1985-08-16 1987-01-13 Motorola, Inc. Summation of address transition signals
JPH0831275B2 (ja) * 1986-09-09 1996-03-27 日本電気株式会社 メモリ回路
JPH01174563U (de) * 1988-05-30 1989-12-12
US5023842A (en) * 1988-07-11 1991-06-11 Kabushiki Kaisha Toshiba Semiconductor memory having improved sense amplifiers
DE4107420C2 (de) * 1991-03-08 2002-08-14 Zentr Mikroelekt Dresden Gmbh Schreib-Lese-Schaltung für einen statischen RAM
US7102946B2 (en) * 2005-02-09 2006-09-05 International Business Machines Corporation Local bit select circuit with slow read recovery scheme

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3879621A (en) * 1973-04-18 1975-04-22 Ibm Sense amplifier
JPS538528A (en) * 1976-07-12 1978-01-26 Nec Corp Memory circuit
JPS5472641A (en) * 1977-11-21 1979-06-11 Toshiba Corp Voltage detection circuit

Also Published As

Publication number Publication date
JPS59915B2 (ja) 1984-01-09
US4400800A (en) 1983-08-23
EP0031995A2 (de) 1981-07-15
CA1174762A (en) 1984-09-18
JPS5677982A (en) 1981-06-26
EP0031995A3 (en) 1982-11-17
IE51438B1 (en) 1986-12-24
IE802439L (en) 1981-05-29
DE3071458D1 (en) 1986-04-03

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