EP0034168A1 - Procede de recuit a l'hydrogene pour un dispositif de memoire de porte au silicium - Google Patents

Procede de recuit a l'hydrogene pour un dispositif de memoire de porte au silicium

Info

Publication number
EP0034168A1
EP0034168A1 EP80901693A EP80901693A EP0034168A1 EP 0034168 A1 EP0034168 A1 EP 0034168A1 EP 80901693 A EP80901693 A EP 80901693A EP 80901693 A EP80901693 A EP 80901693A EP 0034168 A1 EP0034168 A1 EP 0034168A1
Authority
EP
European Patent Office
Prior art keywords
terized
charac
process according
vessel
temperature
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP80901693A
Other languages
German (de)
English (en)
Other versions
EP0034168A4 (fr
Inventor
Murray Lawrence Trudel
Vinod Kumar Central Park Apartments Apt. 92 Dham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0034168A1 publication Critical patent/EP0034168A1/fr
Publication of EP0034168A4 publication Critical patent/EP0034168A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H10P95/94—Hydrogenation or deuterisation, e.g. using atomic hydrogen from a plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates

Definitions

  • SNOS silicon (polysilicon)-nitride-oxide- semiconductor.
  • silicon gate memory structures frequently have relatively low retention and endurance as compared to metal gate struc ⁇ tures (such as aluminum or aluminum alloy metal gate structures).
  • metal gate struc ⁇ tures such as aluminum or aluminum alloy metal gate structures.
  • the article relates to improved SONOS structures and discusses the relatively poor retention of silicon gate structures: for example, Chen indicated that 15 Angstrom thick gate oxide provides retention measured in years in typical MNOS structures, but only in hours in SONOS structures. Chen increased the retention of his SONOS devices by increasing the thickness of the gate oxide to 30 Angstroms. However increasing the gate oxide thickness has the disadvantage of slowing write and erase speeds.
  • a process for manufacturing a semi ⁇ conductor non-volatile memory device of the kind speci ⁇ fied characterized by the steps of loading the device into an annealing vessel, raising the temperature of the vessel to within the range 600-1100°C. in hydrogen ambient, maintaining the temperature and hydrogen ambient for a sufficient time to anneal the device, and reducing the temperature of the vessel to about 100°C. or less while maintaining the hydrogen ambient.
  • source 17 and drain 18 are formed in ⁇ silicon substrate 16 by n-type impurities such as phosphorus (or p-type impurities such as boron for p-channel) using diffusion or ion implantation techniques.
  • Field oxide 21 can be formed by wet thermal oxidation of the substrate 16, to a typical thickness of 14kA to 16kA (14,000 to 16,000 Angstroms).
  • Memory gate oxide 11 of thickness 10-30 Angstroms is preferably formed by dry thermal oxidation, typically within the approximate range 600-750°C. in an oxygen-nitrogen ambient.
  • the memory memory nitride 12 can be deposited by the chem- ical vapor deposition technique in a vertical reactor at a temperature of about 700-750°C. using an ammonia- silane-nitrogen ambient, to a thickness of about 350- 550 Angstroms.
  • step 1 the loading step
  • pre-condi ⁇ tion clean the bell jar 41 by heating to about 900°C. and maintaining the temperature for about 15 minutes in the presence of nitrogen (flow rates of about 48 liters/ min. have been used) , then shutting off the temperature and gas flow.
  • step 3 was done at room 5 temperature using an applied gate voltage of +_ 25 volts and a 10 millisecond pulse width for both polarities.
  • the source, drain and substrate were all tied to ground during the write-erase cycling.

Landscapes

  • Non-Volatile Memory (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Dans un procede de fabrication d'un dispositif de memoire SNOF ou FONOS remanent semi-conducteur ayant une structure de porte qui comprend une couche d'oxyde de porte (11) disposee sur un substrat semi-conducteur (16), une couche de nitrure (12) formee sur la couche d'oxyde de porte (11) et une electrode de porte de polysilicium (14) recouvrant la couche de nitrure (12), le dispositif est recuit dans l'hydrogene, dans un recipient de recuit (40), d'une maniere caracteristique pendant 15-60 minutes a 600-1100 C.
EP19800901693 1979-08-13 1981-02-24 Procede de recuit a l'hydrogene pour un dispositif de memoire de porte au silicium. Withdrawn EP0034168A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6580679A 1979-08-13 1979-08-13
US65806 1979-08-13

Publications (2)

Publication Number Publication Date
EP0034168A1 true EP0034168A1 (fr) 1981-08-26
EP0034168A4 EP0034168A4 (fr) 1981-12-10

Family

ID=22065234

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19800901693 Withdrawn EP0034168A4 (fr) 1979-08-13 1981-02-24 Procede de recuit a l'hydrogene pour un dispositif de memoire de porte au silicium.

Country Status (3)

Country Link
EP (1) EP0034168A4 (fr)
JP (1) JPS56501028A (fr)
WO (1) WO1981000487A1 (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4448633A (en) * 1982-11-29 1984-05-15 United Technologies Corporation Passivation of III-V semiconductor surfaces by plasma nitridation
US5229311A (en) * 1989-03-22 1993-07-20 Intel Corporation Method of reducing hot-electron degradation in semiconductor devices
GB2229575B (en) * 1989-03-22 1993-05-12 Intel Corp Method of reducing hot-electron degradation in semiconductor devices
WO1991011022A1 (fr) * 1990-01-10 1991-07-25 Australian Nuclear Science & Technology Organisation Purification d'un materiau semi-conducteur
JP3516596B2 (ja) * 1998-10-19 2004-04-05 松下電器産業株式会社 半導体装置の製造方法
CN102800584A (zh) * 2012-08-29 2012-11-28 上海宏力半导体制造有限公司 提高sonos闪存可靠性的方法

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1261723A (en) * 1968-03-11 1972-01-26 Associated Semiconductor Mft Improvements in and relating to semiconductor devices
US3556880A (en) * 1968-04-11 1971-01-19 Rca Corp Method of treating semiconductor devices to improve lifetime
US3615873A (en) * 1969-06-03 1971-10-26 Sprague Electric Co Method of stabilizing mos devices
US3719866A (en) * 1970-12-03 1973-03-06 Ncr Semiconductor memory device
US3867196A (en) * 1974-03-11 1975-02-18 Smc Microsystems Corp Method for selectively establishing regions of different surface charge densities in a silicon wafer
US4027380A (en) * 1974-06-03 1977-06-07 Fairchild Camera And Instrument Corporation Complementary insulated gate field effect transistor structure and process for fabricating the structure
US4057821A (en) * 1975-11-20 1977-11-08 Nitron Corporation/Mcdonnell-Douglas Corporation Non-volatile semiconductor memory device
US4097314A (en) * 1976-12-30 1978-06-27 Rca Corp. Method of making a sapphire gate transistor
US4151007A (en) * 1977-10-11 1979-04-24 Bell Telephone Laboratories, Incorporated Hydrogen annealing process for stabilizing metal-oxide-semiconductor structures
NL7902247A (nl) * 1978-03-25 1979-09-27 Fujitsu Ltd Metaal-isolator-halfgeleidertype halfgeleiderinrich- ting en werkwijze voor het vervaardigen ervan.
JPS5530846A (en) * 1978-08-28 1980-03-04 Hitachi Ltd Method for manufacturing fixed memory

Also Published As

Publication number Publication date
EP0034168A4 (fr) 1981-12-10
WO1981000487A1 (fr) 1981-02-19
JPS56501028A (fr) 1981-07-23

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

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AK Designated contracting states

Designated state(s): DE GB NL

17P Request for examination filed

Effective date: 19810717

DET De: translation of patent claims
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION HAS BEEN WITHDRAWN

18W Application withdrawn

Withdrawal date: 19820622

RIN1 Information on inventor provided before grant (corrected)

Inventor name: DHAM, VINOD KUMARCENTRAL PARK APARTMENTS, APT. 92

Inventor name: TRUDEL, MURRAY LAWRENCE