EP0035558A1 - Dispositif de memoire remanente a porte de silicium - Google Patents

Dispositif de memoire remanente a porte de silicium

Info

Publication number
EP0035558A1
EP0035558A1 EP80901882A EP80901882A EP0035558A1 EP 0035558 A1 EP0035558 A1 EP 0035558A1 EP 80901882 A EP80901882 A EP 80901882A EP 80901882 A EP80901882 A EP 80901882A EP 0035558 A1 EP0035558 A1 EP 0035558A1
Authority
EP
European Patent Office
Prior art keywords
layer
silicon dioxide
silicon
dioxide layer
memory device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP80901882A
Other languages
German (de)
English (en)
Inventor
Murray Lawrence Trudel
Vinod Kumar Dham
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NCR Voyix Corp
Original Assignee
NCR Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NCR Corp filed Critical NCR Corp
Publication of EP0035558A1 publication Critical patent/EP0035558A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/01—Manufacture or treatment
    • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
    • H10D30/0413—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having charge-trapping gate insulators, e.g. MNOS transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors

Definitions

  • This invention relates to non-volatile memory devices of the kind including a semiconductor substrate having provided thereon a first silicon dioxide layer, a silicon nitride layer provided on said first silicon dioxide layer and a silicon gate electrode overlying said silicon nitride layer.
  • the invention also relates to methods of making gate dielectric structures for non-volatile memory devices.
  • SNOS silicon (polysilicon)-nitride- oxide-semiconductor.
  • SONOS is silicon (polysilicon)-oxide- nitride-oxide-semiconductor.
  • Gate oxide and “memory gate oxide” refer to the silicon dioxide dielectric formed between the semiconductor and the silicon nitride (SONC-S) in the active area of a non-volatile memory device such as a capacitor or field-effect transistor.
  • Interfacial oxide refers to the silicon dioxide layer formed between the silicon gate and the silicon nitride dielectric in SONOS structures.
  • Retention is a measure of the ability of the memory device to retain its stored charge subsequent to a write or erase operation.
  • Endurance is a measure of the retention of the memory device as a function of the number of write-erase cycles to which the device has been subjected.
  • a non-volatile memory device of the kind specified is known from an article by Peter C. Y. Chen entitled “Threshold-Alterable Silicon Gate MOS Devices", IEEE Transactions on Electron Devices, Vol. ED-24, No. 5, May, 1977.
  • Chen addresses the relatively poor retention of silicon gate structures: for example, a 15 Angstrom thick gate oxide provides retention measured in years in typical MNOS structures, but only in hours in SONOS structures. Chen increased the retention of his SONOS devices by increasing the thickness of the gate oxide to 30 Angstroms. However, increasing the oxide thickness has the disadvantage of slowing write and erase speeds.
  • a non-volatile memory device of the kind specified characterized by a second silicon dioxide layer located between said silicon nitride layer and said gate electrode and formed by chemical vapor deposition to a thickness of about 70-100 Angstroms, said first silicon dioxide layer having a thickness not greater than about 15 Angstroms.
  • a method of making a gate dielectric structure for a silicon gate non-volatile memory device characterized by the steps of forming on a semiconductor substrate, a first, memory, silicon dioxide layer; forming on the first silicon dioxide layer a layer of silicon nitride; and forming on the silicon nitride layer a second, interfacial, silicon dioxide layer by chemical vapor deposition.
  • Fig. 1 is a cross-sectional representation of a silicon gate memory device embodying the principles of the present invention.
  • Fig. 2 is a graphical representation of the retention and endurance characteristics of prior art SNOS devices.
  • Fig. 3 is a graphical representation of the retention and endurance characteristics of SONOS devices embodying the characteristics of the present invention.
  • FIG. 1 A cross-section of an n-channel SONOS memory field effect transistor 10 embodying the features of the present invention is illustrated in Fig. 1.
  • the device 10 is conventional except as noted.
  • the illustrated device is formed by the well-known LOCOS (localized oxidation of silicon) process, although certainly the invention is not limited to this process.
  • a p- silicon substrate 16 has source- and drain- forming, opposite conductivity n + diffusions 17 and 18 therein, and a gate structure 15 which embodies the present invention.
  • the gate structure includes a very thin (about 10-15 Angstroms) gate oxide 11, a silicon nitride gate dielectric layer 12 of about 350 to 550 Angstroms thickness, an interfacial silicon dioxide gate dielectric layer 13 which is about 70-100 Angstroms thick, and a polysilicon gate electrode 14 which is typically several thousand Angstroms thick. Electrical contact is made to the source- and drain- forming diffusion 17 and 18 by electrodes 27 and 28, and to the silicon gate 14 by electrode 25. Also, electrical isolation of the device 10 is provided by field oxide layer 21 and isolation oxide layer 22.
  • the device 10 features the 70-100 Angstrom thick interfacial oxide layer 13 interposed at the nitride 12-polysilicon gate 14 interface and the very thin, 10-15 Angstroms thick, gate silicon oxide layer 11.
  • the source 17 and drain 18 are formed by n-type impurities such as phosphorus (or p-type such as boron for p-channel) using diffusion or ion implantation techniques.
  • the field oxide 21 can be formed by wet thermal oxidation of the substrate 16, to a typical thickness of 14K to 16K. (14,000 to 16,000) Angstroms, as grown.
  • the memory gate oxide 11 is preferably formed by dry thermal oxidation (thermal oxidation using dry oxygen), typically at 600 to 750°C. in an oxygen-nitrogen ambient.
  • the memory nitride layer 12 can be deposited by the chemical vapor deposition technique at a temperature of about 700-750°C.
  • the interfacial oxide 13 is deposited by the atmospheric pressure chemical vapor deposition (APCVD) technique using a dry oxygen-silane-nitrogen ambient and a temperature of approximately 600°C, for example a temperature in the range of about 600-625°C.
  • the polysilicon gate 14 can be formed using either the low pressure chemical vapor deposition (LPCVD) technique or the APCVD technique in an ambient of silane or silane-nitrogen, respectively, over the temperature range 600-700°C.
  • the isolation oxide 22 can be formed by several techniques, the illustrated oxide is an APCVD oxide deposited at a temperature of about 425°C. in a silane-nitrogen-oxygen ambient to a typical thickness of about 6K Angstroms.
  • Contacts 25, 27 and 28 are conductors such as aluminum or aluminum-silicon alloy which are formed using standard metallization techniques.
  • the silicon nitride gate dielectric layer 12 is preferably formed by chemical vapor deposition by reacting ammonia and silane (the nitrogen is a carrier gas) in a reactor maintained at 700-750°C.
  • ammonia and silane the nitrogen is a carrier gas
  • the present embodiment achieves this purpose by forming the interfacial oxide layer 13 using the above-described low temperature APCVD technique. It should also be possible to generate the interfacial oxide layer 13 by other low temperature methods, for example, by the LPCVD technique.
  • the transistors were formed in accordance with the exemplary procedure described above.
  • the substrate 16 was ⁇ 100> p-type, 15-20 ohm-cm silicon.
  • the final thickness of the field oxide 21 was 9K Angstroms; of isolation oxide 22, 6K Angstroms.
  • the gate structure 15 included 15 Angstroms thick gate memory oxide 11; 400-500 Angstroms thick gate memory nitride 12; 70 Angstroms thick APCVD interfacial oxide 13 (for the SONOS FETs only, not the SNOS FETs); and 3500 Angstroms thick APCVD polysilicon gate 14.
  • the metallization was approximately 14K Angstroms aluminum.
  • the retention-endurance data of Figs. 2, 3 was obtained by (1) initializing the FETs by determining the initial written (or "1") and erased (or "0") threshold voltages V T ; (2) generating uncycled retention-endurance curves by storing the devices at an elevated temperature for the times shown in Figs. 2, 3 and determining the threshold voltages at intervals during this time; (3) write-erase cycling the FETs 10 4 times; (4) reinitializing the FETs; (5) generating retention-endurance curves for the 10 4 cycles by again storing at elevated temperature per step 2; (6) write- erase cycling to 10 total cycles; (7) reinitializing; and (8) generating retention-endurance curves for 10 5 cycles per step 2.
  • the initialization procedure (steps 1, 4 and 7), i.e. obtaining the initial written and erased state threshold voltages, involved applying +25 volts for three seconds and -25 volts for three seconds, respectively, at room temperature to the gates of the memory FETs. Source, drain and substrate were all tied to ground during this initialization.
  • Write-erase cycling (steps 3 and 6) was done at room temperature (approximately 24°C.) using an applied gate voltage of ⁇ 25 volts and a 10 millisecond pulse width for both polarities.
  • the source, drain and substrate were all tied to ground during the write- erase cycling.
  • the storage at temperature data for the un- cycled and cycled parts were obtained by first placing the parts in an oven at 125°C. in an air ambient to accelerate charge decay. (Note: The parts were packaged in metal cans to protect them from mechanical damage and against potentially harmful exposure to the storage and room temperature ambients.) The parts were removed from the oven at various time intervals and the gate voltage required for a 20 micro amp drain-source current (I DS ) was measured and recorded at room temperature. The decay of the stored charge, or equivalently, the rate of threshold voltage window closure as a function of log time for the SNOS and SONOS transistors, is shown in Figs. 2 and 3, respectively.
  • the initial threshold voltage window at 1 hour decreases with an increase in the number of write-erase cycles for the SNOS devices, while the window actually increases for the SONOS devices.
  • the normalized closure of the window between the "0" and “1" states threshold voltages increases significantly with increased write-erase cycles for the SNOS devices but changes very little for the SONOS devices.
  • the SONOS devices in addition, exhibit lower normalized decay rates (window closure) at all values of the write-erase cycles.
  • the addition of the interfacial oxide layer 13 (Fig. 1) and the resulting SONOS structure leads to a significant improvement in the normalized retention (window closure) and endurance characteristics of the basic SNOS memory structure.
  • the window decay rates for the SONOS devices shown in Fig. 3 are close to that obtained by Chen in the above-referenced article, indicating that the 15 Angstrom-thick gate oxide samples provide the same retention as the thicker oxide SONOS structure required by Chen.
  • the improved normalized retention and endurance may in part be due to a reduction in the normalized charge leakage through the nitride to the polysilicon gate by virtue of the interfacial oxide layer which presents a potential barrier at this interface.
  • the exact mechanism responsible for the improved normalized retention and endurance of the SONOS devices and for the increase in the voltage window with increased write-erase cycling is not understood.
  • the improved memory characteristics obtained with the mono gate memory FET SONOS structure 10 should be equally valid for split-gate and trigate memory structures such as taught in U. S. 3,719,866 issued March 6, 1973 to Naber and Lockwood and assigned to NCR. Also, the improved memory characteristics are applicable to all silicon gate structures to which the gate structure 15 is applicable, and includes capacitor structures (i.e. FET 10 without source 17 and drain 18) as well as transistor structures.

Landscapes

  • Non-Volatile Memory (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Un dispositif de memoire remanente comprend un substrat semi-conducteur (16), une couche fine d'oxyde de memoire de 10-15 angstroms d'epaisseur (11), une couche de nitrure de silicium (12), une couche d'oxyde d'interface d'une epaisseur de 70-100 angstroms (13), et une electrode de porte de poly-silicium (14). La couche d'oxyde d'interface (13) est formee par depot de vapeur chimique a une temperature situee entre 600 et 625 C environ.
EP80901882A 1979-09-13 1981-03-23 Dispositif de memoire remanente a porte de silicium Withdrawn EP0035558A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US7484079A 1979-09-13 1979-09-13
US74840 1979-09-13

Publications (1)

Publication Number Publication Date
EP0035558A1 true EP0035558A1 (fr) 1981-09-16

Family

ID=22121989

Family Applications (1)

Application Number Title Priority Date Filing Date
EP80901882A Withdrawn EP0035558A1 (fr) 1979-09-13 1981-03-23 Dispositif de memoire remanente a porte de silicium

Country Status (3)

Country Link
EP (1) EP0035558A1 (fr)
JP (1) JPS56501146A (fr)
WO (1) WO1981000790A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
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US7738600B2 (en) 2001-08-16 2010-06-15 Dsp Group Inc. Digital phase locked loop

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Publication number Priority date Publication date Assignee Title
EP0078318A4 (fr) * 1981-05-11 1983-06-24 Ncr Corp Dispositif de memoire a semi-conducteur a seuil modifiable.
US5168334A (en) * 1987-07-31 1992-12-01 Texas Instruments, Incorporated Non-volatile semiconductor memory
US4870470A (en) * 1987-10-16 1989-09-26 International Business Machines Corporation Non-volatile memory cell having Si rich silicon nitride charge trapping layer
JP2871530B2 (ja) * 1995-05-10 1999-03-17 日本電気株式会社 半導体装置の製造方法
US6297096B1 (en) 1997-06-11 2001-10-02 Saifun Semiconductors Ltd. NROM fabrication method
US6768165B1 (en) 1997-08-01 2004-07-27 Saifun Semiconductors Ltd. Two bit non-volatile electrically erasable and programmable semiconductor memory cell utilizing asymmetrical charge trapping
US6215148B1 (en) 1998-05-20 2001-04-10 Saifun Semiconductors Ltd. NROM cell with improved programming, erasing and cycling
US6348711B1 (en) 1998-05-20 2002-02-19 Saifun Semiconductors Ltd. NROM cell with self-aligned programming and erasure areas
US6429063B1 (en) 1999-10-26 2002-08-06 Saifun Semiconductors Ltd. NROM cell with generally decoupled primary and secondary injection
US6490204B2 (en) 2000-05-04 2002-12-03 Saifun Semiconductors Ltd. Programming and erasing methods for a reference cell of an NROM array
US6928001B2 (en) 2000-12-07 2005-08-09 Saifun Semiconductors Ltd. Programming and erasing methods for a non-volatile memory cell
US6614692B2 (en) 2001-01-18 2003-09-02 Saifun Semiconductors Ltd. EEPROM array and method for operation thereof
US6584017B2 (en) 2001-04-05 2003-06-24 Saifun Semiconductors Ltd. Method for programming a reference cell
US7098107B2 (en) 2001-11-19 2006-08-29 Saifun Semiconductor Ltd. Protective layer in memory device and method therefor
US6700818B2 (en) 2002-01-31 2004-03-02 Saifun Semiconductors Ltd. Method for operating a memory device
US7142464B2 (en) 2003-04-29 2006-11-28 Saifun Semiconductors Ltd. Apparatus and methods for multi-level sensing in a memory array
US7123532B2 (en) 2003-09-16 2006-10-17 Saifun Semiconductors Ltd. Operating array cells with matched reference cells
US7317633B2 (en) 2004-07-06 2008-01-08 Saifun Semiconductors Ltd Protection of NROM devices from charge damage
US7095655B2 (en) 2004-08-12 2006-08-22 Saifun Semiconductors Ltd. Dynamic matching of signal path and reference path for sensing
US7638850B2 (en) 2004-10-14 2009-12-29 Saifun Semiconductors Ltd. Non-volatile memory structure and method of fabrication
US7535765B2 (en) 2004-12-09 2009-05-19 Saifun Semiconductors Ltd. Non-volatile memory device and method for reading cells
CN1838328A (zh) 2005-01-19 2006-09-27 赛芬半导体有限公司 擦除存储器阵列上存储单元的方法
US7221138B2 (en) 2005-09-27 2007-05-22 Saifun Semiconductors Ltd Method and apparatus for measuring charge pump output current
US7352627B2 (en) 2006-01-03 2008-04-01 Saifon Semiconductors Ltd. Method, system, and circuit for operating a non-volatile memory array
US7638835B2 (en) 2006-02-28 2009-12-29 Saifun Semiconductors Ltd. Double density NROM with nitride strips (DDNS)
US7605579B2 (en) 2006-09-18 2009-10-20 Saifun Semiconductors Ltd. Measuring and controlling current consumption and output current of charge pumps

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US4151021A (en) * 1977-01-26 1979-04-24 Texas Instruments Incorporated Method of making a high density floating gate electrically programmable ROM

Non-Patent Citations (1)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7738600B2 (en) 2001-08-16 2010-06-15 Dsp Group Inc. Digital phase locked loop

Also Published As

Publication number Publication date
WO1981000790A1 (fr) 1981-03-19
JPS56501146A (fr) 1981-08-13

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Inventor name: DHAM, VINOD KUMAR

Inventor name: TRUDEL, MURRAY LAWRENCE