EP0097947B1 - Dispositif pour générer des séquences pseudo-aléatoires en code AMI - Google Patents

Dispositif pour générer des séquences pseudo-aléatoires en code AMI Download PDF

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Publication number
EP0097947B1
EP0097947B1 EP83106254A EP83106254A EP0097947B1 EP 0097947 B1 EP0097947 B1 EP 0097947B1 EP 83106254 A EP83106254 A EP 83106254A EP 83106254 A EP83106254 A EP 83106254A EP 0097947 B1 EP0097947 B1 EP 0097947B1
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EP
European Patent Office
Prior art keywords
terminal
transistor
input
arrangement
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP83106254A
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German (de)
English (en)
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EP0097947A3 (en
EP0097947A2 (fr
Inventor
Fritz Dr.-Ing. Meyer
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Siemens AG
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Siemens AG
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Publication date
Application filed by Siemens AG filed Critical Siemens AG
Priority to AT83106254T priority Critical patent/ATE37641T1/de
Publication of EP0097947A2 publication Critical patent/EP0097947A2/fr
Publication of EP0097947A3 publication Critical patent/EP0097947A3/de
Application granted granted Critical
Publication of EP0097947B1 publication Critical patent/EP0097947B1/fr
Expired legal-status Critical Current

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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/24—Testing correct operation
    • H04L1/242—Testing correct operation by comparing a transmitted test signal with a locally generated replica
    • H04L1/244—Testing correct operation by comparing a transmitted test signal with a locally generated replica test sequence generators

Definitions

  • the invention relates to an arrangement for generating quasi-random sequences in AMI code with a generator for binary quasi-random sequences.
  • the monitoring of transmission links for digital signals is often carried out by monitoring the transmitted digital signals at individual points on these transmission links for violations of the code rule used in the formation of the digital signals. These code rule violations must have resulted from transmission errors.
  • a prerequisite for determining code rule violations is that there is a redundant code that can be used to identify violations of the code rule.
  • a frequently used code in the transmission of digital signals is the so-called AMI code, which is a pseudo-ternary code, in the successive one-line. Chen are transmitted by pulses with alternating polarity, while zero characters are assigned to the zero level.
  • the transmission of digital signals by means of FM directional radio systems is described in the publication "TELCOM REPORT", Volume 3, No. 5 from October 1980, pages 387 to 389.
  • the digital signals are scrambled using a self-synchronizing scrambler and then converted into two binary AMI signal streams using a JK flip-flop and two D-flip-flops connected via NAND gates, which are converted into a single unipolar AMI signal in an adjustable amplifier.
  • the adjustable amplifier consists of two emitter-coupled differential amplifiers which are controlled by the outputs of the D flip-flops and which are in turn connected to one another in a differential manner.
  • the emitter current for the differential amplifier is generated by an adjustable current source circuit.
  • a problem with the monitoring of transmission links for digital signals by examining these signals for code rule violations is the occasional checking of the code rule violation testers contained at certain points in the transmission link. For this check, for example, AMI-coded test signals are required which are generated locally in response to an additionally transmitted signal; the AMI-coded test signals are also required for the final test after completion of the regenerators with the code violation testers.
  • AMI-coded signals usually takes place in that a stub is connected in parallel to the output of a generator for test signals present in the differential binary code, which is short-circuited at the end and whose simple signal transit time corresponds to half the bit duration of the signals to be converted.
  • a positive pulse for example, at the short-circuited end of the stub line
  • a negative pulse is generated which appears a bit after the positive pulse at the input of the stub line.
  • such a way of generating AMI-coded signals is not suitable for generating test signals, since the use of a stub line enforces compliance with the AMI code rule, while the test signals must contain a certain number of code rule violations.
  • the object of the present invention is therefore to find a way of generating AMI-coded test signals with a certain number of code rule violations, the test signals being in the form of quasi-random sequences for carrying out an optimal test.
  • the object is achieved in that the first input of a differential amplifier arrangement and the one input of an exclusive OR gate are connected to an output of the clocked generator for binary quasi-random sequences in that the other input of the exclusive OR gate is connected to a control connection is connected that the output of the exclusive-OR gate is connected via a delay element to the second input of the differential amplifier arrangement, that the differential amplifier arrangement contains two emitter-coupled differential amplifiers, that the first of these differential amplifiers contains two npn transistors, the emitters of which are connected to one another and via a first Current source is connected to a connection for the negative operating voltage, that the base connection of the first transistor is connected to the first input of the differential amplifier arrangement and the base connection of the second transistor is connected to a reference voltage source, that the collector connection of the first trans istors with an output for the inverse output signal and is connected via a first resistor with reference potential that the collector terminal of the second transistor is connected to a signal output and via a second resistor with reference potential that the second differential amplifier a third and
  • the solution according to the invention offers a number of advantages, which lie in particular in the fact that the arrangement is easy to integrate overall and has a low power requirement with a simple structure.
  • a variant of the arrangement according to the invention is expedient in which the delay element is implemented by an electrical circuit arrangement, in particular a clocked shift register.
  • the arrangement for generating quasi-random sequences in the AMI code according to FIG. 1 contains a generator PNG for generating binary quasi-random sequences, which receives a clock signal via a connection C1.
  • the one connection of an exclusive OR gate EXOR and the first input E1 of a differential amplifier arrangement are connected to the output E of the generator PNG.
  • the differential amplifier arrangement contains two emitter-coupled differential amplifiers, the first differential amplifier containing a first and a second npn transistor T1, T2, the emitter connections of which are connected to one another and via a current source 11 in the form of a resistor to a connection for the operating voltage -Ub.
  • the collector terminal of the first transistor T1 is connected to an output terminal A for the inverse output signal and via a first resistor R1 to reference potential.
  • the collector terminal of the second transistor T2 is connected to an output terminal A for the non-inverted output signal and via a second resistor R2 to reference potential.
  • the second differential amplifier of the differential amplifier arrangement contains a third and a fourth NPN transistor T3, T4, the emitter connections of which are also connected to one another and via a current source for the current 12 to a connection for the operating voltage -Ub.
  • the collector terminal of the third transistor T3 is connected to the collector terminal of the second transistor T2 and the collector terminal of the fourth transistor T4 is connected to the collector terminal of the first transistor T1.
  • the base connections of the second transistor T2 and the fourth transistor T4 are connected to one another and to a source for a reference voltage Ur, this reference voltage lying between the two logic levels of the input signal.
  • the other connection of the exclusive-OR gate EXOR is connected to an input P, to which signals are supplied externally, by means of which code rule violations in the generated AMI-coded quasi-random sequence are to be triggered.
  • the second input E2 of the differential amplifier arrangement which corresponds to the base connection of the third transistor T3, is connected to the output terminal of the Exciusiv-OR gate via a delay element V.
  • the delay element V is implemented at low bit rates by an electronic delay element; at high bit rates, a line is provided as the delay element V which is adapted in terms of its characteristic impedance.
  • the function of the circuit arrangement according to FIG. 1 generally consists in that the quasi-random sequence generator PNG generates a binary quasi-random sequence which is directly and once delayed by the exclusive OR element and the delay element and fed to the differential amplifier arrangement.
  • the total delay in the exclusive OR element and in the delay element corresponds to a bit duration of the binary signals generated by the generator PNG.
  • the binary quasi-random sequence is transformed into an AMI-coded quasi-random sequence, which can be found directly at the output connection A or in inverse form at the output connection ⁇ .
  • the signals at the inputs E1 and E2 of the differential amplifier arrangement can assume the logic states 0 and 1, the state 1 being assigned to the higher potential.
  • the signals at the input connections E1 and E2 can form four different combinations, which result in three different logic states at the signal output A.
  • the first combination of the binary signals can be the case where the logic level is at the value 1 at the first input E1, while the zero level is present at the other input E2. This leads to a positive level at the output connection A.
  • the logic level can be present at the second input E2, while the zero level is present at the other input E1.
  • the level for -1 results at signal output A.
  • the logical zero level at signal output A results in each case.
  • the negative level at signal output A corresponds to the lowest and the positive level to the highest Potential.
  • the transistors T1 and T4 conduct, so that both the current 11 and the current 12 flow through the first resistor R1 while the second resistor R2 remains almost without current and therefore the highest potential and therefore the state +1 occurs at it. If there is zero potential at input E1 and the single potential at input E2, then the transistors T2 and T3 conduct accordingly, so that both currents then flow through the second resistor B2 and at him and thus at the signal output A the most steep potential corresponding to the -1- Level occurs.
  • both input signals are at the logic zero level, the transistors T2 and T4 conduct, so that an equally large current flows through each of the two resistors R1 and R2 and the average potential corresponding to the zero level occurs at the signal output A.
  • This state also arises when the level is present at both inputs, since in this case the transistors T1 and T3 are conducting and likewise an approximately equal current flows through each of the two resistors R1 and R2.
  • the delay element V has a delay - corresponding to a bit duration of the binary signals. If a signal in the differential binary code occurs at the output terminal E of the pseudo-random sequence generator PNG, then this signal occurs practically simultaneously at the first input E1 and a bit later at the second input E2 and leads to a corresponding switchover of the differential amplifier arrangement. A change in potential, for example from 0 to 1 at terminal E, thus leads directly to a positive level at output terminal A and one bit later at this terminal to a signal with negative level. If binary quasi-random sequences are generated by the pseudo-random sequence generator PNG, these also lead to quasi-random sequences which are present in the AMI code at the output connection A. Exchanging the two input connections E1 and E2 as well as exchanging the two output connections A and A leads to an inverse output signal.
  • the exclusive-OR gate EXOR can be supplied with individual pulses which lead to an inversion of the logic level present at the other input connection E2.
  • the upper line shows a binary pulse sequence in NRZ format, which is output by the pseudo random sequence generator PNG at connection E.
  • the middle line of FIG. 2 shows the signal present at the second input E2 of the differential amplifier arrangement. It can be seen that this signal corresponds to the output signal of the pseudo random sequence generator, albeit shifted by one bit duration.
  • the lower line shows the pseudo-ternary signal occurring at the output connection A.
  • An inverted line In is shown in dashed lines in the middle line, which was generated by an input pulse at connection P in the signal present at input connection E2.
  • the number of code rule violations can be less than the number of inversions displayed. For example, when two immediately consecutive bits are inverted, on average only 50% of the errors in the output signal occur as code rule violations. The number of code rule violations is reduced because the inversion also converts two successive states in the AMI code, for example + 1 / -1 or -1 / + 1, to state 0/0. In this case, the errors contained in the quasi-random sequence emitted on the output side do not act as code rule violations. If more than two immediately consecutive bits are inverted, the relative proportion with which these errors occur as code rule violations continues to decrease.
  • FIG. 1a contains a line transformer.
  • This known line transformer is constructed as a symmetrical-asymmetrical 4: 1 line transformer.
  • the line transformer contains two double lines Lt1 and Lt2 of equal length, the first double line Lt1 being wound onto a highly permeable core.
  • the first wire of the first double line Lt1 has at one end a first connection which is connected to connection A for the inverse output signal, while the other connection of the first wire is connected to reference potential.
  • the first adjacent to the first connection of the first wire Connection of the second wire of the first double line Lt1 is connected to reference potential, while the second connection of this wire is connected to the first wire of the second double line Lt2 and via a common consumer resistor RV to reference potential.
  • the second connection of the first wire of the second double line Lt2 is connected to the connection A for the output signal, while the second wire of the second double line Lt2 is connected at its two end points to reference potential.
  • the inputs of the lines are in series on the side of the line transformer facing the differential amplifier arrangement, while the outputs of the lines are connected in parallel on the asymmetrical side facing the consumer resistor.
  • An increase in the output power results from the fact that the powers are available at an output connection which occur separately at the two resistors R1 and R2 in the exemplary embodiment according to FIG. 1.
  • the asymmetrical consumer resistance RV which can represent, for example, a downstream coaxial cable with a characteristic impedance of 75 ohms, into the load resistors R1 and R2 which are symmetrical to ground in a ratio of 4: 1.
  • a further increase in power by the line transformer results from the fact that the collector voltage for the connected transistors can be supplied without a substantial DC voltage drop.
  • a further increase in the output power while improving the edge steepness of the generated signals is possible in that the two differential amplifiers of the differential amplifier arrangement are driven in a push-pull manner, eliminating the reference voltage source.
  • An improvement in the edge steepness is also possible in that the collector capacitance of the transistors, which in the present case is increased by the parallel connection of two collectors, is compensated for by a series inductance in the collector circuit.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Stereo-Broadcasting Methods (AREA)

Claims (3)

1. Dispositif pour générer des séquences pseudo-aléatoires en code AMI avec un générateur pour séquences pseudo-aléatoires binaires, caractérisé en ce qu'une sortie (E) du générateur synchronisé (PNG) pour des séquences pseudo-aléatoires binaires est reliée à la première entrée (E1) d'un montage amplificateur différentiel, et à l'une des entrées d'une porte OU-exclusif (EXOR), que l'autre entrée de la porte OU-exclusif est reliée à une borne de commande (P), que la sortie de la porte OU-exclusif (EXOR) est, par l'intermédiaire d'une unité de retard (V), reliée à la seconde entrée (E2) du montage amplificateur différentiel, que le montage amplificateur différentiel comprend deux amplificateurs différentiels à couplage d'émetteur, que le premier de ces amplificateurs différentiels comprend deux transistors NPN (T1, T2), dont les émetteurs sont reliés, entre eux et, par l'intermédiaire d'une première source de courant (11), à une borne destinée à la tension de service négative (-Ub), que la borne de base du premier transistor (T1) est reliée à la première entrée (E1) du montage amplificateur différentiel et la borne de base du deuxième transistor (T2) est reliée à une source de tension de référence (Ur), que la borne de collecteur du premier transistor (T1) est reliée à une sortie (A) destinée au signal de sortie inversé, et est, par l'intermédiaire d'une première résistance (R1), portée à une potentiel de référence, que la borne de collecteur du deuxième transistor (T2) est reliée à une sortie (A) de signaux, et est, par l'intermédiaire d'une seconde résistance (R2), portée au potentiel de référence, que le second amplificateur différentiel comprend un troisième et un quatrième transistor NPN (T3, T4), dont les bornes d'émetteur sont reliées entre elles et, par l'intermédiaire d'une seconde source de courant (12) portées à une tension de service négative (-Ub), que la borne de collecteur du troisième transistor (T3) est reliée à la borne de collecteur du deuxième transistor (T2) et le borne de collecteur du quatrième transistor (T4) est reliée à la borne de collecteur du premier transistor (T1), et que la borne de base du quatrième transistor (T4) est reliée à la borne de base du deuxième transistor (T2) et la borne de base du troisième transistor (T3) est reliée à la seconde entrée (E2) du montage amplificateur différentiel.
2. Dispositif selon la revendication 1, caractérisé en ce que les deux résistances de charge (R1, R2) sont remplacées par une seule résistance de charge (RV) couplée avec un transformateur de lignes amont, et que ce transformateur de lignes se compose de deux lignes doubles de même longueur (Lt1, Lt2), que la première ligne double (Lt1) est enroulée sur un noyau à haute permiti- vité et le premier conducteur de la première ligne double est, par l'une de ses extrémités, reliée à la borne de sortie (A) destinée au signal de sortie complémentaire et par l'autre extrémité portée au potentiel de référence, que le second conducteur de la première ligne double (Lt1) est, par une première borne, voisine de la première borne du premier conducteur, porté au potentiel de référence et, par une seconde borne, relié à une résistance de charge commune (RV) ainsi qu'à une seconde borne du premier conducteur de la second ligne double (Lt2), que la première borne de ce premier conducteur de la seconde ligne double est reliée à la borne de sortie (A) destinée au signal de sortie, que les deux bornes du second conducteur de la seconde ligne double sont portées au potentiel de référence et que les bornes des conducteurs individuels sont chaque fois prévues aux extrémités des lignes doubles (Lt1, Lt2).
3. Dispositif selon la revendication 1, caractérisé en ce que, l'unité de retard (V) est réalisée au moyen d'un montage électronique, en particulier un registre à décalage synchronisé.
EP83106254A 1982-06-30 1983-06-27 Dispositif pour générer des séquences pseudo-aléatoires en code AMI Expired EP0097947B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT83106254T ATE37641T1 (de) 1982-06-30 1983-06-27 Anordnung zur erzeugung von quasizufallsfolgen im ami-code.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3224442 1982-06-30
DE19823224442 DE3224442A1 (de) 1982-06-30 1982-06-30 Anordnung zur erzeugung von quasizufallsfolgen im ami-code

Publications (3)

Publication Number Publication Date
EP0097947A2 EP0097947A2 (fr) 1984-01-11
EP0097947A3 EP0097947A3 (en) 1986-02-19
EP0097947B1 true EP0097947B1 (fr) 1988-09-28

Family

ID=6167241

Family Applications (1)

Application Number Title Priority Date Filing Date
EP83106254A Expired EP0097947B1 (fr) 1982-06-30 1983-06-27 Dispositif pour générer des séquences pseudo-aléatoires en code AMI

Country Status (6)

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US (1) US4507621A (fr)
EP (1) EP0097947B1 (fr)
JP (1) JPS5910057A (fr)
AT (1) ATE37641T1 (fr)
DE (2) DE3224442A1 (fr)
NO (1) NO832373L (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1241120A (fr) * 1985-10-01 1988-08-23 Sami A. Aly Recepteur de signaux bipolaires alternants
US4960718A (en) * 1985-12-13 1990-10-02 Allied-Signal Inc. MESFET device having a semiconductor surface barrier layer
US4745603A (en) * 1986-05-27 1988-05-17 American Telephone And Telegraph Company, At&T Bell Laboratories Code sequence generator for a digital transmission line fault location system
US4829541A (en) * 1988-01-22 1989-05-09 Advanced Micro Devices, Inc. Pseudo-ternary code transmitter
US4885545A (en) * 1988-08-08 1989-12-05 Tektronix, Inc. High speed circuit with supporting auxiliary circuit
US4928289A (en) * 1988-12-19 1990-05-22 Systran Corporation Apparatus and method for binary data transmission
DE19655110C2 (de) * 1995-12-21 2001-02-15 Advantest Corp Schaltung zum Erzeugen einer Zufalls-Impulsfolge
US6687632B1 (en) * 1998-01-23 2004-02-03 Trilithic, Inc. Testing of CATV systems

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3787613A (en) * 1972-06-27 1974-01-22 Bell Telephone Labor Inc Pulse transmission system for conveying data and control words by means of alternating polarity pulses and violations thereof
US3906174A (en) * 1973-11-16 1975-09-16 Gte Automatic Electric Lab Inc Cable pair testing arrangement
GB1492134A (en) * 1974-04-23 1977-11-16 Wandel & Goltermann Method of measuring the bit error rate of a regenerated pcm transmission path
GB1512700A (en) * 1975-10-23 1978-06-01 Standard Telephones Cables Ltd Data transmission
FR2350005A1 (fr) * 1976-04-30 1977-11-25 Cit Alcatel Dispositif de generation de suite binaire pseudo-aleatoire
CA1180416A (fr) * 1981-05-19 1985-01-02 Botaro Hirosaki Circuit de retablissement de synchronisation

Also Published As

Publication number Publication date
JPS5910057A (ja) 1984-01-19
EP0097947A3 (en) 1986-02-19
EP0097947A2 (fr) 1984-01-11
DE3378151D1 (en) 1988-11-03
DE3224442A1 (de) 1984-01-05
ATE37641T1 (de) 1988-10-15
US4507621A (en) 1985-03-26
NO832373L (no) 1984-01-02

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