Classifications

• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F11/00—Error detection; Error correction; Monitoring
  • G06F11/006—Identification
• • G—PHYSICS
  • G01—MEASURING; TESTING
  • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
  • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
  • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
  • G01R31/317—Testing of digital circuits
  • G01R31/3181—Functional testing
  • G01R31/319—Tester hardware, i.e. output processing circuits
  • G01R31/3193—Tester hardware, i.e. output processing circuits with comparison between actual response and known fault free response

Definitions

• the present invention relates to circuit testing devices, and relates more particularly to portable testing apparatus with a programmable interface between a unit under test and a testing apparatus which provides plurality of tests for a plurality of known different circuits and provides identification of the unit under test upon detection of a passed test.
• the present invention relates to a portable circuit identifier.
• integrated circuit electronics both analog and digital.
• hybrid integrated circuits and various standard modules are also popular.
• the apparatus shown in application Serial No. 96,030 is a device for testing whether a circuit placed in a test socket is properly performing the functions of a particular selected identified circuit. In other words, it is necessary to know the identity of the circuit in order to ascertain whether the circuit is operating properly.
• OEM original-equipment manufacturers
• the present invention provides apparatus which will very quickly provide a plurality of tests for particular transfer characteristics among the pins of a standard socket in order to id.entif a circuit under test inserted into the socket.
• hybrid integrated circuit is used broadly to include both the definition in ANSI/IEEE standard 100-1977 and any modular arrangement of electronic components housed in a unit with a predetermined connecting pin arrangement.
• the present invention includes a plurality of test procedures stored in memory to ascertain proper operation of a plurality of integrated circuits, all of which are arranged to fit the particular socket provided on the test apparatus.
• the present invention is selectively operable to initiate a sequence of tests, which, once began, will continue through the entire test repertoire of the test apparatus until the circuit under test provides a complete set of correct responses to particular test inputs indicative of the circuit's identity or, until the test repertoire is exhausted.
• an identification signal (preferably a visible alpha-numeric output) is provided to identify the particular circuit under test to the user.
• an output is generated indicating either that the circuit under test is of a type different from the plurality of. circuits in the test repertoire or that the circuit is of a type within the test repertoire but is not functioning properly.
• the present invention includes a bidirectional port arrangement connected to a particular standard socket which may be operated under the control of a dedicated microcomputer to provide pin definitions at the pins of the standard socket.
• the pin definitions include input drive, output loading, power supply and ground conditions.
• Fig. 1 is a pictorial view of a preferred embodiment of the present invention.
• Fig. 2 is a block diagram of " the preferred embodiment of the present invention.
• Fig. 3 is a partially schematic, partially block diagram of the preferred embodiment of the present invention.
• Fig. 4A is a diagram illustrating the relationship between the roll table memory structure and the text procedure instructions.
• Fig. 4B is a flow diagram of the sequential test procedure of the present invention for identification of a unit under test.
• Fig. 5 is a diagram of the interface between a particular pin of the socket holding the unit under test and the preferred embodiment of the present invention.
• Fig. 6 is a diagram of the instruction format for the test routine stored in the test procedure memory in the preferred embodiment of the present invention.
• Fig. 1 the pictorial view of the preferred embodiment of the present invention is shown.
• Socket 10 provides a means for making an electrical connection to a unit under test (UUT) .
• socket 5 10 is embodied by a standard forty pin dual in line socket. It will be appreciated by those skilled in the art that other socket configurations such as those for the Standard Electronic Module (SEM) or the Support Equipment Electronic module (SEEM) are o available and that simple adapters from socket 10, or other socket configurations, may be used with the present invention.
• SEM Standard Electronic Module
• SEEM Support Equipment Electronic module
• the preferred embodiment of the present invention is controlled by the operator through the 5 use of three external switches, namely on/test switch 11 and two double-detent switches 12 and 13 which are, respectively, forward (FWD) and reverse. (REV) .
• An alpha numeric display 16 is also Q provided on the preferred embodiment.
• a four character display is used and this has been found to be sufficient for identification of one hundred or more standard circuit modules. It is of course possible to use a 5 greater or lesser number of characters in display _ 16.
• 10 present invention includes memory which contains instructions for testing approximately one hundred . standard devices which may be accepted by socket 10. Internal to the preferred embodiment is a table (or more precisely a means for generating a table)
• the user first depresses on-test button
• the preferred embodiment monitors the output voltage of its battery and will display an appropriate message indicating that battery voltage is too low and the battery should * be replaced or recharged.
• the unit may be turned off either by holding on test button 11 in a depressed state for a predetermined period of time (approximately two seconds in the preferred embodiment) or by failing to provide any input to the device for a second
• any stored test routine for a particular circuit plugged into socket 10 may be executed quickly and simply to the use of only three external inputs (switches 11, 12 and 13) .
• Fig. 2 a block diagram of the preferred embodiment may be seen.
• switches 11, 12 and 13 are the only user operated external inputs required to control the present invention.
• Display 16 is shown as a block in Fig. 2.
• switches 12 and 13 are directly connected to an input of microcomputer 20.
• On/test switch 11 is connected to both microcomputer 20 and power supply 17.
• Microcomputer 20 is connected with the remainder of the preferred embodiment via a bidirectional bus 18 which in Fig. 2 will be understood to include a bidirectional data bus, an address bus, and appropriate control lines.
• Bus 18 is connected to I/O/memory block
• Fig. 2 It will be understood that in the preferred embodiment this connection will manifest itself as socket 10 shown in Fig. 1.
• Line 26 in Fig. 2 shows that power supply 17 supplies power to I/O/memory block 20 and unit under test 27.
• Power is supplied to I/O/memory block 25 and unit under test 27 only under certain specified conditions under the control of microcomputer 20, thus minimizing the drain on the battery of power
• microcomputer 20 is embodied as a type 8748 eight bit one chip microcomputer currently manufactured by Intel Corporation of Santa Clara, California. Detailed descriptions of the functioning of the 8748 microcomputer are available in "MCS-48 Microcomputer Users Manual", °1977, which is hereby incorporated by reference. Sufficient detail will be presented herein to enable one skilled in the art to understand how the microcomputer works in the present invention, and how other microcomputers could be used to construct an embodiment of this invention.
• the type 8748 microcomputer includes IK of eight bit erasable programmable read only memory (EPROM). It will be appreciated by those skilled In the art that a type 8048 microcomputer could be used in the mass production of the preferred embodiment of the present invention since the type 8048 includes a masked programmable read only memory .
• I/O/memory 25 (shown in Fig. 2) is embodied as two integrated circuits 25a and 25b shown in Fig. 3. Each of these circuits is an 8755A EPROM with I/O, currently manufactured by Intel Corporation of Santa Clara, California. From the description of the 8755A to follow, it will be apparent to those skilled in the art how other similar combinations of read only memory and I/O ports may be used to construct an embodiment of the present invention. However, it is to be understood that the novel use of this otherwise standard device is one of the inventive features of the present invention.
• Power supply 17 is shown as a block in Fig. 3. Recall from the discussion of Fig. 2 that the IK of memory for microcomputer 20 may be thought of as being divided into two portions, an operating system memory (28 in Fig. 2) and a roll table memory (29 in Fig. 2).
• the operating system memory (28 in Fig. 2) will be understood to include instructions for running the identification routine (Fig. 4B) while the specific instructions for the plurality of test proceedures reside in chips 25a and 25b.
• the 16K EPROM associated with each of the 8755A chips 25a and 25b is a 2KX8 memory and contains the program instructions for a plurality of test procedures for various known devices. It is to be understood that since each of chips 25a and 25b contain 2K eight bit words, a total of 4K external memory addresses must be accessible in the preferred embodiment shown in Fig. 3. Therefore, twelve bits are required to address the external memory containing test procedure instructions in chips 25a and 25b.
• the generalized bus 18 of Fig. 2 is shown as 18 in Fig.
• Bus 39 connects directly to six pins of socket 10. Bus 39 will be understood to have pull up resistors internal to microcomputer 20 associated therewith and therefore does not need external pull up resistors.
• Switch 12 and 13 have a pole connected to ground. As has been described hereinabove, these switches are double detent switches, and each contact for each detent may be seen in Fig. 3.
• the first level contact of switch 12 is designated 40 while the second contact thereof is designated 42.
• switch 13 operates in an analogous fashion. Note that contacts 42 and 43 of switches 12 and 13, respectively, are electrically identical and therefore the depression to the second level of either switch will ground point 45 which is connected to an input of microcomputer 20 designated as interrupt (INT).
• interrupt interrupt
• switches 12 and 13 cause the roll table to be generated forward and backward.
• the outputs of power supply 17 appear on lines 48, 55, and 56.
• Line 56 supplies power to microcomputer 20 and to resistors associated with switches 12 and 13.
• Line 48 supplies power to chips 25a and 25b where it is tapped at points 49 and 50.
• Line 55 from power supply 17 supplies power to the unit under test at point 57 and to the external pull up resistors 58 which are connected to the receptors of socket 10.
• socket 10 is shown in Fig. 3 as having a dedicated power supply and ground pin as is the case, for example, with the Standard Electronic Module (SEM)
• various pins of socket 10 may be defined as power supply and ground leads in the same manner as other input drive conditions and output loading conditions are defined.
• the lower eight address bits, A0 — 7 of I/O/memory chips 25a and 25b are tied to bidirectional bus 30.
• the upper three address bits are tied to three bits of bus 31.
• the P23 output of microcomputer 20 is tied to the negated chip enable (CE) of chip 25a and to the true chip enable of chip 25b. Therefore, the P23 output of microcomputer 20 which appears on line 59 may be thought of as the most significant address bit of an address bus for accessing chips 25a and 25b in that it will select one chip or the other.
• Socket 10 as shown in Fig. 3 is representative of the forty pin socket 10 shown in
• Fig. 1 the inputs and outputs to the socket terminals are shown in Fig. 3.
• Thirty- two pins of socket 10 are attached to four eight-bit ports from chips 25a and 25b.
• the port A from I/O chip 25a is designated 46 and three bits of port B of I/O chip
• each of these eight bit ports is an eight bit bidirectional port having pull up resistors 58 tied externally thereto.
• Six receptacles from socket 10 are connected to bus 39 from pins P10 — P15 of microcomputer 20.
• the present invention is related to the invention shown in co-pending application Serial No. 96,030.
• the preferred embodiment of the present invention makes use of a roll table memory structure similar to that shown in said co-pending application. Therefore, a detailed explanation of the features of the roll table of the present invention which are similar to those of the apparatus disclosed in said co-pending application will not * be set forth herein in detail.
• the roll table elements which reside in roll table memory 29 contain the memory words necessary to generate, via an iterative scheme, the names of circuits for which test procedures reside in the test procedure memory in order that the names may be shown in display 16.
• Each element of the roll table will comprise between three and six eight bit bytes of roll table memory 29.
• One to four of the bytes for each roll table element comprise a flag bit and a seven bit word in ASCII code.
• Each of the seven bit words of ASCII code correspond to a new letter or number (in ASCII code) which is different from a word or number in the immediately preceding element of the roll table.
• the flag bit is made equal to one to denote the last ASCII code word in that particular roll table element.
• the remaining two bytes provide a twelve bit address pointer pointing to a twelve bit address in test procedure memory 22 (Fig. 2) which resides in the 8755a chips.
• This address contains the first step of the test procedure for the particular circuit identified by the alpha numeric display generated by that particular roll element.
• the twelve bit address pointer comprises: (1) the four least significant bits of the next to last byte in the roll table element; and (2) the following eight bit byte which is the last byte in the table element.
• 96,030 is shown in Fig. 4A.
• a roll table which generates some in-house numbers for devices to be tested as well as generic names for the devices for which a test procedure exists in the test repertoire.
• the user of the present invention or the invention shown in co-pending application Serial No. 96,030 is in an environment which requires servicing of many pieces of equipment manufactured by a particular OEM using in-house numbers, it is desirable to include in the
• FIG. 4A an exemplary portion of the roll table memory 29 is shown on the left hand side with a block diagram of an exemplary portion of test procedure memory 22 shown on the right hand side.
• the portion of the roll table memory shown on Fig. 4A includes six roll table elements (K-l) through (K+4) .
• the block diagram represents the steps for three exemplary test procedures labeled as test (L-l) through test (L+l).
• the last byte of each test procedure contains a dedicated code indicating completion of the particular test. This is shown as "END" in Fig. 4A. It is also possible to dedicate one bit of each byte as a last step flag.
• Fig. 4A It is also possible to dedicate one bit of each byte as a last step flag.
• the most significant bit for each byte, except the second byte of the twelve bit address pointer, is a flag bit.
• the flag bit is set at one to denote the end of the name of each roll table element in a sequence of bytes representing a name.
• the flag bit in the address pointers is set at one to denote the preceding name is generic.
• the name of the roll table element is contained in between one and four bytes, each of which denotes a change in an alpha numeric character (beginning with the rightmost character displayed) from the name of the previous element.
• a NAME portion of a roll table element containing four bytes is indicative of a change in the leftmost alpha numeric character displayed
• a roll table NAME element containing three bytes is indicative of no change in the leftmost character from the previous roll table element, but includes a change in the character next to the leftmost character.
• roll table element (K-l) contains a leftmost character different from roll table element (K-2) .
• the leftmost character is changed in proceeding from roll table (K-l) to roll table element (K) .
• only the rightmost character differs in going from roll element (K) to roll element (K+l) .
• the operating system of the present invention treats the next two bytes as containing a twelve bit address pointer pointing to the first step of the test procedure for the circuit corresponding to the name of the roll table element.
• the NAME portion of element roll (K) contained the characters 7408 (in the order 8047 proceeding sequentially through the roll table memory) so that the name of roll element (K) was 7408.
• this corresponds to a generic name for a quad two input AND gate TTL circuit.
• test (L) provides the appropriate steps for testing a 7408 quad dual input AND gate integrated circuit.
• each roll table element - is identified by a one in the flag bit position.
• next two bytes always represent the twelve bit address pointer to the first step of the appropriate test for that circuit.
• the first bit (most significant) of the first byte of the address pointer is used as a generic flag. It will therefore be appreciated that a plurality of roll table elements may point to the same test procedure so that the roll table memory may generate several different names for the same circuit: one of the names being generic; and the remainder of the names being in-house numbers used by various OEMs for that particular circuit. This arrangement allows a significant saving of memory space because identical test procedures do not have to be duplicated in the test procedure memory 22.
• roll table elements (K) , (K+2) , and (K+3) are the generic names for three particular circuits. It may also be seen that roll table element (K+2) is a nongeneric or in-house name for the circuit generically identified by roll (K-l). Similarly, roll (K+l) is a nongeneric name for the circuit corresponding to roll (K) . Likewise, roll (K+3) is the generic name for a circuit which is also identified by the nongeneric name generated by roll (K+4).
• the preferred embodiment of the present invention provides a tester which operates according to the disclosure of the above-referenced co-pending application which contains both generic and nongeneric names for particular circuits.
• the operating scheme of the present invention executes tests only for roll table elements containing the generic flag in the most significant bit of the first byte containing the twelve bit address pointer as shown in Fig " . 4A.
• a flow chart of the steps executed by the operating system of the present invention is shown in Fig. 4B . It is to be understood that the routine shown in Fig. 4B is executed by firmware contained in the read only memory of microcomputer 20 and more specifically in the operating system portion 28 of the read only memory of the computer (See Fig. 1. ) .
• the preferred embodiment of the present invention is constructed to be an improvement upon the testing apparatus shown in co-pending application Serial No. 96,030. It is of course possible to construct other embodiments of the present invention, but it is believed that the best mode of the present invention is constructed according to the present disclosure so that both the identification function of the present invention, together with the testing apparatus of the invention disclosed in said co-pending application, may be advantageously combined since the preferred embodiments of the both inventions both require generation of a roll table and the storage of a plurality of test procedures.
• BUIE ⁇ ; routine shown in Fig. 4B is a routine which is called by depression of test switch 11 when the roll table generating scheme disclosed in the above-men ioned co-pending application has incremented the roll table to element number 2. This is shown diagrammatically in Fig. 4B as step 112. It is to be understood that a routine initialization procedure is shown as step 110 in Fig. 4B and that roll table element 1 of the preferred embodiment is a self test routine which may be executed by the apparatus. Therefore, the decisional step 115 shown in Fig. 4B corresponds to the identical TEST decisional step shown as step 110 of Fig. 4 in the co-pending application which is a flow chart for generation of the roll table.
• the incrementing of the roll table is the equivalent of the NO branch 116 from step 115 which causes the preferred embodiment to return to its normal test routine shown as block 120.
• the operator of the preferred embodiment manipulates switches 11, 12 and 13 so as to execute branch 116 shown in Fig. 4B, the preferred form of the present invention will operate as disclosed in the co-pending application.
• the identifier routine is, entered and executed.
• the identifier routine comprises a loop which is bounded by dashed line 130 which, once entered via branch 117, can only be exited after the unit under test has passed an entire test procedure residing in memory 22 (Fig. 2) or until the entire test procedure repertoire has been
• the first step in the loop is conditional branch 119. Since it may be seen from Fig. 4A that the generic flag (the first byte of the twelve bit address pointer) is equal to zero, branch 122 will be taken from conditional step 119. The variable ROLL will be incremented at step 140 and then conditional step 141 will be -executed. Step 141 tests to see if the element ROLL is equal to N+l where N is the number of test procedures stored in memory 22 of Fig. 2. If test 141 is satisfied, it indicates that the entire roll table has been scanned without a successful completion of an entire test for the unit under test and therefore loop 130 is exited along branch 145.
• (K) is less than N+l so branch 142 is taken from step 141.
• conditional step 119 is executed on roll table element (K) and, as may be seen from Fig. 4A, the generic flag is equal to one. Therefore, branch 121 is taken causing the operating system to enter the test procedure loop bounded by dashed line 125.
• the first step of the test procedure loop is to set a variable called STEP with a value corresonding to the address pointer from the roll table. This is shown at step 126 in Fig. 4B. It will be understood that step 126 may be executed by loading the address counter of the microcomputer or by the use of a relative addressing scheme. As may be seen from Fig. 4A, step 126 in the procedure described would load the address of the first step of test L into the register corresponding to the variable STEP. The next step 127 corresponds to providing a particular set of test conditions defined by first step of test L. As will be appreciated by those skilled in the art, each step recited herein for Fig. 4B may involve a set of conditions defined by more than one byte of test procedure memory 22 but each set of conditions for which an output is tested is to be considered one step according to the flow chart of Fig. 4B.
• Conditional step 128 tests to see if the correct output for test L is present on appropriate pins of socket 10. Assume for the moment that the unit under test provides the correct output for the first set of test conditions and therefore branch
• Fig. 4B The next step shown in Fig. 4B is conditional to see if the END code is present indicating that the entire test L has been executed. Since this will not be the case in the present example, branch 135 will be taken and the variable STEP will be incremented at step 136. Therefore the operating system will fetch the next set of conditions defined as part of test procedure
• Branch 129 leads to step 140 , incrementation of the roll table which now makes the variable roll equal to (K+l). Again, branch 142 is taken from conditional test 141 leading back to the generic flag test of step 119. Since Fig.
• the twelve bit address pointers associated with roll table element (K+2) points to (L-l) and therefore the variable STEP will be loaded, at step 126, with a number corresponding to the address of the first step of test (L-l).
• roll table element (K+2) is provided in display 16 (Fig. 1) and thus the unit under test has been successfully identified by __ its generic name corresponding to roll table element (K+2) .
• the operating system returns the apparatus to its 5 normal test procedure as shown at block 120.
• step 146 displaying the word "NONE" is executed showing that the unit 5 under test failed to satisfy any test procedure resident in the device. Upon this display, control is again returned to the normal test procedure routine of the operating system.
• memory 22 contains a plurality of test procedures, exemplary ones of which are shown as (L-l) through (L+l) in Fig. 4A. It will further be appreciated that each of the test procedures comprises a plurality of test conditions which are 5 sequentially provided, one at a time, through the steps comprising test procedure loop 125 of Fig. 4B.
• each of the plurality of test conditions defined for any 0 one test procedure correspond to input drive for pins defined as inputs, output loading for pins defined as outputs, power supply conditions corresponding to the provision of appropriate voltages at power supply pins, and grounding of power supply ground pins.
• each set of conditions may be set up and tested, that is,
• microcomputer 20 Among the novel features of the interface between microcomputer 20 and the unit under test are the manner in which inputs and outputs are defined and provided to the unit under test, and the new and nonobvious way of interconnecting a microcomputer and an I/O/memory device such as the type 8755A shown in the preferred embodiment.
• interconnecting microcomputer 20 and I/O/memory devices 25a and 25b is one of the features of the present invention which allows the preferred embodiment to be made quite small while at the same time, storing test routines for one hundred or more devices.
• the means for interconnecting microcomputer 20 and I/O/memory devices 25a and 25b provide an addressing scheme wherein the microcomputer 20 treats accessing the I/O ports of chips 25a and 25b analogously to reading into or writing from external random access memory for a normal connection in a microcomputer system.
• FIG. 5 shows, by way of example, the internal logical equivalent of a particular pin designated AN of output port A of I/O/memory device 25a. It will be understood by those skilled in the art that the portions of Fig. 5 bounded by the block 25a show logical equivalents of the actual type 8755A currently available.
• Pin AN designated as 60 on Fig. 5 should be understood to be one pin of I/O port A of chip 25a. Therefore, it will be understood that one line from bus 46 (Fig. 3) is connected to pin 60.
• Pin 60 is electrically connected to a point 61 which is both the output of a three state buffer 62 and the input to a three state buffer 65.
• Data direction latch (DDR) 66 controls the output of buffer 62 and AND gate 67 controls the output of buffer 65.
• DDR Data direction latch
• Another three state buffer 68 is connected to point 69 which may be seen from Fig. 5 to be on the internal data bus of the 8755A chip.
• Buffer 68 carries the Nth output line from the outputs of the- ROM of the 8755A. Therefore, line 70 carries the Nth bit of the output word from this PROM to the internal data bus 71 of the 8755A.
• a plurality of latches designated as 72 are the address latches internal to an I/O/memory device such as the 8755A.
• the latches for the two least significant bits are shown in Fig. 5 as 75 and 76. These latches contain a two bit pointing vector which determines the source and destination of data for the internal data bus 71.
• Latch 75 latches the least significant bit of data bus 30 when the address latch enable signal on line 35 exhibits a trailing edge. A zero in latch 75 points to port A of the 8755A and a one points to port B. Therefore as will be appreciated from Fig.
• Latch 76 latches a bit which points _ either to data direction register 66 (when a one is latched) , or to output latch 86 (when a zero is latched) .
• line 82 which in part controls the three state buffer 65 through AND gate 76, will simply be the logical inverse of line 38 to the negated IOR input.
• the grounding of input 81 also assures that line 79 is simply the
• PROM will be placed on the internal data bus of the 8755A and thus on bidirectional data bus 30.
• 25 point 85 on line N of the internal data bus will be written into either the data direction register 66 or the output latch 86.
• the particular one of the latches 66 or 86 into which data is written is determined solely by the latched vector in address
• the first write instruction from microcomputer 20 is one in which the latched output of address latch 76 is a one, thus enabling writing into data direction latch 66.
• a zero __ written into data direction latch 66 disables buffer 62 (places its output in a high impedence state) thus defining pin 60 /as an output pin of the unit under test. All subsequent write (line 37 5 going low) operations from microcomputer 20 will be those which will write into output latches for each pin of ports A and B. With a zero in DDR latch 66, data written into the output latch 86 will be ignored since this data cannot pass through buffer 10 62. Of course, some of the other pins are presumed to have had ones written into the data direction latches associated therewith and thus have been defined as inputs for the unit under test. These pins will have data from, the latch associated 5 therewith (which corresponds to output latch 86 shown in Fig. 5) placed onto the pin upon each write operation.
• the contents of the data direction latches such as latch 66 shown in F.ig. 5, will determine which pins from the I/O 0 ports of the 8755As are inputs and which pins are outputs. Subsequent write operations will write into the output latches for the I/O port. All subsequent read operations will either: (1) read the pins of the I/O ports; or (2) read an 5 externally stored instruction from the PROM of the 8755A into microcomputer 20.
• Fig. 6 shows the format for test procedure instructions residing in test procedure memory 22 (Fig. 2).
• test procedure memory 22 will be executed in the preferred embodiment by the 8748 microcomputer 20 to actually implement the test procedures described herein.
• an operating system including an appropriate interpreter may be readily written for read only memory 28 (Fig. 1) to implement the procedure shown in Fig. 4B.
• socket 10 is designed to accept SEM, or SEEM modules. It is well known that such modules have dedicated power supply and ground pins and thus 38 pins may variously be inputs outputs and unconnected.
• block 210 shows a generalized format for one of the three instructions which sets the states of the input/output pins as described hereinabove in connection with Fig. 5.
• this instruction format consists of five eight-bit bytes wherein the two most significant bits of the first byte will define the instruction and the remaining bytes will select which elements of the matrix are to be set according to the instruction defined by the above mentioned two bits.
• the elements of the pin matrix shown at block .210 and the connections to socket 10 (Fig. 3).
• the remaining rows of the pin matrix correspond to the remaining ports of the 8755As.
• Blocks 215 and 216 of Fig. 6 show instructions SET DATA, and SET INPUTS , respectively. As may be seen therefrom, the SET
• DATA instruction is identified by two zeros in the most significant positions of the first byte and the SET INPUTS instruction is identified by 01 in that position. The remainder of these instructions constitute the pin matrix shown in block 210.
• the SET INPUTS instruction 216 will have the following effect. For each position of the pin matrix at which a one appears, this instruction will be processed by microcomputer 20 having the ROM content set forth in table 2 to define those particular elements of the pin. matrix as inputs. From the foregoing discussion of Fig. 5 , it will be appreciated that this will cause a one to be written into the data direction latch 66 for each pin so defined as an input thus enabling the buffer 62 associated with that pin so that the contents of output latch 86 may be applied to the pin 60 in order to drive an input to the unit under test.
• SET DATA instruction 215 defines the expected inputs and outputs at each pin of the pin matrix for the next test to be executed on the unit under test.
• a SET OUTPUTS instruction shown at block 217 may be needed for certain types of devices. Microcomputer 20 upon interpreting and executing a set inputs instruction will cause all of the pins not defined as inputs to be defaulted to a definition of outputs. For some types of devices, certain pins may not properly be treated as either inputs or outputs. Therefore the combination of a SET INPUTS instruction 216 and a
• SET OUTPUTS instruction may be used and the SET
• OUTPUTS instruction should be understood to mask an Y pins not defined as outputs.
• SET INPUTS instruction 217 requires an entire byte consisting of the hex numbers B, Hi to precede the pi matrix.
• the SET OUTPUTS instruction may be retained in. its same format with the first two bits of the second byte being used to define the remaining two pins which are dedicated in the preferred embodiment described herein.
• a test may be conducted on the unit under test. This is executed in response to the VERIFY command 223 having a first nibble as hex B and the second nibble as hex H3.
• COMPLEMENT PIN (r,c) instruction 220 and the PULSE PIN (r,c) instruction 221 are provided.
• r is a binary number between zero and four defining one of the five rows of the pin matrix shown at 210. Thus r ° will have a value between 000 and 100.
• Block 200 also shows that the column element, c, is any three bit binary number between 0 and 7 (000,111).
• COMPLEMENT PIN instruction 220 simply inverts the value for that particular pin (r,c) that was previously defined by a SET DATA instruction 215. 0
• the PULSE PIN instruction 220 causes the particular pin (r,c) to be pulsed approximately once every millisecond. If the counter has been set by one of instructions 218 or 222, the particular pin (r,c) will be pulsed that number of 5 times.
• the SET COUNTER instructions 218 and 222 may be used to set a counter internal to the 8748 to any value between 0 and 255. As may be seen from instructions 218 and 222 and the definitions 0 set forth in definitional block 200, instruction 222 may be used whenever the number to be loaded in the counter is less than sixteen. When the counter is to be loaded with a number between 16 and 255, the two byte instruction, 218, is required. For a 5 SET COUNTER instruction to either m or n, m+1 and
• the remaining instructions of the test procedure instruction set are also shown on Fig. 6.
• the ROUTINE instruction 219 indicates that the bytes following the instruction code hex B, hex H5, are in machine language.
• the last machine language bytes of an instruction in the format of 219 will be understood to be a machine language JUMP instruction which will return the 8748 to its mode of interpreting the instructions shown in Fig. 6.
• the NO OP instruction 224 simply causes the program to continue execution. Similarly, BLANK DISPLAY instruction 226 requires no explanation. DELAY BY COUNTER instruction 227 is executed to cause the present state of the outputs at socket 10 to remain unchanged until the counter value (set by a previous SET instruction) counts down to zero.
• the CONTINUE instruction 225 indicates
• the last instruction is the DISPLAY instruction shown at 228.
• the occurrence of the byte B, H6 indicates that the following bytes contain six or seven bit ASCII code, the alpha-numeric equivalent of which is to be displayed.
• the most significant bit of this ASCII is used as a flag as is shown at block 228 and a one occurring at this bit position is indicative of the last byte of the ASCII code to be displayed.
• test procedure memory 22 is loaded to contain test routines for all circuit modules for a particular piece of equipment, such as a given airplane, the following procedure can be used. The user need only pull and test each module to ascertain if it passes any test in the repertoire. If it passes any test, the identification displayed may be considered a "go" signal. If the device fails to pass any test it is defective since the test routines for all possible modules have been applied. Thus, it is to .be understood that identification as used herein includes identification of a circuit as a working member of a known predetermined population of circuits.

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• 1982
  • 1982-03-30 EP EP19820901340 patent/EP0104169A4/fr not_active Withdrawn
  • 1982-03-30 JP JP57501389A patent/JPS59500437A/ja active Pending
  • 1982-03-30 WO PCT/US1982/000399 patent/WO1983003488A1/fr not_active Ceased

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