EP0141122B1 - Montage pour la mesure d'intervalles de temps courts - Google Patents

Montage pour la mesure d'intervalles de temps courts Download PDF

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Publication number
EP0141122B1
EP0141122B1 EP84110185A EP84110185A EP0141122B1 EP 0141122 B1 EP0141122 B1 EP 0141122B1 EP 84110185 A EP84110185 A EP 84110185A EP 84110185 A EP84110185 A EP 84110185A EP 0141122 B1 EP0141122 B1 EP 0141122B1
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EP
European Patent Office
Prior art keywords
output
circuit
pulse
time
circuit arrangement
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EP84110185A
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German (de)
English (en)
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EP0141122A1 (fr
Inventor
Klaus Welzhofer
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Siemens AG
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Siemens AG
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    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time

Definitions

  • the invention relates to a circuit arrangement for measuring short times according to the preamble of patent claim 1.
  • Computer-controlled test systems require fully automatic testing of individual electronic components, e.g. SSI, MSI, LSI, VLSI components etc., and assembled printed circuit boards, e.g. B. printed circuit boards, in addition to measuring devices for static measurement, z. B. for level evaluation, measurement of currents and voltages, etc., increasingly also measuring devices for dynamic measured value acquisition, z. B. for measuring the period of pulses, the pulse width, the rise and fall time of pulses.
  • An example of this is the testing of ECL-LSI circuits, in which even static module errors can only be detected by high-resolution measured value acquisition (in the ps range) of the pulse edge time or the delay time at the device under test output.
  • Time measurements can be performed on strictly repetitive test procedures, e.g. B. by using programmable oscillographs.
  • the acquisition of measured values according to this procedure requires at least 2000 cycles with a cycle time of ⁇ 10 ⁇ s.
  • Measurements in single-shot mode can be carried out with fast counters.
  • this method only leads to measured value errors of less than 1% from times greater than 1 ⁇ s.
  • a test device with which the pulse width can be measured is known from IBM Technical Disclosure Bull., Vol. 10, No. 12, May 1968, pp. 1888 to 1890.
  • a start and stop pulse is generated here, which are fed to a bistable flip-flop via logic circuits and a delay element.
  • the start pulse is fed to the set input of the stable flip-flop, the stop pulse to the reset input of the bistable flip-flop.
  • the output of the bistable flip-flop is connected to a ramp generator which is switched on when the bistable flip-flop is set and which is switched off when the bistable flip-flop is switched off.
  • the voltage output by the ramp generator is a pulse width to be measured and is subjected to an A-D conversion.
  • both the start pulse and the stop pulse are conducted via a delay element in order to ensure that the stop pulse is only fed to the bistable flip-flop when a gate circuit located in front of the bistable flip-flop switches the connection to the bistable flip-flop from the set input to the reset input Has.
  • a gate circuit located in front of the bistable flip-flop switches the connection to the bistable flip-flop from the set input to the reset input Has.
  • Such a circuit arrangement is not suitable for short times, e.g. B. lying in the ps range, to measure, since both the start pulse and the stop pulse must be routed via a line to the bistable flip-flop and for this reason, with the help of the gate circuit, switching the connection to the bistable flip-flop from the set input to the reset input is required. Measures for adjusting the circuit arrangement in order to avoid influencing the measurement result at the output by component tolerances cannot be found in this reference.
  • EP-A 0 051 531 specifies a circuit arrangement for measuring the time interval between two pulses.
  • a discharge circuit is used here, which is charged when a start pulse occurs, and is discharged again when the stop pulse occurs.
  • the voltage of the discharge circuit when the stop pulse occurs is a measure of the measured time.
  • the time is output digitally by counting the time difference.
  • the stop pulse is supplied to the discharge circuit with a delay in order to prevent the discharge circuit from being operated during the measurement process in the non-linear region of the discharge or charging characteristic. The elimination of the influence of the component tolerances on the measurement result is not provided here.
  • US Pat. No. 3,735,261 discloses a circuit arrangement and a method with which a received pulse can be measured.
  • the rise time, the pulse width and the descent time of a single pulse can be determined.
  • a voltage is first generated which is proportional to the amplitude of the pulse to be measured.
  • the pulse to be measured is delayed with the aid of delay elements of different delay times in order to be able to determine the amplitude of the pulse to be measured at different times and to be able to relate it to the peak value of the pulse.
  • a rise ramp is generated according to the start-stop method and results in an analog voltage element that is proportional to the measured time interval.
  • a time-amplitude converter is described in Instruments and Experimental Techniques, Vol. 23, No. 5, Part 1 (1980), pp. 1155-1157.
  • a charging circuit is also used here to convert the time interval between the start pulse and the stop pulse into a voltage.
  • a delay element is arranged in the signal path between the input for the start pulse and the input for the stop pulse and the discharge circuit in order to compensate for the influence of the delay times of the integrated circuits used. The compensation takes place by changing the delay times of the delay elements, ie the delay elements must be set in accordance with the properties of the integrated circuits used. This way to see the influence of different properties of the integrated Avoiding circuits on the measurement signal requires a relatively large effort.
  • the object on which the invention is based is to provide a circuit arrangement for measuring short times, with which dynamic measurement problems can also be solved, in particular single-shot operation is possible, which operates with a high measurement value resolution in the ps range and which is adjustable so that the Component tolerances of the circuit arrangement do not influence the measurement result at the output.
  • This object is achieved in a circuit arrangement of the type specified at the outset according to the characterizing part of patent claim 1.
  • This setting of the voltage threshold of the analog-digital converter ensures that the tolerances of the components of the circuit arrangement have no influence on the measurement result and that the discharge characteristic of the time-voltage converter is only used in the linear range for time-voltage conversion.
  • This adjustment of the circuit arrangement is achieved in that the delay elements are equipped with different delay times.
  • a preliminary stage is preferably connected upstream of the first and second delay elements, to which the measuring pulse is supplied.
  • this preliminary stage consists of a comparator, to which the measuring pulse and an adjustable reference variable can be fed, a differentiating element connected to the output of the comparator, and a gate circuit arranged between the differentiating element and the delay element.
  • each gate circuit in the pre-stage is preferably connected to an enable flip-flop which emits an enable signal when the gate circuit is to be open for the start or stop pulse and whose reset input is connected to the output of the associated delay element.
  • the time-voltage converter expediently consists of a differential amplifier, the inputs of which are connected to the outputs of the bistable flip-flop, of a discharge circuit with an adjustable capacitor which is connected to the one output of the differential amplifier for discharge with a constant current, and of a switch-off circuit Precharge circuit, which is connected to the discharge circuit for precharging the discharge circuit to a defined initial value.
  • a device under test PF is shown with an input E and an output A.
  • the test object PF is supplied with a test signal at the input E, which leads to a test object signal at its output A.
  • the temporal relationships of this test object signal at output A are measured with the aid of the circuit arrangement SH.
  • the circuit arrangement SH has two inputs ES1 and ES2.
  • the input ES1 can either be connected to the input E of the test object PF or to the output A of the test object.
  • the input ES2 of the circuit arrangement SH is connected to the output A of the device under test PF. If the input ES1 of the circuit arrangement SH is connected to the input E of the test object PF, z. B.
  • the time can be measured, which elapses until, due to a test signal at input E, the device under test signal appears at output A. If, on the other hand, the input ES1 is connected to the output A, the rise or fall time of the device under test or its pulse duration can be measured with the circuit arrangement SH.
  • the signal which is fed to the input ES1 is called the measuring pulse SN1
  • the signal which is fed to the input ES2 is called the measuring pulse SN2.
  • the measuring pulses SN1 and SN2 can be identical or different.
  • the measuring pulse SN1 is fed to the comparator CP1, which is also supplied with an adjustable reference voltage UR1.
  • the measuring pulse SN2 is fed to a comparator CP2, to which an adjustable reference voltage UR2 is also fed.
  • the comparators CP1, CP2 then emit a signal at the output when the measuring pulses SN1 or SN2 exceed or fall below the reference voltages UR1 or UR2.
  • Figure 4 shows the signal at the output B of the comparator CP1 and the signal at the output C of the comparator CP2. It has been assumed that the reference voltage UR1 corresponds to the value SW1 and the reference voltage UR2 to the value SW2.
  • the rise time TR or the fall time TF of the measuring pulse SN can thus be determined by appropriate selection of the edges of the signal at the output B or C of the comparators CP1 and CP2 will.
  • the pulse duration can also be measured by appropriately setting the reference voltages and selecting the comparator output edges.
  • the signals at the outputs B and C of the comparators CP1 and CP2 are each fed to a differentiator DG1 and DG2, which generate needle pulses SZ3 and SZ4 (FIG. 4) from the signals B and C.
  • DG1 and DG2 which generate needle pulses SZ3 and SZ4 (FIG. 4) from the signals B and C.
  • the desired needle pulses SZ3 and SZ4 can be selected for measurement.
  • These selected needle pulses from the pulse train SZ3 and SZ4 are fed to a delay element VZ1 or VZ2.
  • the output of the delay element VZ1 is connected to the set input of a bistable flip-flop FF, the output of the delay element VZ2 to its reset input.
  • the bistable flip-flop FF is released with the aid of an enable signal SF.
  • the selection signals SKO, SK1 and SK2 can be such that, for. B. needle pulses at the output C of the comparator CP2 to the set input of the flip-flop FF and accordingly needle pulses at the output B of the comparator CP1 are fed to the reset input of the flip-flop FF. Or each needle pulse assigned to the rising edge or each needle pulse assigned to the falling edge can be selected at output B or C, etc.
  • the output pulse width of the bistable flip-flop FF corresponds to the time difference between the selected needle pulses that have been fed to the set or reset input of the flip-flop FF.
  • this pulse width corresponding to the time to be measured is converted into a voltage proportional to the time.
  • the analog-digital converter ADU a digital value is determined from the time, which is output at the output SA.
  • the analog-to-digital converter ADU uses a signal EOC to indicate when the voltage has been converted into a binary value. This signal EOC is emitted at the output, but is also fed to the time-voltage converter ZSW at the same time. The signal EOC brings the time-voltage converter ZSW back to its initial state and thus prepares it for the next measurement.
  • the time-voltage converter ZSW can be designed such that a signal is output at the output ME if the measuring range is exceeded.
  • the reference voltages UR1 and UR2 can be set using digital-to-analog converters DAW1 and DAW2. These are supplied with the binary value SL1 or SL2, from which they then generate the reference voltage UR1 and UR2.
  • FIG. 2 and Figure 3 show a more detailed implementation of the circuit arrangement SH.
  • the comparator CP1 and the comparator CP2 have a non-inverting and an inverting output. Each output leads to an associated differentiator DG11 and DG12 for the comparator CP1 and DG21 and DG22 for the comparator CP2.
  • the outputs of the differentiators DG11 and DG12 are connected to a gate circuit consisting of gate elements TR1 and TR2.
  • the differentiators DG21 and DG22 are connected to a gate circuit consisting of gate elements TR3 and TR4.
  • a positive needle pulse according to FIG. 4 is emitted at the output of the differentiating element DG11 when the rising edge of the measuring pulse SN exceeds the reference voltage UR1.
  • a positive needle pulse is emitted at the output of the differentiating element DG12 when the falling edge of the measuring pulse SN falls below the reference voltage UR1.
  • These needle pulses are summarized as signals SZ3 and SZ4 in Figure 4.
  • either the output of the differentiating element DG21 or the output of the differentiating element DG22 can be switched through to the output by the gate elements TR3 and TR4, depending on the selection signal SK2.
  • the outputs of the gate elements TR1 and TR2 are connected together and connected to the input of a delay element VZ1, the output of which leads to the set input S of the bistable flip-flop FF.
  • the outputs of the gate elements TR3 and TR4 are also connected together and connected to the input of a delay element VZ2, the output of which is connected to the reset input R of the bistable flip-flop FF.
  • the bistable flip-flop FF thus determines the time interval between the occurrence of the needle pulse at the output of the delay element VZ1 and the occurrence of the needle pulse at the output of the delay element VZ2.
  • the delay elements VZ1 and VZ2 are expediently designed such that the delay time of the delay element VZ2 is greater than that of the delay element VZ1. The advantage of this is explained below.
  • release flip-flops FG1 and FG2 are provided.
  • the release flip-flop FG1 is connected to the gate elements TR1 and TR2, the release flip-flop FG2 to the gate elements TR3 and TR4. If a measuring pulse SN is selected, the release flip-flops FG1 and FG2 are set and the gate elements TR1 to TR4 are thus released.
  • the reset input of the release flip-flop FG1 is connected to the output of the delay element VZ1, the reset input of the release flip-flop FG2 to the output of the delay element VZ2.
  • the release flip-flops FG1 and FG2 are then reset again and the gate elements TR1 to TR4 are blocked when the needle pulse selected by the gate elements TR at the output of the delay elements VZ1 and VZ2 appears and is thus fed to the bistable flip-flop FF.
  • the delay time of the delay elements VZ1 and VZ2 is chosen so that the release flip-flops FG1 and FG2 are already reset before a needle pulse assigned to another measuring pulse SN can reach the gate elements TR.
  • the release flip-flops FG1 and FG2 and the bistable flip-flop FF are connected with their reset inputs R to a line for a reset pulse SR.
  • the flip-flops FG1 and FG2 and the bistable flip-flop FF are reset by pulses generated in the circuit arrangement.
  • Figure 2 shows an embodiment of the gate circuit TR according to Figure 1 such that a transition of the signal at the output A of the comparator CP1 to the delay element VZ2 and the signal at the output B of the comparator CP to the delay element VZ1 is not possible. Due to slight changes in the gate circuit TR, which are within the scope of the expert ability, a corresponding structure of the gate circuit is easily possible.
  • the outputs of the bistable flip-flop FF are connected to a differential amplifier DV (see FIG. 3).
  • One output of the differential amplifier DV is connected to a reference potential P1, z. B. ground connected.
  • the other output of the differential amplifier DV leads to a discharge circuit ET, which contains a capacitor CO.
  • the bistable flip-flop FF is not set, the differential amplifier DV is connected to the potential P1, and the discharge circuit ET is not discharged via the differential amplifier DV. If, on the other hand, the bistable flip-flop FF is set, the differential amplifier DV discharges the discharge circuit ET with a constant current. The duration of this unloading process is thus determined by the period of time that the bistable flip-flop FF is in the set state. However, this time corresponds to the time to be measured.
  • the discharge circuit ET is also connected to a precharge circuit AT, by means of which the discharge circuit ET is charged to a defined initial voltage, while the differential amplifier DV is connected to the potential P1.
  • the precharge circuit AT connects the discharge circuit ET to a voltage UV during this time.
  • the signal SZ3 occurs at the output of the gate elements TR1 and TR2
  • the precharge circuit AT is separated from the discharge circuit ET and the discharge circuit ET can only be influenced by the differential amplifier DV.
  • the precharge circuit AT is switched off or on with the aid of a bistable flip-flop KS1, to which the signal SZ3 is fed.
  • the flip-flop KS1 is only reset and thus the precharge circuit AT is switched on again to the discharge circuit ET when the conversion of the voltage output at the output of the discharge circuit ET into a binary value by the analog-digital converter ADU has ended, that is to say the signal EOC issues.
  • the differential amplifier DV and the discharge circuit ET are constructed such that the capacitor CO contained in the discharge circuit ET is discharged with a constant current during the time during which the bistable flip-flop FF is set. This converts time into tension.
  • the discharge characteristic curve used is shown in FIG. 5.
  • the capacitor CO of the discharge circuit z. B. pre-charged to + 10 volts.
  • the differential amplifier DV switches over to the discharge circuit ET the capacitor CO is discharged with constant current, i. H. the characteristic curve according to FIG. 5 passes into the unloading area TE.
  • the voltage across the capacitor CO reaches zero volts. If the measurement is finished, this is indicated by the signal EOC, then the precharge circuit AT is connected again to the discharge circuit ET and the capacitor CO is recharged to + 10 volts. A new time measurement can then begin again and thus a new discharge of the capacitor CO.
  • An operational amplifier OP1 is connected to the output of the discharge circuit ET and is connected in such a way that the discharge circuit ET is not loaded.
  • a reference voltage UR3 is fed to the operational amplifier OP1, which is set in such a way that work is carried out only in the linear region of the discharge characteristic.
  • the output of the operational amplifier OP1 is finally connected to the analog-digital converter ADU, which generates a binary value at the output SA from the voltage output by the operational amplifier OP1.
  • FIG. 3 shows a further flip-flop KS2, to which the signal SZ4 is fed from the output of the gate elements TR3 and TR4 via a delay element VZ3.
  • the flip-flop KS2 With this signal SZ4, the flip-flop KS2 is brought into its one state, in which it outputs the release signal SC for the analog-digital converter ADU at the output.
  • the ADU analog-digital converter is only switched on when a needle pulse has occurred at the output of the gate elements TR3 and TR4. This needle pulse is delayed by the delay element VZ3 in such a way that the analog-digital converter ADU is not switched on too early.
  • the flip-flop KS2 can also be used to determine whether the measuring range has been exceeded.
  • the output of the flip-flop KS1 is connected to a timing element Z1, the inverting input of which, together with the output of the delay element VZ3, is connected to an AND gate UD1, which leads to the input of the flip-flop KS2.
  • the output of the timing element Z1 is connected to a further timing element Z2, which is connected to a further AND element UD2.
  • the AND gate UD2 is still connected to the other output of the flip-flop KS2 and outputs the measurement range exceeding signal ME at its output and continues to the reset input of the flip-flop KS1.
  • the permissible measuring range is determined with the help of timer Z1. If the time between the occurrence of the signal SZ3 and the signal SZ4 to becomes large, then a signal will appear at the inverting output of the timing element Z1, which blocks the AND gate UD1, so that the flip-flop KS2 remains in the reset state. The result of this is that the AND gate UD2 is enabled and the measuring range exceeding signal ME can occur.
  • the output of the AND gate UD2 is also connected to the reset input of the bistable flip-flop KS1, so that it is also reset when the measuring range exceeding signal ME occurs. Furthermore, if the measuring range is exceeded, the release signal SC for the analog-digital converter ADU is not generated, so that it is not released.
  • the output of the bistable flip-flop KS1, on which the signal SZ5 appears, is connected to the bistable flip-flop FF, so that this is reset when the signal SZ5 occurs. Then the evaluation process of the bistable flip-flop FF is ended in any case.
  • the time-to-voltage converter ZSW of FIG. 1 thus consists in any case of the differential amplifier DV, the discharge circuit ET, the precharge circuit AT, the bistable flip-flop KS1 and possibly the bistable flip-flop KS2, if a permissible measuring range is provided.
  • the inputs of the comparators CP1 and CP2, on which the measuring pulse occurs are short-circuited and the reference voltages UR1 and UR2 are set to the same value. Since the delay elements VZ1 and VZ2 have different values, the bistable flip-flop FF is set briefly. Consequently, the discharge circuit ET is briefly discharged from the differential amplifier DV. The reference voltage UR3 of the operational amplifier OP1 is now set so that this discharge is not yet evaluated by the analog-digital converter ADU, that is to say the binary value at the output SA remains zero.
  • This measure ensures that component tolerances of the circuit arrangement do not influence the measurement result at the output of the analog-digital converter ADU, and it is also achieved that the start of the discharge characteristic (see FIG. 5) in which the characteristic does not is linear, is not used for time-voltage conversion. Only the linear range of the discharge characteristic is used for the conversion.
  • the delay time of the timing element Z1 and the steepness of the discharge characteristic, and thus the range in which a time-voltage conversion can be carried out, must correspond to one another.
  • the discharge characteristic is selected by adjusting the capacitance of the capacitor CO such that the discharge characteristic according to FIG. 5 has just reached zero volts at the maximum time. Accordingly, the delay time of the timing element Z1 must also be selected.
  • the digital value SL of the reference voltage UR is transferred into a memory SP1 and into a memory SP2 when clock signals TS occur.
  • the memory SP1 is connected to the digital-to-analog converter DAW1, the memory SP2 to the digital-to-analog converter DAW2.
  • the binary value stored in the memory SP is converted by the digital-to-analog converter DAW into a proportional current, from which the reference voltage UR1 or UR2 is generated via an operational amplifier.
  • the reference voltage UR1 and the measuring pulse SN1 or the reference voltage UR2 and the measuring pulse SN2 are fed to the comparators CP1 and CP2.
  • the outputs of the comparators CP1 and CP2 lead to the differentiators DG11, DG12 or DG21 and DG22.
  • the differentiators DG are implemented as short-circuited lines at the end, which are connected to a fixed potential. With the help of the short-circuited lines, symmetrical needle pulses are generated.
  • the gate elements TR1, TR2, TR3 and TR4 are implemented in FIG. 6 as NOR elements, to which the needle pulses, a selection signal SK and the output signal from the release flip-flop FG1 and FG2 are supplied.
  • the outputs of the gate elements TR1 and TR2 lead to the delay element VZ1, which is implemented as a line.
  • the outputs of the gate elements TR3 and TR4 lead to the delay element VZ2 implemented as a line.
  • the delay element VZ2 has a longer delay time than the delay element VZ1, e.g. B. 5 ns.
  • the signals supplied to the circuit arrangement have SR, SK, SF TTL levels, these are converted into ECL levels with the aid of TTL-ECL converters. It is also necessary that the enable signal SF is fed to a monoflop to generate a pulse after conversion into an ECL signal.
  • FIG. 7 shows an exact implementation of FIG. 3.
  • the signals SZ1 and SZ2 are fed to the differential amplifier DV.
  • a constant current source KSQ1 is connected to the emitters of the differential transistors T3 and T4.
  • B. a constant current of 30 mA flows.
  • the constant current flows either via the differential transistor T3 to the potential P1 or via the differential transistor T4 to the discharge circuit ET.
  • the discharge circuit ET essentially consists of the capacitor CO, which consists of a capacitor with a fixed capacitance and a capacitor with a variable capacitance.
  • the differential amplifier DV is connected to the connection point VP, specifically via a transistor T10 in the basic circuit. This transistor compensates for the Miller effect of the differential transistor T4.
  • the precharge circuit AT which consists of the constant current source KSQ2 and can be switched off via the transistor T1, is connected to the discharge circuit ET.
  • the constant current source KSQ2 is connected to the connection point VP via diodes D1, D2, D3. It is controlled via an operational amplifier OP2, at the inverting input of which the voltage UV is present.
  • the non invertie rende input of the operational amplifier OP2 is connected to the connection point VP. This feedback causes the voltage at the connection point VP to be approximately + 10 volts as long as the constant current source KSQ2 is switched on.
  • the constant current source KSQ2 is switched off via the transistor T1, the base of which is connected to a further differential amplifier DV1.
  • This differential amplifier DV1 is connected to the bistable flip-flop KS1, to which the signal SZ3 is fed.
  • the transistor T1 is turned on via the differential amplifier DV1, so that there is approximately ground potential at the collector of the transistor T2 of the constant current source KSQ2.
  • the diodes D1 to D3 are connected in series in order to keep the total capacitance as small as possible.
  • the signal SZ4 is applied to the input of the bistable flip-flop KS2 via a delay element VZ3 implemented as a line.
  • the output of the bistable flip-flop KS1 is also present at this input via the timing element Z1, which is implemented as a monoflop.
  • the timing element Z2 is also implemented as a monostable multivibrator. The interaction of the bistable flip-flop KS2 with the timing elements Z1 and Z2 and with the delay line VZ3 has already been described above.
  • a commercially available module can be used as the ADC analog-digital converter. This also applies to the digital-to-analog converters DAW1 and DAW2, the operational amplifiers OP and the comparators CP. The remaining components of FIGS. 4 and 7, which are not described, are used in a known manner for the necessary wiring of the individual components used.
  • Y is a voltage of 0.8 V.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Measurement Of Current Or Voltage (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Analogue/Digital Conversion (AREA)
  • Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)

Claims (14)

1. Montage pour la mesure d'intervalles de temps brefs et pour la délivrance de l'intervalle de temps mesuré sous forme numérique et auquel sont envoyées une impulsion de départ marquant le début de l'intervalle de temps à mesurer et une impulsion d'arrêt indiquant la fin de l'intervalle de temps à mesurer et dans lequel l'impulsion de départ est envoyée à une entrée de positionnement (S) d'un circuit à bascule bistable (FF) et l'impulsion d'arrêt est envoyée à une entrée de remise à l'état initial (R) du circuit à bascule bistable (FF), et dans lequel la sortie du circuit à bascule bistable est reliée à un convertisseur temps/tension (ZSW), qui contient un circuit de décharge (ET) et produit une tension proportionnelle à l'intervalle de temps, et il est prévu un premier circuit de retard (VZ1) et un convertisseur analogique/numérique (ADU), caractérisé par le fait que l'impulsion de départ est envoyée audit premier circuit de retard, qu'il est prévu un second circuit de retard (VZ2) fournissant un temps de retard supérieur à celui du premier circuit de retard et auquel est envoyée l'impulsion d'arrêt, que le premier circuit de retard (VZ1) est relié à l'entrée de positionnement du circuit à bascule bistable (FF) et que le second circuit de retard (VZ2) est relié à l'entrée de remise à l'état initial du circuit à bascule bistable (FF), et qu'à la sortie du convertisseur temps/tension (ZSW) est raccordé le convertisseur analogique/numérique (ADU), qui comporte un seuil de tension réglable qui est réglé de telle sorte que, lors de la réunion des entrées (ES1, ES2) du montage, le convertisseur analogique/numérique (ADU) délivre la valeur binaire pour zéro.
2. Montage suivant la revendication 1, caractérisé par le fait que pour la mesure des conditions temporelles dans le cas d'une impulsion de mesure (SE) en vue de la production du signal de départ ou du signal d'arrêt, un étage amont, auquel l'impulsion de mesure est envoyé, est branché respectivement en amont du premier ou du second circuit de retard (VZ1 ou VZ2), et que l'étage amont contient, pour la production de l'impulsion de départ ou de l'impulsion d'arrêt, respectivement un comparateur (CP1 ou CP2), auquel est envoyée respectivement l'impulsion de mesure et respectivement une tension de référence réglable (UR1 ou UR2), un circuit différentiateur (DG1 ou DG2) raccordé à la sortie du comparateur (CP1 ou CP2), et un circuit de porte (TR) monté entre le circuit différentiateur (DG1 ou DG2) ou le circuit de retard (VZ1 ou VZ2).
3. Montage suivant la revendication 2, caractérisé par le fait que chaque circuit (TR1, TR2 ou TR3, TR4) est relié à une bascule bistable d'autorisation (FG1 ou FG2), qui délivre un signal d'autorisation lorsque le circuit de porte doit être ouvert pour l'impulsion de départ ou l'impulsion d'arrêt.
4. Montage suivant la revendication 3, caractérisé par le fait que l'entrée de remise à l'état initial de la bascule d'autorisation (FG1 ou FG2) est reliée à la sortie du circuit de retard associé (VZ1 ou VZ2).
5. Montage suivant l'une des revendications 2 à 4, caractérisé par le fait que chaque comparateur (CP1, CP2) comporte une sortie non inverseuse et une sortie inverseuse, que la sortie non inverseuse et la sortie inverseuse sont reliées respectivement par l'intermédiaire d'un circuit différentiateur (DG11, DG12 ou DG21, DG22) à un élément formant porte (TR1, TR2 ou TR3, TR4) du circuit de porte et qu'un signal respectif de sélection (SK1 ou SK2) peut être appliqué à l'élément formant porte (TR).
6. Montage suivant la revendication 5, caractérisé par le fait que le circuit différentiateur (DG) est constitué par une ligne court-circuitée.
7. Montage suivant l'une des revendications précédentes, caractérisé par le fait que le convertisseur temps/tension (ZSW) est constitué par un amplificateur différentiel (DV), qui est relié aux sorties du circuit à bascule bistable (FF), par le circuit de décharge (ET) comportant un condensateur réglable (CO), qui est relié à une première sortie de l'amplificateur différentiel, pour réaliser la décharge avec un courant constant, et par un circuit de précharge (AT) pouvant être débranché, qui est relié au circuit de décharge pour réaliser la précharge du circuit de décharge à une valeur définie.
8. Montage suivant la revendication 7, caractérisé par le fait que le circuit de précharge (AT) est constitué par une source de courant constant (KSQ2), dont la sortie est reliée par l'intermédiaire de diodes (D1, D2, D3) au point de liaison (VP) entre le condensateur (CO) et l'amplificateur différentiel (DV), par un amplificateur opérationnel (OP2), dont la sortie est raccordée à l'entrée de la source de courant constant (KSQ2) et dont l'entrée non inverseuse est reliée au point de liaison (VP) et dont l'entrée inverseuse est placée à une tension de charge de base (UV), et par un transistor de commutation (T1), qui est raccordé à la sortie de la source de courant constant (KSQ2) et dont l'électrode de base est reliée à une sortie d'un second amplificateur différentiel (DV) qui, après l'apparition de l'impulsion de départ (SZ3), place le transistor de commutation (T1) à l'état conducteur et déconnecte par conséquent la source de courant constant (KSQ2) par rapport au condensateur (CU).
9. Montage suivant la revendication 8, caractérisé par le fait qu'un transistor (T10) monté en base commune est branché entre le point de liaison (VP) et la sortie du premier amplificateur différentiel (DV) pour réaliser la compensation de l'effet de Miller du transistor (T4) de l'amplificateur différentiel.
10. Montage suivant l'une des revendications 2 à 9, caractérisé par le fait qu'il est prévu une troisième bascule bistable d'autorisation (KS2), dont l'entrée de positionnement est reliée à un circuit ET (DU1), à une entrée duquel le signal d'arrêt (SZK) est appliqué et à l'autre entrée duquel le signal de départ (SZ3) est appliqué, sous forme inversée, par l'intermédiaire du circuit de temporisation (Z1) déterminant la plage de mesure, et qu'un signal d'autorisation (SC) pour le convertisseur analogique/numérique (ADU) est envoyé à une sortie de la troisième bascule bistable d'autorisation (KS2).
11. Montage suivant la revendication 10, caractérisé par le fait que l'autre sortie de la troisième bascule bistable d'autorisation (KS2) est reliée à un circuit ET (UD2), à l'autre entrée duquel est raccordé un second circuit de temporisation (Z2) relié au premier circuit de temporisation (Z1) et à la sortie duquel il apparaît un signal (ME) de dépassement de la plage de mesure.
12. Montage suivant la revendication 11, caractérisé par le fait qu'il est prévu un autre circuit à bascule bistable (KS1), à l'entrée de positionnement duquel est envoyé le signal de départ (SZ3) et à l'entrée de remise à l'état initial duquel est envoyé le signal (ME) de dépassement de la plage de mesure, et dont une sortie est reliée au second amplificateur différentiel (DV1) et au premier circuit de temporisation (Z1
13. Montage suivant la revendication 12, caractérisé par le fait que le convertisseur analogique/numérique (ADU) produit un signal de sortie (EOC) lorsque la conversion en une valeur numérique est terminée, et que le signal de sortie (EOC) est envoyé à l'entrée de remise à l'état initial de l'autre circuit à bascule bistable (KS1) et à l'entrée de remise à l'état initial de la troisième bascule bistable d'autorisation (KS2).
14. Montage suivant l'une des revendications précédentes, caractérisé par le fait que le temps de retard du second circuit de retard (VZ2) diffère du temps de retard du premier circuit de retard (VZ1) de telle sorte que le début de la caractéristique de modification de charge du circuit de décharge (ET) n'est pas utilisé pour la conversion temps/tension.
EP84110185A 1983-09-08 1984-08-27 Montage pour la mesure d'intervalles de temps courts Expired EP0141122B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT84110185T ATE34852T1 (de) 1983-09-08 1984-08-27 Schaltungsanordnung zur messung kurzer zeit.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19833332484 DE3332484A1 (de) 1983-09-08 1983-09-08 Schaltungsanordnung zur messung kurzer zeiten
DE3332484 1983-09-08

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EP0141122A1 EP0141122A1 (fr) 1985-05-15
EP0141122B1 true EP0141122B1 (fr) 1988-06-01

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EP (1) EP0141122B1 (fr)
AT (1) ATE34852T1 (fr)
DE (2) DE3332484A1 (fr)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2540730B (en) * 2015-05-11 2017-09-13 Thermo Fisher Scient (Bremen) Gmbh Time interval measurement

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1520487A (fr) * 1967-01-24 1968-04-12 Onera (Off Nat Aerospatiale) Procédé et appareil de chronométrie
US3735261A (en) * 1971-06-07 1973-05-22 Northrop Corp Pulse analyzer
FR2493553A1 (fr) * 1980-10-31 1982-05-07 Dassault Electronique Appareillage pour la datation precise d'un evenement par rapport a une reference de temps

Also Published As

Publication number Publication date
ATE34852T1 (de) 1988-06-15
DE3332484A1 (de) 1985-03-28
DE3471773D1 (en) 1988-07-07
EP0141122A1 (fr) 1985-05-15

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