EP0159849A2 - Generierung von graphischen Anzeigen - Google Patents

Generierung von graphischen Anzeigen Download PDF

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Publication number
EP0159849A2
EP0159849A2 EP85302436A EP85302436A EP0159849A2 EP 0159849 A2 EP0159849 A2 EP 0159849A2 EP 85302436 A EP85302436 A EP 85302436A EP 85302436 A EP85302436 A EP 85302436A EP 0159849 A2 EP0159849 A2 EP 0159849A2
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EP
European Patent Office
Prior art keywords
pixel
vector
information
visual characteristic
data
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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EP85302436A
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English (en)
French (fr)
Inventor
Gregory Michael Burke
David Oakley
Michael Eugene Jones
Donald Irwin Parsons
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MEGATEK CORP
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MEGATEK CORP
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Priority claimed from US06/600,106 external-priority patent/US4808988A/en
Application filed by MEGATEK CORP filed Critical MEGATEK CORP
Publication of EP0159849A2 publication Critical patent/EP0159849A2/de
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G1/00—Control arrangements or circuits, of interest only in connection with cathode-ray tube indicators; General aspects or details, e.g. selection emphasis on particular characters, dashed line or dotted line generation; Preprocessing of data
    • G09G1/04—Deflection circuits ; Constructional details not otherwise provided for

Definitions

  • This invention relates to high resolution raster graphics image generating systems and more particularly to such systems using subpixel addressing to improve spatial resolution and reduce aliasing.
  • Graphical image display systems provide an array of discrete points known as pixels at which emitted light intensities may be independently controlled. Each pixel may represent a single intensity for a monochrome system or three different primary color intensities for a three color system.
  • a display image is generated by effectively sampling light intensities at each point of a source image which corresponds to a display pixel and then illuminating each pixel in accordance with its corresponding sampled light intensity value.
  • the pixel light intensity values are generated by a computer as a prediction of what the values would be if sampled from an actual image of a selected object under selected light conditions.
  • Raster scan display systems typically provide a two dimensional rectangular array of pixels arranged in rows and columns.
  • a frame buffer stores intensity values for each pixel in a location which may be addressably accessed in response to the row and column position of the pixel within the array.
  • the corresponding illumination data is read from the frame buffer and used to control the intensity of the scanning beam at each pixel and hence the corresponding illumination intensity of the pixel.
  • a commonly used solution to aliasing is to pass the intensity values through a low pass filter as discussed by Foley and VanDam supra pp. 436-437.
  • this technique requires lines to be at least two pixels wide and results in lines with blurred or fuzzy edges.
  • the technique does not work well or moderate with low resolution monochrome or color mapped systems in which a high resolution range of continuous values is not available for each color. Even with high dynamic resolution full color systems, an averaging of intensities at intersecting boundaries of different colors results in colors which do not relate to either of two intersecting colors.
  • dot matrix printer systems which decrease the apparent sampling effects of a displayed image by overstriking an image one or more times with the print hammers offset by a subpixel distance for each different overstrike pass. Because the same display pattern is used for each pass, the display buffer storage requirements are not increased. This arrangement results in thickened, boldface lines and does not really increase the resolution of the displayed image. It is particularly unsatisfactory where narrow, high resolution lines are desired. Furthermore, the operating speed is substantially decreased.
  • a single dimension vector generator is disclosed in U.S. Patent 3,996,585 to Hogan et al. Integer steps are assumed in the vertical direction while the generator produces horizontal dimension pixel data. A Z dimension cannot be accommodated and the vector generator is used only for spatial information, not color or intensity information.
  • Video image data is typically provided to a digital vector generator as lists of lines or polygons defined by end points and corners or line slopes. Visual characteristic information is provided for each line or polygon as part of the test.
  • the spatial information is utilized to initialize digital vector generators which then proceed to generate spatial address locations which define each line of a display as a plurality of adjacent pixel points.
  • the vector generators generate address information defining X, Y and Z coordinates which locate the line in three dimensional display space.
  • a frame buffer store having an address location corresponding to each pixel location in a display image.
  • Visual characteristic information defining the visual display characteristics of each pixel must be stored at the address corresponding to the pixel.
  • the visual characteristic information may have different portions defining intensity and hue, may have different portions defining Red, Green and Blue (RGB) color intensities, or may have information which is to address a color map table to produce the desired visual characteristic information.
  • a central processing unit may also determine the visual characteristic information for the next point.
  • the spatial address information is used to address the frame buffer and the visual characteristic information is written into the selected address location.
  • a graphic image generating system as defined by claim 1 hereinafter.
  • a digital vector generator system as defined by claim 14 hereinafter.
  • a graphic image generating system in accordance with the invention increases the effective spatial resolution of a displayed image without increasing the number of pixels used to display the image.
  • the system includes a preferably rectangular array of pixels, a frame buffer and a visible image generation device such as a cathode ray tube (CRT) coupled to display an image defined by data stored in the frame buffer.
  • the frame buffer includes a storage location for each pixel in the video image and at each storage location stores information indicating at least one visual characteristic of the pixel including a spatial displacement from a normal background or zero displacement position of the pixel within the array of display image defining pixels.
  • the visual image generation device receives the visual characteristic indicating information from the frame store for each pixel in sequence and visually manifests the pixel in response thereto.
  • Each pixel is assigned a normal position within a uniformly spaced rectangular array of pixels and is displaced from the normal position in accordance with the spatial displacement information indicating the true location of the pixel.
  • a pixel boundary can be moved horizontally left or right (in the raster scan dimension) by selectively varying the instant at which the intensity of a pixel is communicated to the display device.
  • an early presentation of the visual intensity signal causes the pixel to move to the left while a later presentation causes the pixel to move to the right.
  • subpixel displacement is accomplished by adding a subpixel vertical deflection mechanism to the conventional vertical deflection system for the display.
  • a subpixel vertical deflection mechanism for example, in thee case of a CRT, a set of single turn, low inductance subpixel deflection coils can be disposed between the CRT funnel and the existing deflection coils. Both horizontal and vertical subpixel addressing can thus be superimposed upon conventional CRT vertical and horizontal deflection circuits without modifying either.
  • a high speed graphics display digital vector generator system in accordance with the invention preferably includes a three dimensional spatial digital vector generator as well as a three dimensional visual characteristic digital vector generator coupled to operate synchronously therewith.
  • a vector processing subsystem responds to the generated visual characteristic vector information with a wide range of selectable alternatives.
  • the three visual characteristic vector generators operating synchronously with spatial vector generators generate multi-dimensional visual characteristic vectors.
  • the vector processing system includes a normalizing circuit coupled to receive the three visual characteristic vectors and generate a normalized intensity value suitable for use in Phong shading in response thereto.
  • a pattern shape multiplexer responds to two of the visual characteristic vectors by generating an output signal that is representative of a selected resolution of each of the received vectors.
  • a writeable pattern RAM is coupled to address by the output of the pattern shape multiplexer to generate an output signal that may be advantageously used to represent hues in any selected solid or textured pattern. Because the visual characteristic vector generators hue patterns within the texture RAM may be readily correlated with spatial patterns in the displayed video image.
  • a color intensity multiplexer is coupled to received output data from the pattern RAM and from the normalizing circuit and combine the outputs into selected data patterns for storage in a frame buffer for request output to a video display device.
  • the color intensity multiplexer is particularly advantageous when used to combine intensity information from the normalizing circuit with hue information from the pattern RAM to form a pixel display data word having a selected resolution for each of the two constitutents.
  • a raster scan graphic image generating system 10 having an image generation and storage system 12 providing a source of images to be displayed.
  • the image generation and storage system 12 may be conventional in nature and in a typical system includes a data base storing the display list for each image to be displayed, communications interface circuits, and peripheral controller circuits including data entry devices such as keyboards, data tablets, and joy sticks.
  • a digital vector generator system 14 receives lists of image definition data from image generation and storage system 12 and converts such data to an array of pixels defining a display image.
  • the array of pixels is communicated to, and then stored in, a frame buffer memory 16.
  • the frame buffer memory 16 includes storage for a two-dimensional 768 x 576 array-of pixels which is deemed to have an origin at the upper lefthand corner of a rectangular image with a Y axis extending positive downward and an X-axis extending positive to the right.
  • For each pixel location within the buffer memory 16 there are stored 12 bits of video information as well as two bits of subpixel X address information and two bits of subpixel Y address information.
  • a Z-buffer 16a having a pixel location corresponding to each pixel location of the video display buffer memory and storing third dimension or Z-axis position information for each pixel position in a display.
  • the Z-axis is deemed to extend from the origin lying in the plane of the display screen positively away from the viewer perpendicular to the X and Y axes.
  • the current Z or depth value is retrieved from the addressed pixel location within the Z-buffer 16a and compared to the Z value of the new data.
  • the Z buffer 16a is set to a maximum positive value of 65, 535 (for 2 16 - 1 ).
  • the new data has a selected functional relationship to pre-existing old data such as being less than or equal to the Z value of the old data, indicating that the new data is at least as close to the viewer as the old data, then the new data is written into the frame buffer memory 16 with the Z coordinate value being written into the Z buffer 16a and the video display intensity and X, Y subpixel address data being written into the frame buffer 16. If the Z value of the new data is greater than the previously stored Z value at the indicated pixel address, (indicating that the new data is farther away from the viewer and hidden by a surface defined by the previously stored data) then writing of the new data into the frame-buffer memory 16 is inhibited and the new data is discarded.
  • the Z buffer inhibit function may be selectively enabled or disabled in accordance with a desired operating mode.
  • Each display buffer contains 12 intensity planes, 4 subpixel address planes and 2 overlay planes for text or cursors.
  • the single Z-buffer 16a stores depth coordinates. Only a first frame buffer can be addressed by the DVGs, but either buffer can be read by the video output subsystem. In normal operation, the second frame buffer is continuously read to refresh the display subsystem while the first buffer is updated. After the first buffer has been updated, the data is transferred into the second buffer. During this transfer period, the video output subsystem reads the first buffer.
  • the frame buffer memory 16 is accessed in raster scan order with the 12 bits of video display data being communicated to a color map RAM 18 which performs a transformation that converts the video data to a predetermined three color RGB representation with 8 bits maximum per color.
  • Color map RAM 18 functions as a color look-up table that is loaded from image generation and storage system 12. This allows a particular intensity and hue to be assigned to a given pattern of bits at a selected address within frame buffer 16.
  • An intensity control and horizontal subpixel deflection circuit 20 receives the RGB color intensity information from color map RAM 18 and the X and Y subpixel address information from frame buffer memory 16 for use in generating display control signals including three visual characteristic signals representing the RGB color intensity input to a cathode ray tube 22 which displays the stored image on the face 24 thereof and a set of vertical displacement signals which command the vertical displacement of a displayed pixel.
  • CRT 22 has a precision in-line (PIL) gun that emits three parallel electron beams that lie within a plane parallel to the horizontal raster scan direction.
  • PIL precision in-line
  • the intensity control and horizontal subpixel deflection circuit 20 displaces each pixel in the X or horizontal direction by quarter pixel increments according to the magnitude of the two bits of subpixpl X address data received from frame buffer memory 16. Because the raster beam scans the face 24 of CRT 22 at a uniform velocity, subpixel displacement of a given pixel can be controlled in the horizontal direction by varying the time at which the 24 bits of RGB color information are actually applied to the color intensity control of CRT 22. To move a pixel to the left of its normal position, the data corresponding thereto is applied to the CRT 22 somewhat earlier than usual and to move the pixel to the right, the data is applied to the CRT 22 somewhat later than usual.
  • a raster deflection control circuit 26 is coupled to drive CRT 22 with a normal raster scan and is not affected by the X and Y subpixel addressing which is superimposed upon the normal raster scan of the electron beams upon the face 24 of CRT 22.
  • Subpixel displacement of the scanning electron beam in the vertical direction is accomplished by a small horizontal magnetic field.
  • Four pairs of single turn windings are placed beneath the conventional deflection coils of CRT 22.
  • the first winding of each pair (4 parallel single turn windings) is placed on one side of CRT 22 in a coaxially wound relationship between existing deflection yoke and the CRT funnel, while the second winding of each pair is similarly placed on the opposite side of CRT 22.
  • the connection of only two turns in series in each winding results in a very low inductance fast response subpixel deflection system.
  • the arrangement increases sensitivity by enabling the low reluctance magnetic return path of the main vertical deflection system to be used for the subpixel deflection system as well.
  • a world X Y Z coordinate system is used with the origin at the center of the image.
  • An image is stored as a display list in which the image is represented by a list of individual line segments of standard shapes such as straight lines and circular curves. Line segments are defined within a three dimensional Euclidean space with a resolution of + bits on each axis.
  • a display list is transferred from the image generation and storage system 12 to the digital vector generator 14, portions of the list outside the selected display window are clipped or removed and a transformation is made by the digital vector generator system 14 to a display coordinate system.
  • the display coordinate system places the origin at the upper lefthand corner of the display image with the positive X axis extending to the right and the positive Y axis extending downward. This convention conforms to the non-interlaced raster scan which is used to paint the display image on the face 24 of CRT 22.
  • Use of two bits each to define the X and Y subpixel addresses results in 4 discrete subpixel address locations in each dimension for each pixel.
  • the four steps are numbered in binary sequence 00, 01, 10, 11 from top to bottom in the Y direction and left to right in the X direction.
  • the value 10 is assigned to the normal or background subpixel location. This enables a given pixel to be selectively shifted to the right (or upward) by one or two quarter pixel increments or to the left (or downward) by one quarter pixel increment.
  • the subpixel address adjusts the starting time (or left edge) of the pixel. The location is changed by starting the pixel display slightly earlier or slightly later. However, in the Y direction, special subpixel deflection coils must be added and driven with subpixel deflection currents.
  • a vertical subpixel deflection circuit 28 receives the two bits of Y subpixel address information from frame buffer memory 16 through the intensity control and horizontal subpixel deflection circuit 20 and selectively drives the vertical subpixel deflection coils in response thereto.
  • the color map RAM 18, intensity control and horizontal subpixel deflection circuit 20 and vertical subpixel deflection circuit 28 form a display control system 30 which drives the CRT 22 to control the visual characteristics and position of each visual picture element of a displayed video image.
  • the intensity control and horizontal subpixel deflection circuit 20 and the vertical subpixel deflection circuit 32 within the display control system 30 form a video output subsystem 32.
  • the video output subsystem 32 operates to repetitively update CRT 24 with information received from frame buffer 16 and color map RAM 18 to maintain a continuous visual display.
  • the subpixel address may be changed from the normal 2, 2 value as necessary to provide amoother edges and to reduce aliasing.
  • a subpixel address value of 0, 0 would move the displayed pixel location one-half of a pixel distance vertically higher and one-half of a pixel distance horizontally to the left while a subpixel address value of 1, 2 would move the pixel by one-fourth of a pixel distance horizontally to the left without changing the normal vertical displacement.
  • a value of 2, 2 is the normal display position and a value of 3, 3 moves the pixel by one-fourth of a pixel distance horizontally to the right and one-fourth pixel distance vertically downward relative to the normal background display position.
  • X and Y subpixel addresses independently control the horizontal and vertical deflections so that each pixel may be selectively deflected by a selected quarter pixel increment either horizontally or vertically or both.
  • Vector end-points are always located with a (2,2) bcas. Due to the nature of the DVGs, addresses between end points are always (a,2) or (2,m) depending upon which axis is the major axis. The major axis subpixel address is always selected to-be 2.
  • the intensity control and horizontal subpixel deflection circuit 20 is represented in a somewhat simplified form.
  • Frame buffer display architectures are well known and therefore much of the conventional circuitry required to access the frame buffer memory 16 in raster scan order, read out the pixel data, and cause the face 24 of CRT 22 to be illuminated with the pixel data has not been explicitly shown. Only that portion of the deflection circuit 20 which relates to horizontal and vertical subpixel deflection of the normal pixel display position is illustrated in detail.
  • a timing and control circuit 40 generates the master timing and synchronization signals for operation of monitor 41 including CRT 22. These signals include a synchronization signal which is communicated to the deflection control circuit 44 which controls the raster scanning of a beam across the face 24 of CRT 22 in a conventional manner.
  • the deflection control circuit 44 which controls the raster scanning of a beam across the face 24 of CRT 22 in a conventional manner.
  • a set of magnetic deflection coils 46 produce a conventional raster display pattern although alternative deflection means such as electrostatic deflection plates or other display technology could be employed.
  • Timing and control circuit 40 generates a pixel rate clock signal 33 MHz/ which is used to latch color intensity and subpixel address data received from color map RAM 18 and frame buffer memory 16. Timing and control circuit 40 also generates at the 33. MHz pixel clock rate a signal ECLK which is utilized to latch the intensity and subpixel address data after processing in a pipeline type of arrangement. Timing and control circuit 40 also generates at the pixel rate a set of four timing signals TO-T3 at the 33 MHz pixel rate, but having relative phase relationships displaced.at quarter pixel time intervals (7.5 nanoseconds) to control the times at which color intensity data is applied to CRT 22 and hence the exact quarter pixel horizontal position of the corresponding video pixel image.
  • a V latch 48 responds to clock signal 33 MHz/ to latch the 24 bits of three color, video intensity data while an X, Y latch 50 latches the four bits of X and Y subpixel address data and a previous X, Y latch 52 latches the immediately preceding four bits of X, Y subpixel address data.
  • a horizontal control ROM 56 receives the current pixel and previous pixel subpixel address information as address inputs and outputs horizontal displacement control information defining the effective subpixel address commands in response thereto.
  • the Y subpixel information output by horizontal control ROM 56 represents a straight passthrough of the current Y subpixel address information.
  • the X subpixel address information output by horizontal control ROM 56 represents a selected blending of the previous and current X, Y subpixel address offsets so as to achieve a positional averaging effect at line or edge boundary intersections.
  • the horizontal control ROM 56 uses subpixel addresses of adjacent horizontal pixels to set the spatial boundary between the pixels so as to produce an aesthetically pleasing image while retaining the full dynamic visual acuity and resolution of the imaging system.
  • line or boundary pixel edges are treated as dominant and conflicting background pixel edges are moved to conform to the subpixel deflection of line or edge pixels.
  • Tables 2A-2D show the response of the horizontal control ROM 56 to the preceding and current subpixel addresses YlYOXlXO.
  • Xp and Xc are the decimal values of the preceding and current subpixel address bits X1X0.
  • Yp and Yc are the decimal values of YlY0 preceding and current address bits.
  • Tables 2A-2D the rows correspond in top to bottom order to current X subpixel address values of 0-3 decimal respectively while the columns correspond in left to right order to the previous pixel X subpixel address values of 0-3 decimal respectively. Look at the major diagonal of the array shown in Table 2A. It will be noted that where both the current and previous pixels have the same subpixel address, the output address from control ROM 56 is the same as the inputs. Where the previous and current pixels do not have the same subpixel X address, the current pixel effective X address is output approximately as an averaging of the previous and current pixel subpixel X addresses depending on the current and previous YlYO address.
  • the subpixel X addresses define the point at which the left edge of a pixel occurs by defining the time at which the corresponding color intensity data is applied to the CRT display. Once a pixel starts it continues until the occurrence of the next pixel by applying-the color intensity information for the next pixel to the CRT display. There is consequently no gap between adjacent pixels in the horizontal direction. The width of each pixel is inherently varied to fill the allotted display space.
  • ROM 56 (designated XR1, XRO) is decoded by a binary decoder 58 and then latched by EX latch 60 in response to clock signal ECLK.
  • EX latch 60 latches the corresponding 24 bits of video color intensity information
  • EY latch 64 latches the corresponding subpixel Y address information Yl, YO which has been passed through horizontal control ROM 56 unchanged.
  • a multiplexer 66 receives the decoded effective X subpixel address information and the four sequentially phased timing signals TO-T3; and in response to these signals generates a pixel start clock signal which effectively defines the time of occurrence and hence the spatial positioning on the video display of the left edge of.each successive pixel.
  • signal pixel start Upon the occurrence of the signal pixel start, three 8 bit digital-to-analog converters, one for each of the R, G, B color components of the video signal, contained within a circuit designated latching I DACs 68 receive and latch the color intensity signals from EV latch 62. These latched color intensity signals are immediately converted to corresponding analog voltages and applied to the color intensity control inputs of the CRT 22 to immediately command the displaying of the latched video information. Simultaneously, signal pixel start causes a Y deflection latch 70 to receive and latch the Y subpixel address information from EY latch 64.
  • a digital-to-analog converter 71 responds to the digital Yl,Y0 subpixel offset signal output by Y.deflection latch 70 to generate an analog signal on conductor 73 that is indicative of the subpixel displacement.
  • DA converter 71 inherently provides the logic conversion that is required to convert the Y subpixel address signals to deflection current command signals.
  • An amplifier 72 with four output stages responds to the analog deflection signal on conductor 71 and drives a current through the four coil pairs in proportion thereto.
  • a set of low inductance subpixel deflection coils 76 having four single turn coils on each side of CRT 22 is driven by the current outputs of buffer amplifier 72 to selectively deflect the scanning or electron beam vertically upward from the normal raster scan position.
  • the 8 coils generate a uniform horizontal magnetic field across the three electron beams from the PIL gun of CRT 22. This causes equal vertical deflection of the three beams.
  • negative subpixel address values are eliminated by utilizing a subpixel address value of 2 as the normal horizontal background position and a subpixel address value of 2 as the normal vertical background position. This background address value corresponds to a vertical offset of 1/4 upward.
  • the displayed pixel location can be moved vertically upward or downward from this normal background position relative to the +1/4 pixel upward bias position.
  • the response rate of the amplifier 72 and the deflection coils 75 match the response rate of the color intensity controls of CRT 22. Because this response rate is very fast, the single turn coils 76, are utilized to reduce the inductance thereof and enable the response time of the subpixel vertical deflection system to match this very fast response of the intensity control system.
  • the amplifier bandwidth can be trimmed at the time of manufacture to synchronize the subpixel vertical deflection with the intensity control.
  • the digital vector generator system 14 operates in response to vector defining information received from the image generation and storage system 12 to generate multi-bit digital words of pixel data representing video image pixels of vectors defined by the vector defining information.
  • the digital vector generator system 14 includes raster display processor (RDP) 110 having input and output data buses RDPIN 90, and RDPOUT 92 which each carry 16 parallel data conductors along with control conductors and couple to raster board buses RBOUT 15-0 96 and RBIN 15-0 100 respectively, which interconnect the major system components of the image generation and storage system 12.
  • the RDP input data bus 90 is coupled through a buffer 94 . to bus RBOUT 96 while the RDP output bus 92 is coupled through a buffer 98 to bus RBIN 100.
  • a 16K x 16 data memory is included within raster data processor 110 to provide storage of object and vector definition data as well as working operands.
  • a message bus with 16 data conductors and 8 control conductors provides communication between the raster data processor 110 and the image generation and storage system 12.
  • the raster data processor 110 Through the RDP input and output buses 90, 92 and their extensions RBOUT 96, RBIN 100 along with control lines, the raster data processor 110 (see Fig. 3) has communication access to the individual registers and memories of the visual characteristic pixel data generating portion 112 of the digital vector generator 14.
  • the raster data processor 110 receives image defining lists from the image generation and storage system 12 and processes these lists to obtain the data necessary to initialize the pixel data generator 112, which in turn generates the actual pixel data containing the dynamic color and intensity visual characterization for each line vector of a display image.
  • the pixel data generator 112 basically operates between only two end points defining a single line vector at any one time.
  • the raster data processor 108 breaks down complex image segments such as vertex defined, filled or unfilled polygons into line vector representations. Typically each object is represented by a series of boundary vectors defining the peripheral edges of the object and a series of fill vectors which are coincident with raster scan lines and define the interior of an object.
  • the pixel data generator 112 is then utilized to generate the actual pixel data values and their display position addresses for these line vector representations.
  • the pixel data generator portion 112 of the digital vector generator 14 includes a digital vector generator control circuit 114 which generates the specific decoding, timing signals and control signals for clocking and enabling the various registers, memories and other circuit components of the pixel data generator 112 for the purpose of transferring . data from one place to another.
  • a digital vector generator control circuit 114 which generates the specific decoding, timing signals and control signals for clocking and enabling the various registers, memories and other circuit components of the pixel data generator 112 for the purpose of transferring . data from one place to another.
  • the digital vector generator system 14 is coupled to frame buffer memory 16 by a large bandwidth bus called the DVG bus 116.
  • DVG bus 116 A set of 79 principal conductors comprising DVG bus 116 is arranged to carry 34 data signals DVGDAT 33-0, 16 address signals DVGADDR 15-0, 24 chip select signals DVGCS 23-0 and 5 frame buffer memory select signals FBMSEL 4-0. All except the data signals are actually addressing signals.
  • the frame buffer memory select signals permit selection of the color components and two single bit overlay components of frame buffer 16, Z buffer 16a or color map RAM 18.
  • the data signals include 16 bits of Z buffer 16a data DVGDAT 33-18, 2 bits of overlay memory data DVGDAT 17-16, 4 bits of X,Y subpixel address data DVGDAT 15-12, and 12 bits of main frame buffer memory 16 data DVGDAT 11-0.
  • Conventional control and clock signals are also passed along the DVG bus conductors.
  • Raster data processor 110 is coupled to the DVG bus 116 to provide RDP 110 with complete control over the contents of the frame buffer 16, 16a for such functions as initialization and diagnostic analysis.
  • the pixel data generator 112 communicates pixel spatial addresses and visual characteristic information over the DVG bus l16 to frame buffer 16, 16a.
  • Buses RBOUT 96 and RBIN 100 couple RDP 110 to the color map RAM 18 for initialization and diagnostic analysis.
  • the pixel data generator 112 includes six component digital vector generators 118-123 designated respectively D VG X, DVG Y, DVG Z, DVG I, DVG J and DVG K. Spatial address generators X, Y and Z l18-120 generate three dimensional positional address information while visual display characteristic generators I, J, K 121-123 generate three dimensional color and video intensity information.
  • the two sets of . generators form a vector generator subsystem 126 with an X, Y, Z spatial address portion 128 and an I, J, K dynamic color portion 130.
  • the two portions 128, 130 are conceptually similar but have differences in their specific implementations.
  • DVGs I,J and K 121-123 perform three primary functions. During Gouraud shading DVG K 123 interpolates intensity data between two end points Phong shading produces a quadratic interpolation between end points and uses DVGs I,J and K. Texture is generated by slaving the r I and J DVGs to the X,Y and Z DVGs and addressing the pattern RAM with the I and J DVGs.
  • a dynamic intensity processing circuit 150 couples the generated visual characteristic information to the DVG bus 116 with a large number of selectable combinations which afford the system operator an extensive collection of selectable operating modes.
  • a pattern shape multiplexer 152 receives the 13 bits I 6-0, J 5-0 and selectively outputs 12 of the 13 bits to a 4K x 12 pattern RAM 156. The output bits are selected as I 5-0, J 5-0 when signal PATTSHPSEL from a mode control register 258 is 1 and I 6-0, J 5-1 when signal PATTSHPSEL is zero. This enables color selection signals to be balanced between the I and J DVGs 121, 122 or to be weighted in favor of DVG I 121.
  • the selected 12 bits become address bits for the pattern RAM 156. If each work in pattern RAM 156 stores the value of its address then the address input signal is output to a color/intensity mixer 158 unchanged. Alternatively, the address input can be made to recycle with a selected period. If a selected visual pattern is stored in pattern RAM 158 at addresses corresponding to the repeating address pattern, pattern RAM 156 will output the pattern on a repetitive basis to provide a textured surface effect.
  • color/intensity multiplexer 158 which selects either 8 bits, PR 7-0 from normalizing circuit 154 or 12 bits COL 11-0, from pattern RAM 156, and outputs 12 bits, comprising a selected combination onto data conductors DVGDAT 11-0 of DVG bus 116. This permits, for example, a surface to be shaded or covered with a pattern.
  • DVG control circuit 114 includes a DVG pixel counter 148 along with functions such as decoding of register selection and enable signals and generation of control signals required for the operation of the pixel data generator 112.
  • An address translate and interleave circuit 146 receives the X, Y integer pixel addresses from X, Y DVG 118, 119 in X, Y coordinate representations and converts these to a set of linear addresses that are compatible with data memories.
  • DVG X 118 includes a 12 bit X fraction register 134, a 12 bit X accumulator register 136 and a 12 bit X adder/subtractor 138 coupled to receive the output of X accumulator 136 as an A input, the output of X fraction register 134 as a B input, and to output the result thereof to the X accumulator 136.
  • a 12 bit up/down X pixel counter 140 is coupled to be selectively incremented or decremented when its count enable input, GET, is enabled by a carry out output, C12, from adder/subtractor 138 which represents a carry out from the most significant bit when adding, or a borrow when subtracting.
  • the C12 output of adder/subtractor 138 is exclusive OR-ed with the DELXSIGN/ signal to insure that carries are propagated for ADDs and borrows are propagated for subtractions.
  • Counter 140 is coupled to be initialized with data from bus RBIN 11-0 100 under control of signal load X counter LDXCTR/, which is decoded in DVG control circuit 114 from a set of 5 binary RB destination control signals which are generated by RDP 110.
  • a 16 bit tristate X buffer 132 is coupled to place upon the RDP output bus 96 a 16 bit word when its output enable control is activated by a signal to read the X DVG, RDXDVG, which is decoded from the RB control signals.
  • the 16 bit word is comprised of 12 bits from the X counter 140 and the most significant four bits, XACC 11-8; from X accumulator 136 which are placed in the four least significant bit positions by bus RBOUT 96. This coupling is useful for test and diagnostic purposes.
  • the X fraction register can be loaded from the RBIN 11-0 bus 100 under control of a signal load X fraction register, LDXFRAC, which is decoded from the RB destination select signals.
  • the 12 bit adder/subtractor 138 is implemented from 74F382 integrated circuits and has three control inputs S0, Sl and S2 which control the operation thereof. With control input S2 tied to logic 0 the four available functions controlled by Sl, SO are 00-output all zeros, 01-subtract B-A, 10-subtract A-B, and 11-add.
  • the X fraction register 134 and X accumulator register 136 can be initialized with any desired data values under the control of the raster data processor 110. For example, accumulator register 136 be cleared using the all zeros output state of adder/sub-tranctor 138 and then any value can be passed through bus 100 to the X fraction register, added to zero and stored in the accumulator register 136. After initializing the X accumulator 136, any desired value can be loaded into the X fraction register 134 from RBIN bus 100.
  • Pixel counter 140 can be directly set with data from bus RBIN 11-0 100.
  • the binary point is deemed to lie between the most significant bit position of accumulator register 136 and the least significant position of X pixel counter 140.
  • X pixel counter 140 stores integer X address values while X accumulator 136 stores fractional X address values.
  • the two most significant fractional address bits, designated X 1 and Xo are communicated to frame buffer 16 for use in subpixel addressing the individual pixels of the displayed image.
  • a set of logic gates 141-143 receives control signals clear accumulators (CLRACCS/) and load X accumulator (LDXACC/), decoded from the RB control signals; and signals delta X sign, (DELXSIGN), and DVG run (DVGRUN/) to control .
  • CLRACCS/ clear accumulators
  • LDXACC/ load X accumulator
  • DELXSIGN delta X sign,
  • DVGRUN/ DVG run
  • the signals are L (logic 0) for a plus sign (add) and H (logic 1) for a negative sign (subtract).
  • Signal DVGRUN/ is generated by DVG control circuit 114 in response to a control signal STARTDVG that is decoded from signals received from the RDP 110 over bus RBIN 100 and continues until a pixel counter 148 within DVG CTRL circuit 114 indicates that all points of a vector have been generated.
  • signal LDXACC may be asserted to place adder/subtractor 138 in the add mode so that the contents of the previously loaded fraction register 134 can be added to zero and transferred to accumulator register 136.
  • Signal DELXSIGN is a direction signal. When L (positive sign) adder/subtractor 138 is placed in an add mode and counter 140 counts up. When B (negative sign) adder/subtractor 138 is placed in a subtract mode and counter 140 counts down.
  • the Y DVG 119 is identical to X DVG 118 except that it is controlled by Y dimension control signals corresponding to the X dimension control signals.
  • the Z DVG 120 is similar to the X and Y DVGs 118, 119 with some small variations. (See Fig. 5).
  • Z DVG 120 includes a Z fraction register 134A, a Z integer register 134B, a Z 12 bit fraction adder/subtractor 138A, a Z 16 bit integer adder/subtractor 138B, a Z 12 bit fraction accumulator 136A, a Z 16 bit integer accumulator 142 to 144.
  • the operation of a Z DVG 120 is essentially the same as X and Y DVGs 118, 119 except that the arithmetic capability is expanded to 16 integer bits. This increases the resolution in the Z dimension to 16 integer bits and permits stepping by multiple integer distances in the .
  • Z dimension as the digital vector generator system is operated to create video data pixel representations of vectors.
  • Z integer register 134B may be loaded for initialization from bus RBIN under control of decoded control signal LDZINT/ while Z fraction register 134A may be loaded from bus RBIN in response to decoded control signal LDZFRAC/.
  • the DVG Z circuit 120 which is shown in Fig. 5, is not constructed with the overflow adder-counter configuration shown for DVDG X circuit 118 in Fig. 4.
  • DVG Z 120 has been provided with a 12 bit fraction portion and a 16 bit integer portion.
  • the fraction portion includes a Z fraction register 134A, a Z adder/subtractor 138A and Z fraction accumulator 136A.
  • the 16 bit integer portion operates synchronously with the fraction portion to process the more significant bit positions and includes a Z integer register 134B coupled to receive initializing data from bus RBIN 15-0, an integer accumulator 136B and an integer adder/subtractor 138B.
  • the 16 available integer bits can be scaled by a the user in a known manner so as best to represent the range of Z dimension distances for any given application.
  • a roundoff value of 1/8 (binary .001) is then loaded into the fraction register and subsequently added to the fractional starting coordinate value for the initial pixel stored by the accumulator.
  • This 1/8 pixel value creates an offset which automatically rounds the 1/4 pixel resolution represented by the two most significant bits to the nearest 1/4 pixel value. That is, as soon as the accumulated incremental value in the accumulator passes the 1/8 point, the two most significant accumulator bits will indicate a value of 1/4 and continue to indicate 1/4 until the accumulated actual values pass the 3/8 point at which time the two most significant bits will indicate a value of 1/2. Rounding is thus automatically effected to the nearest 1/4 pixel value.
  • the major axis is the X or Y axis to which the vector being displayed is most nearly parallel. This is, the axis to which the angle between the axis and vector is less than or equal to 45°. If the vector lies at exactly 45°, the X axis is treated as the major axis.
  • a delta value of all 1's (I-2 -12 ) is loaded into the corresponding fraction register. If DELSIGN is L (increment accumulator), a carry bit is entered into adder/subtractor 138. If DELSIGN is H (decrement accumulator), a borrow (L) bit is entered into the adder/subtractor 138. This process sets the increment along the major axis to unity.
  • each DVG After the DVGs are stepped to generate a next point, the resultant values are written into the frame buffer 16.
  • the value stored in the fraction register of each DVG is thus added to the corrresponding accumulator 136 for each DVG to enable the correct value for each axis to be indicated at the DVG output as the system steps along a line vector in one pixel increments.
  • the adder/subtractor 138 As the adder/subtractor 138 overflows, the counter 140 is incremented (or decremented) so that for each DVG 118-119 the counter 140 indicates the integer portion of the pixel address and the accumulator 136 indicates the frac- . tional portion.
  • Each DVG 118-123 includes an adder/subtractor 138A, 138B and an accumulator 136A, 136B which extends to the integer portion of the resultant vector coordinate.
  • the dynamic value DVGs I, J, K 121-123 operate in the same general manner as the spatial DVGs 118-120, but have a somewhat more flexible hardware configuration.
  • DVG I, J. and K 121-123 are similar to DVG X, Y and 1 118-120 except that DVG I, J and K 121-123 operate upon three dimensional normal intensity vectors rather than positional vectors.
  • the dynamic value DVGs I, J, K 121-123 develop information which defines the visual manifestation characteristics corresponding to the pixels whose addresses are being concurrently generated by the X, Y Z spatial DVGs 118-120.
  • DVG I 121 shown in Fig. 6 the hardware of the dynamic value DVGs provides more flexibility in the selection of operating modes than the spatial DVGs but the basic principle of operation is essentially the same.
  • a 8 bit I fraction register 134C, an 8 bit I fraction adder/subtractor 138C and an 8 bit I fraction accumulator 136C operate in substantially the same manner as the fraction portion of the X and Y DVGs 118, 119 except that the resolution is decreased from 12 to 8 bits.
  • a delta value stored by fraction register 134C is added to an accumulated value stored by I fraction accumulator 136C.
  • pixel spatial addresses are determined by pixel locations in a predetermined pixel display array and can at most change by a value of one, the visual characteristics depend on subject lighting conditions and can change by values greater than one at each step.
  • DVG I 121 The integer portion of DVG I 121 is thus implemented with an 8 bit I integer register 134 D , an 8 bit I integer adder/subtractor 138D and an 8 bit I mask register and accumulator 136D which performs the corresponding accumulator function of I fraction accumulator 136C.
  • I DVG 121 is thus capable of accommodating non-fractional delta increments.
  • mask register and accumulator 136D enables a selected number of most significant integer bits to be effectively frozen or fixed at a value which can be preset into accumulator 136D while the less significant bits are allowed to accumulate and repetitively overflow as a sequence of pixel definition steps is executed.
  • a mask register within I mask register and accumulator 136D receives and stores a mask control byte from bus RBIN 7-0 100 in response to a decoded register load signal LDSHDMSK 1.
  • Each bit of the mask control byte enables the loading of a corresponding bit position in the accumulator register. By disabling the loading of a given accumulator register bit it is "frozen" and no carries can be passed through to higher order bit positions. All values at the masked bit position and above thus remain constant while lower ordered positions the able to increment and overflow as the integer delta value and carries from the fractional portion are added thereto at each DVG step.
  • This elective bit freezing function is particularly useful in conjunction with DVG I 121 and DVG J 122 when they are coupled through the pattern shape multiplexer 152 to address pattern RAM 156.
  • a pattern stored within a selected number of address locations in pattern RAM 156 can be repetitively outputted every 2 n pixels in each dimension where n is the number of bits which are allowed to vary within the I and J outputs.
  • a corresponding pattern can be stored in pattern RAM 156 which will be repetitively accessed synchronously with the incrementing of DVGs X and Y (118, 119) to produce a repetitive display pattern.
  • the size and repetition rate of the pattern stored in pattern RAM 156 thus may be controlled by the mask control signals or, alternatively, by changing the incremental values stored in the I and J fraction registers 134C, the relative pattern sizes may be controlled while I and J mask registers 136D continue to control the repetition rate.
  • the more significant bits of the accumulator register 136D may be masked and used as page address inputs to pattern RAM 156 to selectione of a plurality of pages, each storing a different texture pattern within pattern RAM 156.
  • An I absolute value circuit 147 receives the 8 most significant bits from accumulator register 136D as well as the signal most significant fractional bit from fraction accumulator 136C. Sign bit 17 is used as a control bit while the seven least significant integer bits and the most significant fractional bit are outputted as an 8 bit unsigned number. When enabled, I absolute value circuit outputs the signals received if the sign bit is positive (zero) and the one's complement of the bits received if the sign bit is negative (one). For the I and J DVGs the absolute value.circuit is permanently enabled.. For K DVG 123, the enable input is controlled by a decoded control signal BACKLITE which selectively enables a backlighting effect. During normal operation either the absolute value of K is selected for backlight, or K is set equal to zero.
  • DVG control circuit 114 includes the DVG pixel counter 148, the mode control register 258, a control decoder 252, a run control flip-flop 254, and a direction control register 256.
  • the RDP, 110 initializes the DVG circuits 118-123 as described above, loads the number of pixel points to be plotted into a pixel counter 148 within DVG control circuit 114 (see Fig. 7) under control of a decoded control signal, LDDVGCTR/, and asserts a start signal.
  • STARTDVG/ which is decoded from the DVG control signals by a destination decoder 252.
  • Signal STARTDVG/ sets DVG run/hold flip-flop 254 which generates at its Q/ output a run signal, DVGRUN/.
  • Signal DVGRUN/ enables operation of each of the DVGs 118-123 as well as a count enable input, CET, of 12 bit DVG pixel counter 250.
  • the digital vector generator system then proceeds automatically to step along a display vector in single pixel increments with respect to the major axis under control of clock signal DVGCLK. After each step a current pixel is written to the frame buffer 16 using the position address and dynamic intensity data developed by the digital vector generators 118-123.
  • DVG pixel counter 148 counts down to zero to activate its RC output which operates to reset the run control flip-flop 254 and terminate the run signal DVGRUN/.
  • the digital vector generator system 14 must then be reinitialized with data for the next vector and signal STARTDVG/ must be reasserted to initiate plotting of the next vector.
  • next vector has a first point coincident with an immediately preceding vector, then the first point will already have been output to the frame buffer 16, and the accumulator registers and counters will contain the initial coordinate values. Only the delta or step values and the DVG pixel counter 250 need be updated to generate the next vector.
  • a direction control register 256 operates in response to signal STARTDVG/ to store 6 direction control signals RBDKSIGN-RBDXSIGN and product signals DELKSIGN-DELXSIGN in response thereto. These signals determine whether the DVG adder/subtractor of each DVG 118-123 operates in an add or a subtract mode. This in turn determines whether for a given dimension, a vector extends in a positive or a negative direction.
  • a mode control register 258 is implemented as an addressable latch having its data input connected to bus signal RBIN 3 and the three address inputs connected to bus signal RBIN 2-0. Mode control latch 258 is enabled by a decoded control signal LDMODREG/ to store a data input signal in any addressable register location. The eight output control signals may thus be set by RDP circuit 108 to any desired state.
  • DVG/VTC decoder 252 receives from bus RBIN 100 six control signals RBDEST 0-2, 4-6 which are in essence register address signals. These signals are decoded so long as the reset signal is not asserted to produce twenty-one active low selection signals as follows: LDXYCNTL, SETBRDFLT, LDCLT, LDMODEREG, LDPATT, STARTDVG, CLRACCS, LDDVGCTR, LDSHDMSK, LDKACC, LDDELK, LDJACC, LDDELJ, LDIACC, LDDELI, LDYCTR, LDYACC, LDYFRAC, LDXCTR, LDXACC, LDXFRAC.
  • a fault flip-flop 262 controls a fault circuit 204 in response to a decoded control signal SETBRDFLT/, to generate a warning signal, BROKE,/, and illuminate an LED 266 when DVG system 14 is not properly operating.
  • the contents of the XDVG integer pixel counter 140 and the X accumulator 136 can be concatenated at any given time to provide the complete X dimension pixel address for any current point (see Fig. 4).
  • the integer portion of the address will be in the counter 140 with the 12 bit fractional address portion being in the X accumulator 136.
  • the carry output, CR, of adder/subtractor 138 becomes active high to increment (decrement) the X counter 140 and indicate a next pixel address location.
  • the fractional value stored in X fraction register 134 continues to be added to (subtracted from) the fractional value stored in X accumulator 136.
  • the integer portions of the X and Y addresses stored in the X or Y counters are communicated to an address translate and interleave circuit 146 (see Fig. 3) while the two most significant fractional bits for each Y and X are output to the frame buffer memory data bus 116 at DVGDAT 15-12.
  • Address translate and interleave circuit 146 (Fig. 3) then converts the integer X and Y values to memory chip addresses for the frame buffer memory 16.
  • dynamic intensity video information derived from the contents of the I, J and K digital vector generators 121-123 is stored in the main portion of the frame buffer memory 16 along with the X and Y subpixel values.
  • the integer and subpixel values of the Z dimension taken from the DVG Z circuit 120 are stored in the Z buffer portion 165a of the buffer memory 16 at the indicated pixel address. If hidden surface processing is activated, then the intensity data is only stored if the Z coordinate value of the pixel is deemed closer to the origin than data previously written into that pixel X, Y location.
  • vector generator circuits 118-123 are incremented. The next sample intensity and subpixel address values are then stored in frame buffer memory 16 at the next pixel address.
  • the raster data processor 110 calculates the number of pixel sample points to be generated and stores this value in the 12 bit DVG pixel counter 148 (Fig. 7). For each occurrence of signal DVGCLK a pixel data point is sampled and stored in the frame buffer memory 16 and the pixel counter 148 is decremented until it reaches a count of 0 at which time an RC output generates a count complete signal which resets run control flip-flop 254 to terminate signal DVGRUN and thus end processing for the current line vector.
  • a dynamic intensity or visual characteristic processing circuit 150 is coupled to receive visual characteristic information from the visual characteristic vector generators I, J, K 121-123 and process this information to generate information defining the visual characteristics at each spatial pixel point along a display vector that is being generated.
  • Processing circuit 150 includes a pattern shape multiplexer 152 coupled to receive seven bits from the DVG I circuit 121 and 6 bits from the DVG J circuit 122, a normalizing circuit 154 coupled to receive six bits each from the DVI 121 and DVG J 122 circuits and eight bits from DVG K 123, a 4K by 12 pattern RAM 156, and color/intensity multiplexer 158.
  • Selected background color patterns such as dashed line patterns or background color windows for insertion of separate data can be generated by initializing frame buffer 16 to a background color before vector generation begins. A pattern of zero's is then written into pattern RAM 156 at pattern locations at which it is desired that the background color be displayed.
  • Zero detect circuit 166 detects this zero value output data and responds by terminating the active state of signal DVG Write Enable, DVGWE. This prevents the background color stored in frame buffer 16 from being overwritten .
  • Normalizing circuit 154 is shown in greater detail in Fig. 8 and operates during Phong shading operations to convert the three normal magnitudes generated by the I, J and K DVGs 121-123 to a single normalized value that is representative of pixel intensity.
  • this mode signal PATTEN from mode control register 258 constrains the pattern shape multiplexer 152 to produce a zero address input to texture RAM 156 to assure a constant color output.
  • normalizing circuit 154 includes a B ROM 190, an A ROM 192 and an adder 194.
  • Adder 194 sums ABSK 7-0 with the AR7-ARO output from A ROM 192 and outputs PR7-PR0.
  • Normalizing circuit 154 responds to the outputs of the I, J and K digital vector generators 121-123 to approximate the magnitude of a Phong shading algorithm while making optimum use of economically available precision by the formula:
  • N is the corrected intensity component parallel to the K axis. N is computed from the interpolated IJK values. The initial term in parentheses is a correction value to be algebraically added to the interpolated value of K.
  • B ROM 190 receives the 6 most significant bits of the absolute value output signals from DVG I 121 and DVG J 122 as address inputs and outputs 1 2 + J 2 in response thereto.
  • This output, BR7-BR2 is limited to a maximum value of 0.999 regardless of the input values in order to maintain a combination of a maximum number of significant digits and simple hardware.
  • a ROM 192 receives as its 6 most significant address inputs 6 data bits D5-0 from B ROM 190 which represent the 6 most significant bits BR7-2 of the B ROM function.
  • a ROM 192 also receives as its 6 least significant address bits the output of an AND gate 191 which receives K intensity signals ABSK7-2 and a single gating signal from mode control register 160, PHONGSHD.
  • a ROM 192 generates the correction term (K I 2 + J 2 + K 2 - K) as output AR7-ARO.
  • Eight bit adder 194 adds the outputs ABSK7-0 and the output of a ROM 192 and as the sum thereof generates output N/, represented by binary signals PR7-PRO.
  • color intensity multiplexer . 158 receives signals COL 11-0 from pattern RAM 156 and signals PR 7-0 from normalizing circuit 154 and selectively combines these signals in one of 6 modes defined by binary counts 0-5 of a mode control signal, MIXMODE 3-0.
  • a buffer 340 receives a selected group of twelve of these signals and outputs them as signals DVGDAT 11-0. Buffer 340 also receives the four X and Y subpixel address signals and outputs them as DVG data signals DVGDAT 15- 12 to the frame buffer 16, 16a.
  • a quad 2:1 multiplexer 350 receives signals COL 11-8 as a B input and signals PR7-4 as an A input. Multiplexer 350 selects one of these inputs as an output in response to a control signal SEL2 and the output signal is connected to buffer 340 to supply bits DVGDAT 11-8.
  • a decoder 352 receives signals MIXMODE 3-0 and generates the color intensity multiplexer 158 control and selection signals in response thereto.
  • Signal SEL2 is decoded to go low and select the PR7-4 A input only during mode 5.
  • Signal DVGDAT 11-8 thus represents COL 11-8 in modes zero to four and PR7-4 in mode 5.
  • Signals DVGDAT 7-4 are generated as the output of one of two tri-state multiplexers 342, 357.
  • Multiplexer 357 is a quad 4:1 multiplexer and multiplexer 342 is a quad 2:1 multiplexer.
  • the output enable input to multiplexer 357 is connected to signal MIXMODE 1 while the output enable input to multiplexer 342 is connected to signal MIXMODE 1/.
  • Multiplexer 342 is thus active during modes 2 and 3 while multiplexer 357 is active during modes 0, 1, 4 and 5.
  • Decoder 352 generates signal SEL0 low during mode 2 to provide signals COL 7, PR7-5 for signals DVGDAT 7-4.
  • signal SELO is generated high to select the B input and couple signals PR7-4 to DVGDAT 7-4.
  • Decoder generates signals SEL 3, 4 to select one of 4 inputs A-D to multiplexer 357 during modes 0, 1, -4 and 5.
  • mode zero input A is selected to couple COL 7-5, PR7 to DVGDAT 7-4.
  • mode 1 input B is selected with signals COL 7-6, PR 7-6.
  • mode 4 input C is selected with signals COL 7-4 and during mode 5 input D is selected to provide signals PR3-0.
  • the four least significant bits DVGDAT 3-0 are coupled to buffer 340 by a quad 2:1 multiplexer 348 having a B input connected to receive signals COL 3-0 and an A input coupled to the output of a 4 bit shifter 344.
  • the SEL B input to multiplexer 348 is decoded to go high to select the B input and signals COL 3-0 during modes 4 and 5. During modes zero to three signal SEL 5 remains low to select the output of shifter 344.
  • Shifter 344 receives as inputs signals PR6-0.
  • the shift control inputs to shifter 344 are responsive to signals MIXMODE 1, 0 to output during mode 0, PR6-3, during mode 1, PRS-2, during mode 2, PR4-1 and during mode 3, PR3-0.
  • a 2910 microcode control unit 270 which is arranged in a conventional manner and includes a 2910 controller and a 4K x 64 microcode memory with conventional decoding.
  • Microcode control 270 provides six mode control signals MODCNTL 5-0 which are used to control several different functional circuits throughout the digital vector generator system 12. The signals are communicated in a manner analogous to a data bus. For example, during execution of a clock generator initialize routine a selected set of clock speed control signals is placed on the MODCNTL lines and loaded into a clock generator control register. In a similar manner an .
  • RDP mode register a box test control register, a shift control register and a multiplier control register can all be sequentially loaded to provide selectable control by RDP 110.
  • Most of these mode control registers are used in a conventional manner and have not been explicitly shown in the drawings.
  • Direction control register 256 (Fig. 7) is an example of such a control register.
  • the three least significant bits MODCNTL 2-0 are used as bit selection addresses to load the ALU 272 (Fig. 10) output sign bit, ALUDAT 15, into a selected bit position of a direction control decode register 255.
  • Each bit position generates an output driving one of the RBDSIGN control signals which are in turn stored by direction control latch 256 (Fig. 7).
  • Microcode control 270 also outputs a set of source select signals, DATAMEMSRCSEL 7-0 and a set of destination select signals DEST 5-0. These signals generate RBSRCSEL 2-0, RBDST 2-0 and RBDESTEN 6-4 which are decoded by control decoder 252 (Fig. 7) to generate the source and destination select signals for the pixel data generator 112. These signals are typically used during a bus transfer to designate the register or memory which is to be enabled to place data onto the bus as well as the destination register or memory which is to be strobed to take data off of the bus. By applying the 6 destination signals in a two step sequence, first to select one of a plurality of decoders and then to supply a code to be decoded by the selected decoder, more than 64 destination select signals can be generated from signals DEST 5-0.
  • control signals include ALU functions select 5-0 (ALUFNSEL 5-0) which control the function performed by an arithmetic logic unit 272, signals ALU source select 27-0 (ALUSRCSEL 27-0) which control the sources of data for A and B ALU data buses 274, 276, signals data memory source select 7-0 (DATAMEMSECSEL 7-0) which define the source of data applied to the input of the A and B portions of data memory 106, and signals data memory control 6-0 (DATAMEMCTRL 6-0) which control the operation of data memory 106.
  • ALU functions select 5-0 ALUFNSEL 5-0
  • ALU source select 27-0 ALUSRCSEL 27-0
  • data memory source select 7-0 data memory source select 7-0
  • data memory control 6-0 DATAMEMCTRL 6-0
  • the RDP 110 main bus structure includes a memory A data bus 278 connected to the input/output port of the A portion of data memory 106 and a MEM B data bus 280 connected to the input/output port of the B portion of data memory 106.
  • a message bus output interface circuit 282 provides an output coupling between the memory B data bus 280 and a message bus which connects digital vector generator system 14 to the image generation and storage system 12.
  • a memory buffer input interface circuit 284 provides an input connection between the message bus and the memory A data bus 278.
  • the message bus includes 15 data lines designated MBD 15-0 and 8 control lines designated MBC 7-0.
  • the A ALU data bus 274 connects through the RDP output data bus 90 to RDP input buffer 94 to provide a connection to bus RB OUT 15-0 96 which services the pixel data portion 112 of digital vector generator 14.
  • the MEM B data bus 280 connects through RDP input data bus 92 to RDP output buffer 98 which provides connection to RB IN 15-0 bus 100 for the pixel data generating portion 112 of digital vector generator system 14.
  • a digital vector generator input/output interface 286, which includes refresh control for the frame buffer memory 16, is coupled to transfer data from a digital vector generator bus DVGBUS 78-0 to the A ALU data bus 274 and to transfer data from the MEM B data bus 280 to DVGBUS 78-0.
  • DVGBUS 78-0 includes a data portion DVGDAT 15-0 which connects to the output of color/intensity mixer 158 as well as to frame buffer memory 16 and an address portion DVGADDR 15-0 which connects to the output of address translate and interleave circuit 146 as well as to frame buffer memory 16.
  • Data for Z buffer 16a, subpixel addressing and two overlay stores within frame buffer 16 are carried by data lines DVGDAT 33-16.
  • An arithmetic logic unit 272 has its A input connected to the A ALU data bus 274, its B input connected to the B ALU data bus 276 and its Y output connected to the MEM B data bus 280.
  • a 16 x 16 multiply circuit 290 has its Y input . and least significant product output connected to the A ALU data bus 274, its X input connected to the B ALU data bus 276 and a most significant product output connected to the MEM A data bus 278. Together, the multiplier 290 and ALU 272 provide the programmed ALU control circuit 108 with a sophisticated, high speed arithmetic capability for rapid manipulation and transfer of vector data.
  • a divide lookup ROM 292 provides a high speed division capability and has its address input connected to MEM A data bus 278 with its outputs connected to the A ALU data bus 274.
  • a 16 bit data register 294 provides a connection between the MEM A data bus 278 and the A ALU data bus 274.
  • a buffer 296 provides a connection from the B ALU data bus 276 to the MEM B data bus 280.
  • a 16 bit register 298 provides a data connection in the opposite direction from the MEM B data bus 280 to the B ALU data bus 272.
  • An immediate data buffer 300 provides a connection for 16 bits of data from the 2910 microcontrol 270 to the B ALU data bus 272 to enable the microcode control 270 to directly place data onto the B ALU data bus 276.
  • a clock generator 302 receives mode control signals MODCNTL 5-0 from the microcode control circuit 270 and in response thereto generates the master system control clock signals, frame buffer memory clock, FBMCLK, digital vector generator clock, DVGCLK, and raster data processor clock RDPCLK.
  • a buffer 304 provides bidirectional communication directly between the MEM A data bus 278 and the MEM B data bus 280.
  • An A address control circuit 306 receives address data from MEM B data bus 280 and in response thereto generates the address signals for addressing the A portion of data memory 106.
  • the B address control circuit 308 receives address information from MEM B data bus 280 and in response thereto provides address signals for accessing the B portion of data memory 106.
  • a message bus DMA circuit 310 is coupled through control signals not explicitly shown to microcode controller 270 and to the address output of A address control circuit 306 to provide for direct memory access data transfers from the message bus to RDP 110 in a conventional . manner.
  • a shift circuit 312 has inputs connected to A ALU bus 274 and B ALU bus 276 and an output connected to the 16 bit MEM B data bus 280. Shift circuit 312 in effect concatenates the 16 bit A ALU bus signals 274 as the most significant word and the 16 bit B ALU bus signals on bus 276 as the least significant word and shifts a selected group of 16 of these signals to the output in response to a 4 bit shift command SHFNUM 3-0 when enabled by an enable shift signal, ENSHIFT/. If SHFNUM 3-0 equal 0, the contents of A ALU bus 274 are shifted through to the memory B data bus 280.
  • Shift circuit 312 thus provides a mechanism for converting independent signals on the A and B ALU buses 274, 276 to a selected group of a concatenated combination thereof.
  • a normalizing circuit 314 facilitates hardware adjustment of the binary point as a means of improving operating speed. It detects the number of leading zero's in a signal on ALU A bus 274 and generates shift control signals SHFNUM 3-0 in response thereto. These shift control signals are communicated to shift circuit 312 and may also be coupled onto MEM A data bus 278.
  • a box test circuit 316 receives the most significant ALU output data bit, ALUDAT 15, which is the output sign bit as well as mode control signals MODCNTL 2-0 and enable signals and operates to determine whether or not a set of values is within a certain range. It is particularly useful in determining very rapidly whether or not a vector is within a selected spatial volume.
  • Example 1 PRIOR ART -- Conventional integer pixel addressing.
  • Line vector 200 shown in Fig. 11 in an X, Y, Z Cartesian coordinate grid representing the face 24 of CRT 22.
  • Line vector 200 has a start point (3.40, 2.75, 1) and an end point of (8.85, 4.22, 1).
  • An integer X value is deemed to define the left boundary of a column of base or background pixel positions while an integer Y value is deemed to define a lower boundary of a row of base or background pixel positions.
  • each pixel is identified by the location of the upper lefthand corner thereof in Fig. 11.
  • RDP 110 first rounds off the start and end points to (3,3,1) and (9,4,1), and then initializes the DVGs as follows. By comparing the differences between rounded-off X and Y coordinates, X is determined to be the major axis because delta X is greater than delta Y. Then the distance 9 - 3 - 6 along the X axis is calculated and stored in pixel counter 148 (see Fig. 7). X counter 140 (see Fig. 4) is initialized at 3, X accumulator 136 is initialized at 0.000 and X fraction register is initialized at 0.999. Since DVGXMAJOR is active, the carry into adder/subtractor 138 is activated, and the X DVG steps in increments of unity.
  • the initial integer number Y pixel value of 3 is stored in the Y counter.
  • the initial integer Z value (1) is stored in the Z integer accumulator 136B
  • the initial fractional Z value (0) is stored in the Z fraction accumulator 136A
  • Table 4 below lists the values that are generated as DVGs X, Y, Z 118-120 are stepped along line vector 200.
  • the fractional values contained in the accumulators are not used in establishing the pixel locations but are included for ease of reference. It can be seen from Table 4, that the value of Y stays at 3, and then jumps to 4 at the end point of the vector. As the counter 250 counts down to zero the operation is complete and the system is ready to reinitialize for generation of the next line vector.
  • Example 2 Subpixel addressing in accordance with the invention.
  • a line vector 202 which is similar to line vector 200 except that it is translated by 10 pixel locations along the X axis.
  • Line vector 202 extends from (13.40, 2.75,1) to (18.85, 4.22,1).
  • these points become (13,50, 2.75,1) and (18.75, 4.25,1).
  • the RDP 110 calculates these initial point pixel values along with the visual characteristic values (shading in this example) and stores them in the DVGs 118-123.
  • the 1/2 component of this value assigns the background subpixel address value of 2 quarters to the end points while the 1/8 component enables the fractional values to be rounded to the nearest quarter pixel by simply truncating the less significant fractional address bits. Assignment of line vector end points to integer pixel locations with 2,2 subpixel address values assures proper matching of mating line segments with no visual discontinuities.
  • the rounded-off end points are determined as:
  • Delta X is clearly the larger value so the X axis is selected as the major spatial axis.
  • pixel counter 148 is set to the major axis (X) delta value of 6.
  • the initial display X location is written iunto DVG X 118 with 13 being written into counter 140 and 0.625 being written into accumulator 136. Since X is the major axis, a delta value of 0.999 is written into the fraction register 134.
  • DVG Z is initialized at 1 with a fraction value of zero which maintains the indicated value constant at one.
  • the K fraction register is initialized with the color intensity slope of -2.0.
  • pixel counter 148 decrements to zero to signal the end of processing for the current line vector. Looking at the vector 202 in Fig. 11, it can be seen that the subpixel addressing representation of vector 202 is much less jagged than the integer pixel addressing representation of corresponding line vector 200.
  • address zero is applied to pattern RAM 156 so that the four most significant bits of color stored at word location zero drive color bits Cll-C8 while the eight absolute value bits from DVG K 123, K7-KO drive frame buffer memory bus DVGDAT 11-4.
  • the resultant effect is a constant hue with a varying intensity.
  • the X and Y quarter pixel values are of course placed on frame buffer memory bus 116 conductors DVGDAT 15-12 as the visual characteristic data for each pixel point is stored.
  • Example 3 A polygon 210 is to be displayed and filled with a pattern as shown in Table 6 in accordance with the invention.
  • the pattern shown in Table 6 begins at display coordinates 0,0 and repeats vertically and horizontally every 8 pixels with 0 representing a selected first color and 1 representing a selected second color different from the first color.
  • the signal PATTSHPSEL will be set to 1 so that pattern shape multiplexer 152 supplies the 12 address inputs to pattern RAM 156 as 15-0, J5-0. Only bits 12-0 and J2-0 are used to control pattern RAM 156. Bits 15-13 and J5-J3 are set and masked in the I and J DVGs 122 and 123. In addressing the pattern RAM, I and J determine the spatial frequency and phase of the data generated by the pattern RAM, 156.
  • texture RAM 156 To allow different patterns to be retained in different locations within texture RAM 156 the current pattern will be stored in texture RAM 156 starting at address 3640 (H E38). This address corresponds to setting the masked bits 15-13 and J5-J3 equal to logic ones.
  • the background color corresponding to "0" in the pattern is written into word locations 3640-42 (H E38-E3A) and 3645-47 (H E3D-E3F) while the foreground color corresponding to "1" in the pattern is written into address word locations 3643-4 (H E3B-E3C).
  • color intensity multiplexer 158 is set to mode 1 so that the 12 bit visual characteristic words stored in the frame buffer 16 are derived as COL 11-6, PR 7-2.
  • X, Y and Z are the spatial coordinates of the vertices of the quadrilateral.
  • I and J define the start and stop locations of data to be selected from the pattern RAM.
  • K is the magnitude of the surface normal intensity component pointing at the observer in a direction parallel to the Z axis.
  • the RDP proceeds as follows. First of all the highest vertex is located. If there are two, the leftmost is selected. Next the RDP executes a software DVG function that picks pair of points with the same ordinate until the next highest vertex is reached. Then the software DVG proceeds to the next lower vertex and finally . to the lowest vertex. For both points of each pair, the X, Y, J, Z, I, J and K values are computed by interpolation.
  • the X DVG, 118 interpolates the pixel data between the points to generate one horizontal fill line.
  • I DVG 121 is stepped synchronously with X DVG to generate the I bits that address the pattern RAM.
  • the quadrilateral is filled with a series of horizontal lines.
  • Visual Attribute data is stored in frame buffer memory 16 as a function of the IJ data supplied to the pattern RAM 156.
  • I DVG, 121 is incremented in tandem with the X DVG, 114, and J DVG, 121 is incremented in tandem with Y DVG 119.
  • Table 8 shows the data interpolated to generate the first line.
  • the individual digital vector generators 119-123 are initialized as shown for step 1 in Table 9.
  • the initial X pixel display location 26.625 is written into X counter 140 and into the X accumulator 136.
  • the X increment value Delta X/(Delta Y)(Y INC.) - 2.0/(-12.0)(-1) - 0.1667 is placed in the fraction register.
  • the (-1) coefficient in this calculation accounts for the Y counter decrementing.
  • DVG Y 119 is initialized by placing the initial integer Y value, 19, in the counter and the fractional value of 0.625 in the accumulator. The -0.999 stepping distance is placed in the fraction register.
  • DVG Z 120 is initialized by placing the initial integer Z value, 4 in the integer accumulator register and the fractional value 0.7 (0.2 plus a roundoff value of 0.500) in the fraction accumulator register.
  • the slope (Delta Z/Delta Y) (Y INC) - (-3.2/-12.0)(-1) - -.2667 is placed in the Z fraction register.
  • the Z output MUX is set to bypass the Z absolute value generator although no negative Z values will be encountered in this particular example.
  • DVG I 121 is initialized by placing the initial I vector value, 66 plus 0.500 roundoff, in the accumulator 174 and the slope Delta I/Delta Y - 50/(-12.0)(-1) - 4.167 in the integer and fraction registers 134D, 134C.
  • the DVG J 121 is initialized by loading the initial value plus a 0.500 roundoff - 125.500 into the accumulator and the slope (Delta J/Delta Y)(INC. Y) - (-37/12.0)(-1) --3.083 into integer and fraction register.
  • the pixel counter 148 is set to an initial value of INT(AABST (Delta Y)) - 12 to count major axis pixel steps.
  • the 6 bit dynamic intensity value normal is generated by normalizing circuit 154 (Figs. 3 and 8) which treats the most significant 6 bit I, J and K output values as fractional values and thus in effect divides them by 64 at the input to the circuit and then multiples the result PR7-0 by 64 at the output.
  • the normal values N/ presented to color/intensity mixer 158 on signals PR7-0 can readily be calculated using the normalization formula described previously at each DVG step.
  • An even more sophisticated graphic representation can be generated by using two or more passes of the vector generator 112 for each vector.
  • Gouraud type shading is employed to generate a desired color or hue pattern using texture RAM 156.
  • the vector generator 112 is operated in a PHONG shading mode and the more sophisticated PHONG generated intensity vector N is substituted in frame buffer memory 16 for the previously generated Gouraud shading value.

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  • Computer Hardware Design (AREA)
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EP85302436A 1984-04-09 1985-04-04 Generierung von graphischen Anzeigen Withdrawn EP0159849A2 (de)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US59838584A 1984-04-09 1984-04-09
US06/600,106 US4808988A (en) 1984-04-13 1984-04-13 Digital vector generator for a graphic display system
US600106 1984-04-13
US598385 1990-10-18

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