EP0183598A3 - Empaquetage à écran pour circuit intégré - Google Patents

Empaquetage à écran pour circuit intégré Download PDF

Info

Publication number
EP0183598A3
EP0183598A3 EP85402171A EP85402171A EP0183598A3 EP 0183598 A3 EP0183598 A3 EP 0183598A3 EP 85402171 A EP85402171 A EP 85402171A EP 85402171 A EP85402171 A EP 85402171A EP 0183598 A3 EP0183598 A3 EP 0183598A3
Authority
EP
European Patent Office
Prior art keywords
lip
integrated circuit
contact pads
plastic substrate
coaxial cable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85402171A
Other languages
German (de)
English (en)
Other versions
EP0183598A2 (fr
Inventor
Sandford Lebow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Augat Inc
Original Assignee
Augat Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Augat Inc filed Critical Augat Inc
Publication of EP0183598A2 publication Critical patent/EP0183598A2/fr
Publication of EP0183598A3 publication Critical patent/EP0183598A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/20—Arrangements for protection of devices protecting against electromagnetic or particle radiation, e.g. light, X-rays, gamma-rays or electrons
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H10W70/685—Shapes or dispositions thereof comprising multiple insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/531—Shapes of wire connectors
    • H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
EP85402171A 1984-11-13 1985-11-12 Empaquetage à écran pour circuit intégré Withdrawn EP0183598A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US67081884A 1984-11-13 1984-11-13
US670818 1984-11-13

Publications (2)

Publication Number Publication Date
EP0183598A2 EP0183598A2 (fr) 1986-06-04
EP0183598A3 true EP0183598A3 (fr) 1987-01-28

Family

ID=24692009

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85402171A Withdrawn EP0183598A3 (fr) 1984-11-13 1985-11-12 Empaquetage à écran pour circuit intégré

Country Status (2)

Country Link
EP (1) EP0183598A3 (fr)
JP (1) JPS61121457A (fr)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2168857A (en) * 1984-11-14 1986-06-25 Int Standard Electric Corp Method and structure for interconnecting high frequency components
EP0391979A1 (fr) * 1988-02-05 1990-10-17 Raychem Limited Ultilisation d'articles conducteurs de l'electricite suivant un axe unique
EP0329314A1 (fr) * 1988-02-05 1989-08-23 Raychem Limited Utilisation d'articles électroconducteurs uni-axiaux
US5631447A (en) * 1988-02-05 1997-05-20 Raychem Limited Uses of uniaxially electrically conductive articles
US5637925A (en) * 1988-02-05 1997-06-10 Raychem Ltd Uses of uniaxially electrically conductive articles
JP2537503Y2 (ja) * 1991-02-07 1997-06-04 三菱重工業株式会社 枚葉印刷機の用紙搬送胴
FR2674680B1 (fr) * 1991-03-26 1993-12-03 Thomson Csf Procede de realisation de connexions coaxiales pour composant electronique, et boitier de composant comportant de telles connexions.
GB2258341B (en) * 1991-07-17 1996-01-17 Lsi Logic Europ Improved bonding wire
EP0547807A3 (en) * 1991-12-16 1993-09-22 General Electric Company Packaged electronic system
US9368440B1 (en) 2013-07-31 2016-06-14 Altera Corporation Embedded coaxial wire and method of manufacture

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4159222A (en) * 1977-01-11 1979-06-26 Pactel Corporation Method of manufacturing high density fine line printed circuitry
EP0122687A2 (fr) * 1983-03-18 1984-10-24 Mitsubishi Denki Kabushiki Kaisha Un dispositif semi-conducteur comprenant un empaquetage pour protéger des parties du dispositif
FR2573272A1 (fr) * 1984-11-14 1986-05-16 Int Standard Electric Corp Procede de realisation d'un substrat comportant un conducteur coaxial

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4159222A (en) * 1977-01-11 1979-06-26 Pactel Corporation Method of manufacturing high density fine line printed circuitry
EP0122687A2 (fr) * 1983-03-18 1984-10-24 Mitsubishi Denki Kabushiki Kaisha Un dispositif semi-conducteur comprenant un empaquetage pour protéger des parties du dispositif
FR2573272A1 (fr) * 1984-11-14 1986-05-16 Int Standard Electric Corp Procede de realisation d'un substrat comportant un conducteur coaxial

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 5, October 1978, pages 1895-1897, New York, US; S. MAGDO: "Low inductance module" *
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 21, no. 6, November 1978, pages 2270,2271, New York, US; J.M. KOLLY et al.: "Laminated PC board system" *

Also Published As

Publication number Publication date
EP0183598A2 (fr) 1986-06-04
JPS61121457A (ja) 1986-06-09

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Inventor name: LEBOW, SANDFORD