EP0190578A2 - Phasendiskriminator für einen Taktgeber - Google Patents

Phasendiskriminator für einen Taktgeber Download PDF

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Publication number
EP0190578A2
EP0190578A2 EP86100558A EP86100558A EP0190578A2 EP 0190578 A2 EP0190578 A2 EP 0190578A2 EP 86100558 A EP86100558 A EP 86100558A EP 86100558 A EP86100558 A EP 86100558A EP 0190578 A2 EP0190578 A2 EP 0190578A2
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EP
European Patent Office
Prior art keywords
signal
phase
transition
clock
state
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86100558A
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English (en)
French (fr)
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EP0190578A3 (en
EP0190578B1 (de
Inventor
Dale B. Chapman
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International Business Machines Corp
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International Business Machines Corp
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Publication of EP0190578A2 publication Critical patent/EP0190578A2/de
Publication of EP0190578A3 publication Critical patent/EP0190578A3/en
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Publication of EP0190578B1 publication Critical patent/EP0190578B1/de
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    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R25/00—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents
    • G01R25/04—Arrangements for measuring phase angle between a voltage and a current or between voltages or currents involving adjustment of a phase shifter to produce a predetermined phase difference, e.g. zero difference

Definitions

  • the present invention relates to a phase discriminator that detects the difference in phase between a pair of clock signals and produces an output for changing the frequency of one of the clock signals to a frequency that reduces the measured phase difference.
  • phase discriminators for detection of the difference in phase between a pair of clock signals typically use circuitry that is sensitive to race conditions when the clock edges used to indicate phase arrive at substantially the same time. Stated differently, in such circuits, the closer in phase the clocks become, the less stable are the circuits.
  • a typical discriminator used to measure the phase difference between a pair of clock signals, C l and C 2 is illustrated in Figure 1 and includes a pair of latches, L and L 2 .
  • Each latch is set by a respective one of the gates G 1 and G 2 .
  • Each gate receives one of the clock signals (through a pulse shaper PS) and the output of the other latch.
  • Either latch is set when the output of its gate is changed by a change in state of the associated input clock.
  • the leading clock will set its associated latch first, causing an error signal E to be produced that indicates the time by which that clock leads the other.
  • the set latch will remain set until reset by the lagging clock. However, if a change in state of the lagging clock is presented to its gate before the lead clock latch is set, the output of the circuit will be indeterminate and can incorrectly reflect the relative phase between the signals.
  • the present invention suppresses the occurrence of race conditions in a clock phase discriminator used to detect phase differences between a of race conditions from the measuring circuitry of the discriminator.
  • the invention uses a latching circuit that measures the relative phase between a pair of input clock signals by following a multi-state transition path in which each state transition results from the change of only one respective state variable.
  • the phase discriminator of the invention measures the difference in phase between an input clock signal of nominal frequency and a variable-frequency reference clock signal. In response to the phase difference measurement, the discriminator produces an error signal for changing the frequency of the reference clock signal in a direction tending to eliminate the phase difference.
  • the discriminator includes a start latch, responsive to a transition of the input clock for producing a start cycle signal and a frequency divider responsive to the start cycle for dividing the reference clock frequency to produce a comparison clock signal having substantially the same frequency as the input clock signal.
  • the latch circuit of the discriminator responds to the start cycle signal, a comparison clock signal transition following the start cycle signal, and an input clock transition following the start cycle signal by measuring the relative phase between the signals by means of a multi-state transition cycle in which each state transition results from the change of a single respective variable, and producing a phase difference signal indicative of the measured phase difference.
  • a gate circuit that responds to the phase difference signal by producing a correction signal to change the frequency of the reference clock signal to a frequency that reduces the phase difference.
  • a still further object of the invention is to provide an improved phase discriminator for measuring the phase difference between a pair of clock signals.
  • the phase discriminator of the invention relates to a novel and improved apparatus for performing phase and frequency synchronization necessary in a data processing system wherein a reference clock signal must be synchronized to a clock signal provided by a servo system.
  • a reference clock signal used to stage data to and from the disk must be synchronized to the servo clock to be sure that the data is written at the correct density on the disk. Without the synchroization of the clocks, the density of the data would vary as the speed of the disk varies.
  • a reference data clock in a magnetic storage access system that uses rotating disks to store data is provided from a phase-locked loop such as is illustrated in Figure 2.
  • the reference data clock is provided by a voltage controlled oscillator (VCO) 10 that produces the reference clock (f VCO ), the frequency of which is determined by the magnitude of a voltage signal provided by a typical charge pump 12 through a low pass filter (LPF) 14.
  • VCO voltage controlled oscillator
  • LPF low pass filter
  • Charge pumps and low pass filters are known in the art, and such devices are taught in U.S. Patent No. 4,034,309, which is assigned to the Assignee of this patent application and is incorporated herein by reference.
  • the charge pump of the incorporated patent consists of two differentially-driven, emitter-coupled transistor pairs.
  • the charge pump drives the low pass filter, which performs an integrating function.
  • One of the charge pump pairs is enabled by a phase difference signal to provide a charge current to the low pass filter, which increases the magnitude of the voltage provided to the VCO, thereby increasing the frequency of the reference clock signal.
  • the other charge pump pair responds to another phase difference signal by drawing current from the low pass filter, thereby reducing the reference clock frequency.
  • the charge pump is fed by a phase discriminator that produces a pair of phase correction signals, one to increase the charge held by the low pass filter (and thus the frequency of f VCO ).
  • the other correction signal is produced by the phase discriminator to decrease the low pass filter voltage magnitude and, with it, the frequency of f VCO .
  • the phase discriminator (D) of the invention indicated by reference numeral 16 in Figure 2, accepts as inputs the reference data clock f vCO and the servo clock f and produces as outputs an increase (INC) phase correction signal and a decrease (DEC) phase correction signal.
  • phase discriminator 16 The operation of the phase discriminator 16 is illustrated by the waveforms of Figure 3.
  • the waveform f/4 represents a clock signal that is derived directly from f VCO in a manner described below. Since f/4 is derived directly from f VCO , it is to be assumed that there is no significant variation in the phase difference between the signals.
  • the phase of f/4 leads that of f S
  • the phase of f S leads that of f/4.
  • the phase detector 16 will produce the DEC signal for a time t that is proportional to the phase difference between f/4 and f s .
  • This causes the charge pump 12 to reduce the charge on the LPF so as to reduce the filter voltage and hence decrease the frequency of the VCO 10.
  • the effect of reducing the frequency of f VCO will be to retard the transitions of f/4 in time, thus moving them towards the transitions of f S .
  • phase discriminator will place the INC signal in a positive condition.
  • the charge pump will direct current into the LPF so as to raise the magnitude of the voltage provided to the VCO 10, which will increase the frequency of f VCO so that the transitions of f/4 will tend to move forward in time to catch up with the transitions of f s .
  • the phase detector 16 will keep the INC signal in a positive condition while holding the DEC signal negative for an amount of time (t 2 ) equal to the phase difference between the edges 22 and 24.
  • phase correction signal initially output by the phase discriminator 16 to the charge pump 12 is effectively neutralized when the other correction signal is also placed in the positive state. This is because the second charge pump circuit is turned on and the increase and decrease frequency currents eliminate each other. This is necessary in order to prevent the occurrence of a deadband region in the response of the phase-locked loop system that would result from the finite time required to switch the charge pump current circuits. After providing both phase correction signals in their positive states for an amount of time, the phase discriminator will simultaneously deactivate them.
  • the phase discriminator 16 is shown in greater detail in Figure 4.
  • the reference data clock signal f VCO oscillates at approximately 48 MHz, while the servo clock f cycles at approximately 12 MHz. Therefore, to rationalize the relationship between f VCO and f S , a frequency divider 30 divides the frequency of f VCO by 4 to produce a comparison clock f/4 whose phase (which has an essentially constant phase relationship to f VCO ) is compared with that of f in the operation of the phase discriminator.
  • the frequency divider 30 can comprise, for example, a conventional ring counter.
  • the phase discriminator of the invention further includes a START latch 32.
  • the inputs to the START latch 32 include an ENABLE signal and the servo clock signal f S .
  • the START latch 32 provides a start cycle signal, shown as G in Figures 4-6.
  • a multi-state latch circuit includes latches 34-42.
  • the latch circuit transitions through a selected one of a plurality of multi-state phase measurement cycles, with cycle selection depending upon the relative phase of the clock signal and the result of the adjustment of f VCO .
  • the latch 34 called the CLOCK latch, searches for transitions of f/4. Transitions in the servo clock f are captured by the SERVO latch 36.
  • the end of a multi-state phase measurement cycle is determined by a CYCLE DONE latch 38.
  • the latches 34 and 36 are prepared for the next phase measurement cycle by a CLOCK CLEAR latch 40 and a SERVO CLEAR latch 42, respectively.
  • the outputs of the latches 34, 36, 38, 40, and 42 are labelled V, W, Z, Y, and X, respectively. These outputs, together with f/4, G, and f S , comprise the state variables that control the transition of the phase discriminator 16 through its phase measurement cycles.
  • the output V of the CLOCK latch 34 is determined by the state variables Y, f/4, G, and Z.
  • the output W of the SERVO latch 36 depends upon the state variables X, G, f S , and Z.
  • the output Z of the CYCLE DONE latch 38 is dependent upon the condition of state variables W and V.
  • the clock clear variable Y provided by the CLOCK CLEAR latch 40 results from the condition of state variables V, f/4, and Z, while the variable X output by the SERVO CLEAR latch 42 is controlled by the state variables f S , W, and Z.
  • the DEC and INC signals are provided by a DEC gate 44 and an INC gate 46.
  • the DEC signal output by the DEC gate 44 depends upon the state variables V and Z that are input to the gate.
  • the INC signal output by the INC gate 46 is determined by the state variables Z and W.
  • phase discriminator of Figure 4 is illustrated by the state transition diagram of Figure 5.
  • Each state of the Figure 5 diagram is determined by a particular combination of the state variables produced by the latch circuit latches 34-42. Transitions between the states are determined by the state of the start latch 32 and transitions of the servo clock f and the comparison clock f/4.
  • Table 1 associates the states of Figure 5 with determining latch states made up of the V, W, X, Y, and Z state variables.
  • phase discriminator latch circuit is in state OA when all of the latches 34-42 are reset.
  • latch circuit is in state OB when all of the latches 34-42 are set.
  • reset state of a state variable is indicated by a bar over the variable, while the set state is indicated by the absence of a bar.
  • phase correction signals output by the phase discriminator of Figure 4 are given by equations (1) and (2).
  • the variable terms of equations (1) and (2) are produced by the action of the latches 34-42.
  • each variahle term of the equations can be considered to be a phase difference signal equivalent to the result of a phase measurement cycle, with the duration of the variable corresponding to the measured phase difference between f/4 and f C .
  • the start latch 32 and the latch circuit latches 34-42 are all initially reset.
  • the ENABLE signal is placed in a high digital state. This may be provided by conventional circuitry when, for example, data is transferred to or from a rotating magnetic disk to which the servo clock f S is synchronized.
  • the START latch 32 will provide a start cycle signal G.
  • the start cycle signal is provided, the frequency 30 will begin operation and the first transition of f/4 will be aligned in phase with the transition of f S that sets the START latch 32. This causes the f/4 and fS to start substantially in phase, which persons skilled in the art will realize speeds up the phase lock process.
  • the phase discriminator will undertake a state transition cycle resulting in the provision of an INC signal to increase the frequency of f VCO and eliminate the phase difference between f/4 and f S . This is accomplished in the following manner.
  • state 4A is automatic because the set conditions for the CYCLE DONE latch 38 exist.
  • state 4A the outputs of the gates 44 and 46 transition substantially simultaneously to a low state. This happens because the state variables V, W, and Z are all in their positive conditions, which prevents any of the terms in equation (1) or equation (2) from being satisfied.
  • the frequency of f VCO will have been adjusted through the action of the charge pump 12, LPF 14 and the VCO 10. This will advance the succeeding transitions of the comparison clock in Figure 3 in time towards the transitions of f s. If the negative transition 24 precedes the negative transition 50 of the servo clock, then the phase discriminator latch circuit will enter state OB by way of state 5A by setting first the CLOCK CLEAR latch 40 and then the SERVO CLEAR latch 42. Alternatively, if the negative transition 24 is after the negative transition 25 in time, the phase detector circuit will enter state OB by way of state 6A. In transitioning through state 6A, first the SERVO CLEAR latch 42 will be set by the negative transition of f and then the CLOCK CLEAR latch 40 will be set by the negative transition 48 of the comparison clock.
  • phase discriminator will be prepared to undertake another phase measurement cycle in response to the first positive transition of either clock following the end of the just-described cycle. This permits the phase discriminator to measure the phase difference of the clocks on each cycle of f S .
  • the comparison clock f/4 (and, therefore, the reference data clock f VCO ) will lead the servo clock f in phase, causing the phase discriminator to provide an error signal for decreasing the frequency of f VCO in an attempt to align the phases of f/4 and f S .
  • the CLOCK latch 34 will be set by the positive transition 18 of f/4 that precedes the positive transition 20 of the servo clock f S .
  • transition cycles proceeding from state OA through state 2A can be constructed from the transition cycles of Table III simply by substituting state 2A for each occurrence of state lA.
  • state OB the response of the latch circuit from state OB back to state OA will be exactly the same as the response from state OA, except that, at the beginning of a transition cycle from state OB, all of the latches 34-42 will be set. Then, a transition cycle will be followed through state 1B (corresponding to state lA) to increase the frequency of f VCO and through state 2B to decrease the frequency of f VCO .
  • the ENABLE signal is removed, which resets the START latch 32 and puts the start cycle signal into a low logic level state G.
  • G will cause the phase discriminator to go from state 0B to state OA by resetting the CLOCK and SERVO latches 34 and 36, which will force the circuit to go to state 4B, and from there, with successive transitions of f/4 and f s , to state OA.
  • the start cycle signal is disabled (G)
  • OA becomes a reset state.
  • CECL cascaded emitter coupled logic
  • FIG. 6 is a schematic representation of a CECL circuit that is functionally equivalent to the CLOCK latch 34.
  • two cascaded sets of emitter coupled transistor pairs 60-66 and 70-76 are used to implement logic internal to the latch that will provide the response to the input state variables required to set and reset the variable V that is output by the latch.
  • each of the positive-sense state voltages V1, V2, and V3 will be at a lower voltage than the corresponding one of the negative-sense output voltages VI, V2, and V3.
  • the set or reset state is determined by diversion of the current from the main current source transistor 80 through successive ones of the emitter coupled switch pairs 60-66, and 70-76, which are connected in such a manner as to allow a number of logical decisions to be made while only expending the dissipation of a single current path.
  • transistor 82 is added to the circuit and its collector is connected to R 2 .
  • This provides a collector loading on the resister R that is substantially equivalent to the collector loading on the resistor R 1 , which makes the time constants at nodes N 1 and N 2 more nearly equal than would otherwise be the case.
  • the same resistor loading equalization is provided in the SERVO latch 36, so that the transition times from state 0B to state 1B and to state 2B are substantially equivalent to the transitions times to states 1A and 2A from OA.
  • trickle current transistors one of which is indicated by 84 in Figure 6.
  • Each of the trickle transistors is biased by a voltage -V b , to keep the emitter coupled transistor pair to which it is connected in a low current-on state so that, when the switch below the pair is switched to provide current, the pair will quickly pass on the current.
  • the current from the trickle current transistors is substantially lower than the current produced by the main current source transistor 59. Without a trickle transistor, the node to which the emitters of a respective pair was attached could float to a voltage near the positive power supply due to minute leakage currents that are commonly found within transistor technologies.
  • phase discriminator of the invention may be practiced in a manner that has not been specifically described.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Manipulation Of Pulses (AREA)
EP19860100558 1985-02-04 1986-01-17 Phasendiskriminator für einen Taktgeber Expired EP0190578B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69811785A 1985-02-04 1985-02-04
US698117 1985-02-04

Publications (3)

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EP0190578A2 true EP0190578A2 (de) 1986-08-13
EP0190578A3 EP0190578A3 (en) 1987-12-23
EP0190578B1 EP0190578B1 (de) 1991-11-27

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EP19860100558 Expired EP0190578B1 (de) 1985-02-04 1986-01-17 Phasendiskriminator für einen Taktgeber

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EP (1) EP0190578B1 (de)
JP (1) JPS61177813A (de)
CA (1) CA1257661A (de)
DE (1) DE3682596D1 (de)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4825572B2 (ja) * 2006-04-17 2011-11-30 住友重機械工業株式会社 トランスファ成形による樹脂封止装置及び樹脂封止方法

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4105947A (en) * 1977-09-16 1978-08-08 Rca Corporation Pulse wave phase and frequency detector
US4291274A (en) * 1978-11-22 1981-09-22 Tokyo Shibaura Denki Kabushiki Kaisha Phase detector circuit using logic gates
JPS57164620A (en) * 1981-04-02 1982-10-09 Sony Corp Phase comparator

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Publication number Publication date
EP0190578A3 (en) 1987-12-23
CA1257661A (en) 1989-07-18
EP0190578B1 (de) 1991-11-27
JPS61177813A (ja) 1986-08-09
DE3682596D1 (de) 1992-01-09

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