EP0201267A3 - Processeur de ligne pour un dispositif d'affichage à mémoire topographique - Google Patents
Processeur de ligne pour un dispositif d'affichage à mémoire topographique Download PDFInfo
- Publication number
- EP0201267A3 EP0201267A3 EP86303243A EP86303243A EP0201267A3 EP 0201267 A3 EP0201267 A3 EP 0201267A3 EP 86303243 A EP86303243 A EP 86303243A EP 86303243 A EP86303243 A EP 86303243A EP 0201267 A3 EP0201267 A3 EP 0201267A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- bit
- row processor
- frame buffer
- processor unit
- scan
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
Links
- 230000006870 function Effects 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/34—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling
- G09G5/346—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators for rolling or scrolling for systems having a bit-mapped display memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/08—Cursor circuits
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
- Digital Computer Display Output (AREA)
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US73000385A | 1985-05-02 | 1985-05-02 | |
| US730003 | 1985-05-02 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| EP0201267A2 EP0201267A2 (fr) | 1986-11-12 |
| EP0201267A3 true EP0201267A3 (fr) | 1990-04-04 |
Family
ID=24933514
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP86303243A Withdrawn EP0201267A3 (fr) | 1985-05-02 | 1986-04-29 | Processeur de ligne pour un dispositif d'affichage à mémoire topographique |
Country Status (2)
| Country | Link |
|---|---|
| EP (1) | EP0201267A3 (fr) |
| JP (1) | JPS61254984A (fr) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1317041C (fr) * | 1987-12-24 | 1993-04-27 | Ncr Corporation | Dispositif creant un curseur au moyen de bandes reliees aux lignes de balayage individuelles |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0058011A2 (fr) * | 1981-01-27 | 1982-08-18 | Syntrex Incorporated | Système de traitement de mots |
| FR2544898A1 (fr) * | 1983-04-25 | 1984-10-26 | Texas Instruments France | Dispositif d'affichage video sur ecran d'affichage par balayage d'une trame ligne par ligne et point par point |
-
1986
- 1986-04-28 JP JP61099305A patent/JPS61254984A/ja active Pending
- 1986-04-29 EP EP86303243A patent/EP0201267A3/fr not_active Withdrawn
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0058011A2 (fr) * | 1981-01-27 | 1982-08-18 | Syntrex Incorporated | Système de traitement de mots |
| FR2544898A1 (fr) * | 1983-04-25 | 1984-10-26 | Texas Instruments France | Dispositif d'affichage video sur ecran d'affichage par balayage d'une trame ligne par ligne et point par point |
Non-Patent Citations (1)
| Title |
|---|
| E.D.N. ELECTRICAL DESIGN NEWS, vol. 29, no. 11, May 1984, pages 153-170, Boston, Massachusetts, US; M.S. YOUNG: "Use a CRT-controller chip to mix text and graphics" * |
Also Published As
| Publication number | Publication date |
|---|---|
| EP0201267A2 (fr) | 1986-11-12 |
| JPS61254984A (ja) | 1986-11-12 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PUAI | Public reference made under article 153(3) epc to a published international application that has entered the european phase |
Free format text: ORIGINAL CODE: 0009012 |
|
| AK | Designated contracting states |
Kind code of ref document: A2 Designated state(s): DE FR GB NL |
|
| PUAL | Search report despatched |
Free format text: ORIGINAL CODE: 0009013 |
|
| AK | Designated contracting states |
Kind code of ref document: A3 Designated state(s): DE FR GB NL |
|
| STAA | Information on the status of an ep patent application or granted ep patent |
Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN |
|
| 18D | Application deemed to be withdrawn |
Effective date: 19900502 |
|
| RIN1 | Information on inventor provided before grant (corrected) |
Inventor name: HUBERT, JOSEPH H. Inventor name: ECKARDT, DONALD J. |