EP0202865A2 - Générateur d'affichage vidéotestable - Google Patents

Générateur d'affichage vidéotestable Download PDF

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Publication number
EP0202865A2
EP0202865A2 EP86303691A EP86303691A EP0202865A2 EP 0202865 A2 EP0202865 A2 EP 0202865A2 EP 86303691 A EP86303691 A EP 86303691A EP 86303691 A EP86303691 A EP 86303691A EP 0202865 A2 EP0202865 A2 EP 0202865A2
Authority
EP
European Patent Office
Prior art keywords
display
memory
monitor
information
logic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP86303691A
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German (de)
English (en)
Other versions
EP0202865B1 (fr
EP0202865A3 (en
Inventor
Kevin P. Staggs
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Honeywell Inc
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Honeywell Inc
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Publication date
Application filed by Honeywell Inc filed Critical Honeywell Inc
Publication of EP0202865A2 publication Critical patent/EP0202865A2/fr
Publication of EP0202865A3 publication Critical patent/EP0202865A3/en
Application granted granted Critical
Publication of EP0202865B1 publication Critical patent/EP0202865B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays

Definitions

  • the loopback register 34 provides the capability for the graphics processor 10 to write various data patterns into the loopback register 34 and read the data back, to accomplish the verificationtiop of the data paths to and from the graphics processor 10.
  • the snapshot register 36 stores an 8-bit output generated by the colour lookup address generator 28 based on a predetermined input, the predetermined input being known information stored in display memories 22 by the graphics processor 10.
  • the 8-bit output stored in snapshot register 36 is checked by the graphics processor 10 to determine if the correct output has been generated, thereby verifying several of the logic blocks within the video display generator 11.
  • the cursor display logic 18 generates a visible cursor which can be positioned anywhere on the display under control of the graphic controller 10.
  • the colour lookup address generation logic 28 determines if the current displayable element is a pixel, alphagraphic, or cursor element (based on the display priority) and uses this determination along with the proper index bits (pixel or alphagraphic) to access a location in the colour lookup memory 16.
  • the colour lookup memory 16, at locations having addresses corresponding to the colour addresses applied by the colour lookup address generator logic 28, has stored colour control signals which are used to control the intensity of the electron beams of the colour guns of a conventional colour CRT monitor (not shown) and which determine the colour and intensity of each picture element of the display array as it is scanned. Eight- bit bytes are stored in the colour lookup memory 16 at locations corresponding to the colour addresses applied.
  • the colour control signal is read out of colour lookup memory 16 and applied to D to A converters 32, which convert 6 of the 8 bits into analog signals for controlling intensity of the red, green, and blue electron beam guns of the conventional CRt monitor.
  • D to A converters 32 which convert 6 of the 8 bits into analog signals for controlling intensity of the red, green, and blue electron beam guns of the conventional CRt monitor.
  • two bits of the colour control signal are applied to a fourth D to A converter which converts these two bits into a monochrome analog signal which can be used to produce a permanent record of the raster display using conventional equipment, as is well known in the art.
  • FIG. 2 shows the organization of the pixel memory 12 and Figure 3 shows the layout of the CRT monitor display.
  • the pixel memory 12 stores characteristic information for each pixel element; namely, planes 0-2 contains colour information, plane 3 contains intensity information, and plane 4 contains blink information.
  • graphic memory 14 There is a similar organization for graphic memory 14.
  • the active display area of the CRT monitor is divided into 640 horizontal elements and 448 vertical elements.
  • the character size is a 5X9 character in an 8X16 character cell (i.e., 8 horizontal pixels by 16 vertical pixels).
  • the pixel memory 12 contains five planes, p0, p1, p2, p3, and p4. Each plane is an 8-bit wide by 64K memory. Each location of each plane contains 8 bits of information relating to 8 corresponding picture elements.
  • the information in display memory 22 corresponds to the position of the sweep of the CRT monitor (not shown).
  • the sweep is a horizontal sweep from let to right, top to bottom, in which the sweep starts at location 0,0 and moves horizontally across the display to location 0,639.
  • the information fetched from display memory 22 for display must correspond to the positioning of the sweep of the CRT monitor.
  • location 0 of display memory 22 is fetched which corresponds to picture elements 0,0 to 0,7
  • location 512 of display memory 22 is fetched which corresponds to the picture elements 0,8 to 0,15
  • location 1024 is fetched, etc., up to location 40448 which corresponds to picture elements 0,632 to 0,639.
  • the next line of the display (picture element 1, 0 to 1, 639) is scanned and the corresponding information is fetched from the display memory 22 at locations 1, 513, 1025, etc.
  • line 447 is completed, the display has been completed and the scanning is restarted at line 0.
  • the alphagraphic memory 14 also corresponds to a display which is 640 horizontal elements and 448 vertical elements.
  • the graphic memory 14 consists of 2 memory planes with each plane organized such that each 8-bit byte corresponds to 8 horizontal elements by 1 vertical element.
  • a dot memory each bit determines if the picture element is a foreground or background colour.
  • the behavior memory each 8 bit location determines the behavior index of an entire associated location in the dot memory, and the display priority between the pixel memory 12 and the alphagraphic memory 14.
  • a behavior index is 6 bits and a display priority is 2 bits.
  • the 6 bits representing the behavior index and the 1 bit identification of each foreground or background colour results in a 7 bit value used as an index into the colour lookup memory 16.
  • the 2 priority bits determine the priority of the pixel display with respect to the alphagraphic display.
  • Figure 4 shows some of the logic of the video display generator 11 utilized for displaying the information stored in the display memories 22.
  • the raster scan logic 20 reads the alphagraphic memory 14 and the pixel memory 12 at the same location; in the example shown in Figure 5, location 0 is being read.
  • the 8 bits from the dot memory 14' are loaded into a shift register 26B and the 8 bits from location 0 of the behavior memory 14" are loaded into a latch 26A.
  • the contents of location 0 of each plane of the pixel memory 12 are loaded into a corresponding shift register.
  • All of the shift registers are shifted such that the colour lookup address generation logic 28 processes the information related to picture element 0,0 from both- the pixel memory 12 and the dot memory 14'. Processing is performed to correspond to the information contained in latch 26A.
  • the sweep of the CRT monitor is at location 0,0 of the display.
  • the display moves to the next position, i.e., picture element 0,1 of the display and likewise the information corresponding to location 0,1 is shifted into the colour lookup address generation logic 28 from the shift registers 30 and the shift register 26B. Again, this information is processed by the colour lookup address generation logic 28 as defined by the information latched in latch 26A, which is valid for the 8 bits of location 0.
  • the process continues until the sweep of the CRT monitor has displayed the 8 picture elements of a horizontal line.
  • the next element to be displayed is location 0,8 which corresponds to address 512.
  • the raster scan logic 20 causes a read of location 512 from the graphic memory 14 and the pixel memory 12 into the shift registers and latch and the above process continues until the entire line is displayed, and then continues as described above until the entire display area has been processed for display.
  • Figure 5 is a partial functional logic block diagram of the raster scan logic 20.
  • the counters shown in Figure 5 are part of the raster scan logic 20 which is verified by the verification apparatus, and include a divide-by-eight circuit 42 for the pixel clock signal, horizontal address counter 44, vertical address counter 46, an odd/even frame counter 48, an end-of-line detector 50, and an end-of-frame detector 52.
  • the outputs of the horizontal address counter 44, vertical address counter 46, and odd/even frame counter 48 are coupled to the display memory 22 for addressing the display memory.
  • the outputs of the horizontal address counter 44, the vertical address counter 46, and the odd/even frame counter 48 make up the display memory address.
  • the output of the odd/even frame counter 48 makes up the least significant bit portion
  • the 8 bits outputted from the vertical address counter 46 makes up the next least significant bits of the memory address
  • the 7 bits outputted from the horizontal address counter make up the most significant bit portion of the display memory address.
  • the pixels are read from the display memory 22 in groups of eight pixels at a time and loaded into shift registers and latches 26, 30 as described above, therefore requiring the pixel clock signal to be divided by eight when clocking the horizontal address counter 44.
  • the horizontal address counter 44 is allowed to continue to count during horizontal retrace, the count being used for generating synchronizing signals.
  • the retrace count for the horizontal address counter 44 is 16 cells, which results in a total count of 768 for each horizontal line.
  • the video display generator 11 is an interlace system, two frames of the display comprising a single complete display. One frame is all of the even horizontal lines of the display and the other frame is all of the odd horizontal lines of the display. During successive vertical scans of the CRT monitor, the frames are alternated as a result of the odd/even frame counter 48.
  • the vertical address counter 46 is similar in operation to the horizontal address counter 44 except that the vertical address counter 46 is only incremented at the end of each horizontal scan line. When the end-of-frame detector 52 senses that the display is at the end of the frame an end-of-frame signal is generated, the vertical address counter 46 is reset to - 16, and the odd/even frame counter 48 is toggled. While the vertical address counter 46 is counting from the count of -16 to 0, the CRT display is blanked and the video display generator 11 is generating the synchronization signals to the CRT monitor.
  • Figure 6 shows the apparatus added to the video display generator 11 to provide the on-line verification function.
  • the end-of-frame signal is utilized as a vertical retrace interrupt signal back to the microprocessor of the graphics processor 10.
  • point 447, 639 the odd frame is completed and the vertical retrace signal is generated (point 446, 639 is the last point for the even frame).
  • location 449 of the display memories 22 which corresponds to the points 449,0 to 449,7 - (for the even frame the location to be addressed and accessed is location 448 which corresponds to points 448,0 to 448,7).
  • locations 448,0-7 and 449,0-7 are in the "hole" area of display memory 22 (i.e., there is no corresponding active display area for these locations), test data is prestored into locations 448 and 449. Since the logic of the video display generator 11 is active, the counters of raster scan 20 are counting during the retrace period, and the locations in the hole area are being accessed.
  • the end-of-frame signal (or vertical retrace interrupt which is active for 8 pixel times, i.e., 8 bits) enables a serial-to- parallel shift register 39 during a portion of the retrace period while location 449 is being addressed (location 448 for the even frame).
  • the address information contained on the data lines from colour lookup address generator 28 corresponds to the 8 bits of address information generated by the counters and shift registers of the logic of video display generator 11 based on the test data stored in location 449 (location 448 for the even frame retrace).
  • An interrupt routine in the graphics processor 10 sets up the loopback register 34 such that a MUX 37 sequentially inputs the generated address information from the colour lookup address generator 28 into the serial-to-parallel shift register 39.
  • the shift register 39 is full the data is read by the graphics processor 10 and compared to an expected result.
  • the test data stored in the display memory 22 is varied by the graphics processor 10 to different patterns to ensure all the logic of the video display generator 11 is adequately tested. Since the colour lookup memory is a RAM, the colour lookup memory 16 can be tested by reading and writing into the RAM.
  • the loopback register 34 is utilized to verify the data paths from the graphics processor 10 to the video display generator 11 and can be done in an off-line as well as an on-line mode.
  • loopback register 34 is set up to select bit 0 of the output of colour lookup address generator 28, and the results stored in the shift register 39 are for the first pixel, bit 0, second pixel, bit 0, etc., to the eighth pixel, bit 0.
  • loopback register is set up by graphic controller 10 to read bit 1, etc., until the eighth retrace when bit 7 for all eight pixels of the test word are read.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)
  • Digital Computer Display Output (AREA)
  • Closed-Circuit Television Systems (AREA)
  • Traffic Control Systems (AREA)
EP86303691A 1985-05-17 1986-05-15 Générateur d'affichage vidéotestable Expired - Lifetime EP0202865B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73524185A 1985-05-17 1985-05-17
US735241 1991-07-24

Publications (3)

Publication Number Publication Date
EP0202865A2 true EP0202865A2 (fr) 1986-11-26
EP0202865A3 EP0202865A3 (en) 1988-09-14
EP0202865B1 EP0202865B1 (fr) 1991-11-06

Family

ID=24954934

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86303691A Expired - Lifetime EP0202865B1 (fr) 1985-05-17 1986-05-15 Générateur d'affichage vidéotestable

Country Status (8)

Country Link
EP (1) EP0202865B1 (fr)
JP (1) JPH0642132B2 (fr)
AU (1) AU579928B2 (fr)
CA (1) CA1254683A (fr)
DE (1) DE3682322D1 (fr)
NO (1) NO169926C (fr)
SG (1) SG2392G (fr)
ZA (1) ZA862964B (fr)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0642085A1 (fr) * 1993-07-22 1995-03-08 Texas Instruments Incorporated Circuit d'échantillonnage
EP0582546B1 (fr) * 1992-08-06 1999-03-24 De La Rue Giori S.A. Dispositif de surveillance des opérations de traitement d'image
GB2337603A (en) * 1998-03-30 1999-11-24 Samsung Electronics Co Ltd Monitor manufacturing apparatus and method

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01149124A (ja) * 1987-12-07 1989-06-12 Yokogawa Electric Corp グラフィックディスプレイ装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA1134050A (fr) * 1978-10-11 1982-10-19 Charles A. Ii Lawson Affichage numerique de controle
US4513318A (en) * 1982-09-30 1985-04-23 Allied Corporation Programmable video test pattern generator for display systems
US4569049A (en) * 1983-05-09 1986-02-04 Digital Equipment Corp. Diagnostic system for a digital computer
DE3468535D1 (en) * 1983-06-30 1988-02-11 Tektronix Inc Diagnostic system for a raster scan type display device
US4663619A (en) * 1985-04-08 1987-05-05 Honeywell Inc. Memory access modes for a video display generator

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0582546B1 (fr) * 1992-08-06 1999-03-24 De La Rue Giori S.A. Dispositif de surveillance des opérations de traitement d'image
EP0642085A1 (fr) * 1993-07-22 1995-03-08 Texas Instruments Incorporated Circuit d'échantillonnage
US5825786A (en) * 1993-07-22 1998-10-20 Texas Instruments Incorporated Undersampling digital testability circuit
GB2337603A (en) * 1998-03-30 1999-11-24 Samsung Electronics Co Ltd Monitor manufacturing apparatus and method
GB2337603B (en) * 1998-03-30 2002-07-17 Samsung Electronics Co Ltd Monitor manufacturing apparatus and method

Also Published As

Publication number Publication date
NO169926C (no) 1992-08-19
DE3682322D1 (de) 1991-12-12
NO861057L (no) 1986-11-18
AU579928B2 (en) 1988-12-15
JPS61267087A (ja) 1986-11-26
EP0202865B1 (fr) 1991-11-06
EP0202865A3 (en) 1988-09-14
NO169926B (no) 1992-05-11
AU5712186A (en) 1986-11-20
JPH0642132B2 (ja) 1994-06-01
CA1254683A (fr) 1989-05-23
ZA862964B (en) 1986-12-30
SG2392G (en) 1992-03-20

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