EP0263374B1 - Reaktives Ionenätzen von tiefen und vertikalen Gräben in Halbleitersubstraten - Google Patents

Reaktives Ionenätzen von tiefen und vertikalen Gräben in Halbleitersubstraten Download PDF

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Publication number
EP0263374B1
EP0263374B1 EP87114029A EP87114029A EP0263374B1 EP 0263374 B1 EP0263374 B1 EP 0263374B1 EP 87114029 A EP87114029 A EP 87114029A EP 87114029 A EP87114029 A EP 87114029A EP 0263374 B1 EP0263374 B1 EP 0263374B1
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EP
European Patent Office
Prior art keywords
etch
trench
sccm
silicon
plasma
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
EP87114029A
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English (en)
French (fr)
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EP0263374A2 (de
EP0263374A3 (en
Inventor
Randy Dean Cos
Arthur Barry Israel
Edward Henry Payne
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International Business Machines Corp
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International Business Machines Corp
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Publication date
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Publication of EP0263374A2 publication Critical patent/EP0263374A2/de
Publication of EP0263374A3 publication Critical patent/EP0263374A3/en
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Publication of EP0263374B1 publication Critical patent/EP0263374B1/de
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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/24—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials
    • H10P50/242—Dry etching; Plasma etching; Reactive-ion etching of semiconductor materials of Group IV materials

Definitions

  • the invention relates to a specific chemistry for effecting deep trenches having substantially vertical sidewalls in semiconductor substrates.
  • the charge plate of the storage capacitor is formed by one or more polysilicon layers and one or more dielectric layers that are coated within a deep (e.g., 5-6 ⁇ m) trench.
  • the sidewalls of these deep trenches must be substantially vertical (i.e., have a slight positive taper x, where 88° ⁇ x ⁇ 90°) in order to (a) minimize the amount of chip space consumed by the trench, and (b) present a topology that can be reliably coated with deposited conductive and insulative films.
  • any etch process that is used to form deep trenches in silicon must provide a maximum “aspect ratio” (i.e., the vertical dimension of the trench should be at a maximum as compared to the horizontal dimension) while minimizing “etch bias” (i.e., the horizontal dimension of the trench should not be appreciably greater than the horizontal dimension of an aperture formed in a masking layer through which the trench is etched).
  • U.S.P. 4,222,792 discloses a process of forming a trench isolation region.
  • the patent lists various techniques of forming a trench in a silicon substrate, namely Cl2/Ar or CCl4/Ar based RIE, fluorine based RIE such as CF4, sputter etching or ion milling.
  • U.S.P. 4,417,947 relates to a process of controlling the slope of apertures formed in silicon by varying the oxygen content of a CCl4/O2 RIE.
  • An anisotropic profile is achieved when there is no oxygen present.
  • U.S.P. 4,450,042 discloses a BCl3/Br2 plasma chemistry for anisotropic etching of silicon and silicon-containing compounds such as silicide.
  • the etch rate increased with increasing He (inert ion bombardment) in the presence of 8% BCl3.
  • the addition of bromine was found to be critical in that it passivated the sidewalls to increase the verticality of the etch.
  • U.S.P. 4,475,982 relates to etching trenches through differentially-doped regions in a silicon substrate. Specifically, a CCl2F2/argon RIE is used to etch lightly-doped regions, and a CCl2F2/oxygen RIE is used to etch more heavily-doped regions.
  • U.S.P. 4,569,718 teaches the use of a BCl3/Cl2 etch chemistry to etch gallium arsenide.
  • US-A-4,613,400 relates to a two-step photoresist capping process which comprises exposing photoresist structures on a polysilicon layer to a chlorinated plasma to form a silicon-chlorine containing material on the photoresist structures and then exposing the resulting structures to an oxidizing plasma containing a chlorine etch species to selectively oxidize the capping layer.
  • the cap deposition involves applying a chlorinated etch gas, such as BCl3 and HCl at a pressure which is relatively high and at a DC bias voltage level which is relatively low compared to the usual pressures and applied for polysilicon etching.
  • the plasma for selectively oxidizing the capping layer involves applying oxygen and HCl to provide the required oxidizing and etching ambient.
  • a carrier gas of He or Ar is used.
  • an Ar/O2 and HCl gas mixture is used with flow rates of 15 SCCM and 100 SCCM respectively.
  • a relatively low pressure and high bias level is used during etching.
  • US-A-4,468,285 relates to a plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide. According to this process oxygen is used as an effective etching selectivity enhancer. When oxygen is added to a plasma etching composition which includes a chlorine containing compound and a shape modifier species the ratio of the amounts of silicon and silicon dioxide removed is at least 10 : 1.
  • the foregoing and other objects of the invention are realized by a chlorine-based trench etch process that provides a maximum aspect ratio at a minimum etch bias.
  • the etch chemistry comprises a combination of oxygen, hydrogen chloride, and boron trichloride. It has been found that the sidewalls of the etched trenches are substantially vertical and the bottoms of the etched trenches are rounded when the trenches are etched in a gaseous plasma reactor using a gas flow of 50 to 125 SCCM hydrogen chloride; 1 to 10 SCCM of a compound comprised of a base atom selected from the group of carbon, boron, and silicon that is linked to halogen atoms other than fluorine; and 10 to 20 SCCM oxygen; a reactor pressure within the range of 6.65 to 26.6 ubar; and a bias of at least -400 volts.
  • the etch process of the present invention is carried out on a p+ type, ⁇ 100> oriented silicon substrate that has a 2.5 ⁇ m thick p-type epitaxial layer disposed thereon.
  • a layer of silicon oxide is formed on the epitaxial layer.
  • the silicon oxide layer could be formed by any one of a number of known techniques (e.g., oxidation of the wafer by exposure to steam or dry O2 at high temperature, chemical vapor deposition, etc). Whichever way the oxide layer is formed, its thickness should be in the region of 300 nm. The reasons for this critical thickness will be explained below.
  • a photosensitive polymer is then applied to the surface of the silicon oxide layer.
  • Any one of a number of known photoresists could be used here.
  • the photoresist is patterned to expose selected areas of the silicon oxide layer and then the exposed portions of the silicon oxide layer are removed to expose underlaying portions of the silicon substrate. It is preferred that dry etch techniques be used to pattern the oxide layer, so as to form apertures therein having vertical profiles. Any etch chemistry (or combination of etch chemistries) that would etch the oxide layer in an anisotropic mode could be used.
  • a two-step etch process is used. In the first step, a CF4 RIE (400V d.c.
  • O2 RIE 800W power, 46.5 bar pressure, 50 SCCM gas flow
  • the thickness of the silicon oxide layer is of primary importance.
  • the trench etch includes a small percentage of oxygen. The oxygen will attack the photoresist above the silicon oxide layer, substantially removing it during the trench etch. Therefore, although the etch rate ratio of silicon oxide to silicon is in the order of 1:50 during the trench etch, the silicon oxide layer must be thick enough so that it is not totally eroded during the trench etch. Therefore, in order to form a 6.5 ⁇ m deep trench, the silicon oxide layer should not be less than 100 nm. In practice, a 300 nm layer is used.
  • BCl3/Cl2 was used to etch trenches in silicon.
  • the trenches produced during this initial phase were characterized by "irregular" side-wall profiles, “dovetail” bottoms, “black silicon,” and nonuniformity across the wafer.
  • the BCl3/Cl2 etch was preceded by a brief (not more than five minutes) BCl3 etch at high pressure (26.6 ⁇ bar) and low power (-200V d.c. bias). This initial etch acts as a chamber conditioner. After etching the oxide layer to expose portions of the substrate, some oxide may form on the silicon surface to be etched.
  • the initial BCl3 etch will remove any oxides from the silicon substrate, while also gettering any contaminants present in the chamber. While this process step is shown separately as the first step in Trial 1, it is to be understood that this same initial BCl3 etch precedes all of the trial etch steps shown in Table 1. That is, this initial etch is used in conjunction with the etch process of the invention. It is omitted from the other etch processes listed in Table 1 purely for the sake of clarity.
  • the sidewalls of the trenches were "irregular" in that they did not have a uniform slope. In general, the slope of the sidewalls varied as a function of depth. The sidewalls should have a constant near-vertical slope that does not vary as a function of depth. At least some of the trenches exhibited a "dovetail" trench bottom, wherein the bottom of the trench had a convex, semi-hemispherical shape.
  • This convex shape is the inverse of the concave, rounded trench bottom that is desired in order to maximize trench filling by eliminating void formation in the filler material. That is, a dovetailed trench bottom would be difficult to reliably cover with layers to be subsequently coated within the trench.
  • Some of the trenches exhibited "black silicon” formation on the trench bottom. "Black silicon” results when a reaction byproduct such as boron oxide is redeposited on the etched surface. These small particles form miniature etch masks in that they will not be removed in the trench etch chemistry. Therefore, silicon regions beneath these particles will not be etched, resulting in a roughened topography. This roughened surface will not reflect incident light, such that the trench bottom will appear to be black when viewed through an optical monitor.
  • the d.c. bias was incrementally raised by increasing the magnitude of the anode-cathode d.c. bias differential, and the gas flows were varied.
  • the d.c. bias was raised above -350V, the trenching problem was reduced and eventually eliminated at -475V.
  • the bowing problem became more severe.
  • This problem was addressed by decreasing the Cl2 flow and increasing the HCl flow.
  • the Cl2 flow was reduced to zero and the HCl flow was increased to 75 SCCM. Surprisingly, it was only when the Cl2 flow was eliminated that the bowing problem was substantially eliminated. The only remaining problem was a residual amount of necking.
  • the etch rate increases by 4% without adversely affecting the etched profiles.
  • the HCl flow is dropped to 50 SCCM, long trench spikes form (i.e., grossly exaggerated black silicon roughening).
  • the HCl flow is increased to 125 SCCM, the sidewalls of the trenches become somewhat bowed.
  • Raising the oxygen flow by 5 SCCM has no apparent effect on trench profiles or etch rate, but it does create black silicon in the large open areas of the pattern. Conversely, a 5 SCCM lower oxygen flow destroys the trench profile, leaving huge silicon spikes.
  • BCl3 was eliminated from the process, no trench was formed. That is, without BCl3, apertures of only 1-2 ⁇ m were formed, having irregular, spiked profiles.
  • the BCl3 flow rate was raised from 6 SCCM to 10 SCCM, dovetailing was introduced at the bottom of the trench.
  • the silicon trench etch has the following attributes. Approximately 100nm-150nm of the silicon oxide layer is removed during the trench etch. Moreover, experiments showed that if a 150nm oxide mask is used, dovetailing is produced at the bottom of the trench. Therefore, it appears that the oxide mask should be at least on the order of 200nm in thickness.
  • the etch bias achieved by the process of the present invention averages roughly less than 0.025 ⁇ m, which is extremely small.
  • the aspect ratio achieved by the process of the present invention is approximately 8:1 to 15:1, typically about 9:1.
  • the present invention provides a trench etch process in which deep trenches are formed in monocrystalline silicon substrates.
  • the trenches are characterized by sidewalls having a substantially vertical slope and rounded trench bottoms.
  • the trench etch exhibits a high aspect ratio and a minimum of etch bias.
  • BCl3 is of particular importance in the etch chemistry of the invention.
  • Other compounds based on a carbon, boron, or silicon base atom linked to a plurality of higher halogen atoms should perform the functions of BCl3 in the etch chemistry of the invention.
  • the term "higher halogens" refer to halogens other than hydrogen or fluorine.
  • a fluorine-containing compound would have a low silicon-to-silicon oxide etch rate ratio, causing substantial mask erosion and discontinuities in the trench profiles.
  • carbon-chloride compounds such as carbon tetrachloride (CCl4) would seem to be of use in the present invention.
  • BCl3 is preferred, in that it posesses optimized oxide etch and impurity gettering properties that are of particular importance to the present invention.

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  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Claims (8)

  1. Verfahren zum Ätzen von Gräben in ein Siliziumsubstrat, wobei die Gräben im wesentlichen vertikale Seitenwände und abgerundete Unterflächen aufweisen, folgende Schritte umfassend:

    Ausbilden einer Maskenschicht auf dem Substrat, um Bereiche des Substrats, in denen Gräben ausgebildet werden sollen, freizulegen, sowie

    Ätzen der Substratbereiche in einem Gasplasmareaktor mit

    einem Gasfluß von 50 bis 125 SCCM Chlorwasserstoff; 1 bis 10 SCCM einer Verbindung eines Basisatoms aus der Gruppe von Kohlenstoff, Bor und Silizium, die mit mit anderen als Fluorhalogenatomen verbunden ist, und 10 bis 20 SCCM Sauerstoff;

    einem Reaktordruck zwischen 6,65 and 26,6 µbar sowie

    einer Spannung von mindestens -400 Volt.
  2. Verfahren nach Anspruch 1, wobei es sich bei der Verbindung um Bortrichlorid handelt.
  3. Verfahren nach Anspruch 1, wobei der Reaktordruck während des Ätzschrittes 13,3 µbar beträgt.
  4. Verfahren nach Anspruch 1, wobei der Reaktor während des Ätzschrittes mit einer Spannung zwischen -450 und -475 Volt beaufschlagt wird.
  5. Verfahren nach Anspruch 1, wobei die Maskenschicht aus Siliziumoxid besteht.
  6. Verfahren zum Ätzen von Gräben nach einem oder mehreren der Ansprüche 1 bis 5, außerdem folgendes umfassend:

    Behandeln der Substratbereiche für eine Zeitdauer von maximal 5 Minuten mit einem ersten Bortrichloridplasma, mit dem restliche Oberflächenoxide entfernt und Verunreinigungen gegettert werden, sowie

    Ätzen der Substratbereiche in einem zweiten Plasma aus Chlorwasserstoff, Borchlorid und Sauerstoff.
  7. Verfahren nach Anspruch 6, wobei das erste Plasma einen Gasfluß von ca. 50 SCCM BCl₃ aufweist und in einem Reaktor mit einer Spannung von -200 Volt und einem Druck von 26,6 µbar erzeugt wird.
  8. Verfahren nach Anspruch 6, wobei das zweite Plasma einen Gasfluß von 100 SCCM HCl, 6 SCCM BCl₃ und 15 SCCM Sauerstoff aufweist und in einem Reaktor mit einer Spannung von -450 Volt und einem Druck von 13,3 µbar erzeugt wird.
EP87114029A 1986-10-09 1987-09-25 Reaktives Ionenätzen von tiefen und vertikalen Gräben in Halbleitersubstraten Expired EP0263374B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US917131 1978-06-19
US06/917,131 US4717448A (en) 1986-10-09 1986-10-09 Reactive ion etch chemistry for providing deep vertical trenches in semiconductor substrates

Publications (3)

Publication Number Publication Date
EP0263374A2 EP0263374A2 (de) 1988-04-13
EP0263374A3 EP0263374A3 (en) 1988-08-03
EP0263374B1 true EP0263374B1 (de) 1991-07-24

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EP87114029A Expired EP0263374B1 (de) 1986-10-09 1987-09-25 Reaktives Ionenätzen von tiefen und vertikalen Gräben in Halbleitersubstraten

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US (1) US4717448A (de)
EP (1) EP0263374B1 (de)
JP (1) JPS63104335A (de)
DE (1) DE3771633D1 (de)

Families Citing this family (27)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5258332A (en) * 1987-08-28 1993-11-02 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices including rounding of corner portions by etching
US4818334A (en) * 1988-03-15 1989-04-04 General Electric Company Method of etching a layer including polysilicon
JPH0265132A (ja) * 1988-08-30 1990-03-05 Sony Corp ドライエッチング方法
DE3915650A1 (de) * 1989-05-12 1990-11-15 Siemens Ag Verfahren zur strukturierung einer auf einem halbleiterschichtaufbau angeordneten schicht
EP0407077A3 (de) * 1989-07-03 1992-12-30 AT&T Corp. Verfahren zur Herstellung einer Halbleiteranordnung mit integrierten Schaltungen
EP0439727A3 (en) * 1990-02-01 1991-10-02 Siemens Aktiengesellschaft Process to make grooves in silicon substrates for high density integrated circuits
US5169487A (en) * 1990-08-27 1992-12-08 Micron Technology, Inc. Anisotropic etch method
US5202754A (en) * 1991-09-13 1993-04-13 International Business Machines Corporation Three-dimensional multichip packages and methods of fabrication
JP3407086B2 (ja) * 1994-06-17 2003-05-19 日本テキサス・インスツルメンツ株式会社 半導体装置の製造方法
US5783101A (en) * 1994-09-16 1998-07-21 Applied Materials, Inc. High etch rate residue free metal etch process with low frequency high power inductive coupled plasma
US5605603A (en) * 1995-03-29 1997-02-25 International Business Machines Corporation Deep trench process
US5637189A (en) * 1996-06-25 1997-06-10 Xerox Corporation Dry etch process control using electrically biased stop junctions
US5865938A (en) * 1996-06-25 1999-02-02 Xerox Corporation Wafer chuck for inducing an electrical bias across wafer heterojunctions
US6051100A (en) * 1997-10-24 2000-04-18 International Business Machines Corporation High conductance plasma containment structure
US5994229A (en) * 1998-01-12 1999-11-30 Taiwan Semiconductor Manufacturing Company Ltd. Achievement of top rounding in shallow trench etch
US6440858B1 (en) 1998-08-24 2002-08-27 International Business Machines Corporation Multi-layer hard mask for deep trench silicon etch
US6221202B1 (en) 1999-04-01 2001-04-24 International Business Machines Corporation Efficient plasma containment structure
US6635335B1 (en) * 1999-06-29 2003-10-21 Micron Technology, Inc. Etching methods and apparatus and substrate assemblies produced therewith
US6291357B1 (en) 1999-10-06 2001-09-18 Applied Materials, Inc. Method and apparatus for etching a substrate with reduced microloading
US6402301B1 (en) 2000-10-27 2002-06-11 Lexmark International, Inc Ink jet printheads and methods therefor
US6921725B2 (en) 2001-06-28 2005-07-26 Micron Technology, Inc. Etching of high aspect ratio structures
US20040224524A1 (en) * 2003-05-09 2004-11-11 Applied Materials, Inc. Maintaining the dimensions of features being etched on a lithographic mask
DE102004034223B3 (de) * 2004-07-15 2006-04-27 Infineon Technologies Ag Verfahren zum Trockenätzen
US7481943B2 (en) * 2005-08-08 2009-01-27 Silverbrook Research Pty Ltd Method suitable for etching hydrophillic trenches in a substrate
DE102005048366A1 (de) * 2005-10-10 2007-04-19 X-Fab Semiconductor Foundries Ag Verfahren zur Herstellung von defektarmen selbstorganisierten nadelartigen Strukturen mit Nano-Dimensionen im Bereich unterhalb der üblichen Lichtwellenlängen mit großem Aspektverhältnis
WO2007042521A2 (de) * 2005-10-10 2007-04-19 X-Fab Semiconductor Foundries Ag Herstellung von selbstorganisierten nadelartigen nano-strukturen und ihre recht umfangreichen anwendungen
US12154784B2 (en) * 2021-12-07 2024-11-26 Taiwan Semiconductor Manufacturing Co., Ltd. Semiconductor devices and methods of manufacture

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4222792A (en) * 1979-09-10 1980-09-16 International Business Machines Corporation Planar deep oxide isolation process utilizing resin glass and E-beam exposure
US4569718A (en) * 1980-08-22 1986-02-11 At&T Bell Laboratories Method for plasma etching III-V semiconductors with a BCl3 -Cl2 gas
DE3275447D1 (en) * 1982-07-03 1987-03-19 Ibm Deutschland Process for the formation of grooves having essentially vertical lateral silicium walls by reactive ion etching
US4450042A (en) * 1982-07-06 1984-05-22 Texas Instruments Incorporated Plasma etch chemistry for anisotropic etching of silicon
US4417947A (en) * 1982-07-16 1983-11-29 Signetics Corporation Edge profile control during patterning of silicon by dry etching with CCl4 -O2 mixtures
US4426246A (en) * 1982-07-26 1984-01-17 Bell Telephone Laboratories, Incorporated Plasma pretreatment with BCl3 to remove passivation formed by fluorine-etch
US4475982A (en) * 1983-12-12 1984-10-09 International Business Machines Corporation Deep trench etching process using CCl2 F2 /Ar and CCl2 F.sub. /O2 RIE
US4468285A (en) * 1983-12-22 1984-08-28 Advanced Micro Devices, Inc. Plasma etch process for single-crystal silicon with improved selectivity to silicon dioxide
US4533430A (en) * 1984-01-04 1985-08-06 Advanced Micro Devices, Inc. Process for forming slots having near vertical sidewalls at their upper extremities
US4561907A (en) * 1984-07-12 1985-12-31 Bruha Raicu Process for forming low sheet resistance polysilicon having anisotropic etch characteristics
US4702795A (en) * 1985-05-03 1987-10-27 Texas Instruments Incorporated Trench etch process
US4613400A (en) * 1985-05-20 1986-09-23 Applied Materials, Inc. In-situ photoresist capping process for plasma etching
JPH0744173B2 (ja) * 1985-10-11 1995-05-15 アプライド マテリアルズ インコ−ポレ−テツド シリサイド、多結晶シリコン及びポリサイドのエッチング方法

Also Published As

Publication number Publication date
EP0263374A2 (de) 1988-04-13
US4717448A (en) 1988-01-05
JPS63104335A (ja) 1988-05-09
DE3771633D1 (de) 1991-08-29
EP0263374A3 (en) 1988-08-03

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