EP0270524A1 - Systemes d'affichage de graphiques - Google Patents

Systemes d'affichage de graphiques

Info

Publication number
EP0270524A1
EP0270524A1 EP85904399A EP85904399A EP0270524A1 EP 0270524 A1 EP0270524 A1 EP 0270524A1 EP 85904399 A EP85904399 A EP 85904399A EP 85904399 A EP85904399 A EP 85904399A EP 0270524 A1 EP0270524 A1 EP 0270524A1
Authority
EP
European Patent Office
Prior art keywords
elements
image
group
successive
columns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP85904399A
Other languages
German (de)
English (en)
Inventor
John Ross
Amedeo Filiberto Sala-Spini
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ran Data Pty Ltd
Original Assignee
Ran Data Pty Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ran Data Pty Ltd filed Critical Ran Data Pty Ltd
Publication of EP0270524A1 publication Critical patent/EP0270524A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/004—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes to give the appearance of moving signs
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources

Definitions

  • THIS INVENTION relates to improvements in graphic display systems.
  • graphic is defined to include sequences of any length made up from letters, words, numbers, idiographs, severally or in combination, symbols and artwork, in colour or in black and white, which can be defined by elements arranged in dot matrix form.
  • Australian Patent Specification 493435 (21004/76) has dis ⁇ closed means whereby high definition graphics may be dis ⁇ played using only a fraction of the picture elements necessary in prior systems.
  • the previous invention capi ⁇ talized on the fact, now established by scientific experi ⁇ ment, that the visual system of man can interpolate in space when visual mechanisms sensitive to motion are stimulated by stroboscopic sequences. Accordingly a viewer- can be caused to see an entire image in motion when only fragments of it are displayed stroboscopically in sequences such as described in Patent Specification 493435 (21004/76).
  • the display system was designed as a stand alone system and was not readily adapted for inclusion as an element in a network.
  • the object of the present invention is to provide a system or method in which some or all of the above limitations are substantially overcome.
  • the invention resides in a display system for depicting a moving image of a graphic of the type herein- defined comprising:-
  • a display means having a display area and an activat ⁇ ing means; said display area being defined by an- array of elements arranged in the form of a matrix having a series of rows and columns, each element forming a cell of the matrix, said rows being arran ⁇ ged parallel to the intended direction of movement of said image and said columns being arranged orthogonal to said intended direction of movement; a first group of elements each having an image source associated therewith, to emit an image element being a portion of said graphic on activation thereof, said first group of elements located in selected rows of said matrix, wherein successive elements of said first group in the same row are spaced apart by one or more columns having blank elements in said same row which do not emit a said image element, and a second group of elements of similar formation to said first group of elements but located in other selected rows of said matrix, wherein said second group of elements are disposed in interlacing fashion relative to said first group such that one element of said second group is disposed intermediate to a pair of successive ⁇ sive elements of said first group in an adjacent row
  • the image sources are arranged in discrete lines within selected columns, orthogonal to the intended direction of movement of said image.
  • the invention resides in a method of depicting a moving image of a graphic of the type herein defined on a display means having a display area being defined by an array of elements arranged in the form of a matrix having a series of rows and columns, each element forming a cell of the matrix, said rows being arranged parallel to the intended direction of movement of said image and said columns being arranged orthongonal to said intended direction of movement; a first group of elements each having an image source associated therewith, to emit a portion of said graphic on activation thereof, said first group of elements located in selected rows of said matrix, wherein successive elements of said first group in the same row are spaced apart by one or more columns having blank elements in said same row which do not emit a said image element, and a second group of elements of similar formation to said first group of elements but located in other selected rows of said matrix, wherein said second group of elements are disposed in interlacing
  • the activating means being associated with each of said image sources to activate an image source in response to the generation of a corresponding electrical signal, the method comprising the steps of generating a set of said electrical signals in sequential groups, each set providing encoded data of a sample portion of said graphic to be represented by one column of said matrix at a pres ⁇ cribed instant, and successive groups of said sets pro ⁇ viding further encoded data of successive sample portions of said graphic to be represented by said one column at successive prescribed instants, the period between successive ⁇ sive prescribed instants being a display state period of said image, said encoded data being sequentially provided to be represented by successive columns of said matrix at said successive prescribed instants, wherein only those rows of image sources within a column of said matrix are activated for which an electrical signal has been genera ⁇ ted
  • the system may include means for storing messages to be displayed, bit maps of characters and graphics used to comprise messages, and means for acquiring messages from remote sources transmitted by telephone lines, radio or other carriers.
  • Fig. 1 is a block diagram of the complete display system
  • Fig. 2 is a block diagram of the preferred forms of activating means for the interlaced arrangement in accordance with the present invention, and the non-interlaced arrangement in accordance with the invention forming the subject of Australian Patent Specification No. 493435 (21004/76);
  • Fig. 3 is a schematic representation of part of the display area showing the relative locations of the image sources
  • Fig. 4 is a schematic diagram of the display area showing the division of the area to facilitate add ⁇ ressing and physical location of the hardware; and Fig. 5 is a timing diagram showing a typical cycle of a display state period.
  • the present embodiment is directed towards a display system, an exemplar version of which is shown at Figure 1 of the drawings.
  • the display system 11 essentially consists of a display means 12 and a controller means 13.
  • the controller means has been developed to a rather sophi ⁇ sticated stage and comprises many features which have now become available as a result of advances in computer technology.
  • the heart of the controller means is a com ⁇ puting means 14 and accompanied therewith an extensive memory means 15, a communication means 16, a timing means 17, an input interface 18, a watch dog circuit 19 and signal conditioning means 20 to interface with the display means.
  • the computing means 14 in the present embodiment is a Z80A CPU with normal clock circuit.
  • the computing means per ⁇ forms most of the control functions of the system and co-ordinates activities between the accompanying circuits and the display means.
  • the memory means 15 is arranged into two distinct sec ⁇ tions.
  • One section 15a provides 6K of RAM and.EEROM which accommodates the operating area used by the operating system and auxiliary message for the computing means.
  • the other section 15b provides an 8K operating system and a massive storage of relevant data to facilitate operation of the display system. This massive storage consists of 48K of memory allocated in blocks of 8K consisting of ROM, RAM or EEROM to suit the individual needs of a user of the system requiring the display of particular graphic infor ⁇ mation.
  • this memory particularly contains bit maps of a reference set of graphic characters in the form of groups of encoded data located within look-up tables. These would be stored in ROM and EEROM or the like.
  • RAM memory may contain a text buffer for the desired graphics which are to be displayed and other operating information.
  • the communication means 16 is in the form of a serial communications controller (SCC) which is provided with two ports to receive communications from different sources.
  • One port 21 is a modem port to receive communications from a remote location and the other port 22 is a local port to receive information from a local keyboard or other input device.
  • SCC serial communications controller
  • the local port operation under either RS232 or RS432 for short or long haul operations.
  • the timing means 17 is in the form of a counter timer circuit (CTC) which provides accurate timing of input/out ⁇ put operations and particularly the cycle of a display state period.
  • CTC counter timer circuit
  • a further adjunct to the timing means of the present embodiment is a real time clock (RTC) 23 which enables the display means 12 to depict the current time if desired and/or effect control of desired functions of the display system with respect to a twenty-four hour clock.
  • the input interface 18 provides basic control of the display system by having a series of input switches 24 connected thereto to invoke basic control of the display means.
  • the watch dog circuit 19 performs a watch dog function by overseeing the operation of the computing means 14 thereby ensuring correct operation of the same, or otherwise applying a resetting pulse to the computing means to reset the same in the event of some malfunction.
  • encoded data is input to the display means via the data bus 25 and signal conditioning means 20 for operation of the display means 12, wherein such encoded data is obtained by using a conventional character gene ⁇ rating technique with the RAM and ROM located in the 48K memory as previously described.
  • the signal conditioning means is provided with a latch 42 and buffer 26 to accom ⁇ modate changes in working voltage levels between the controller means 13 and the display means 12.
  • An important feature of the hardware design of the present system is that all timing is done under interrupt control. That is, the system is partitioned to allow the CTC 17 to perform accurate timing and signal the computing means 14 by way of an interrupt signifying the commencement or completion of a display state period or other such timing requirement. Furthermore, other peripheral devices such as the communication means 16, the RTC 23 and input inter ⁇ face 18 can communicate with the computing means by means of interrupts. However, to ensure that accurate timing is maintained, the CTC 17 is accorded the highest priority interrupt.
  • the display means 12 essentially consists of a display area 27 disposed within an appropriate housing, a series of image sources 28 in the form of LED's and activating means 29, which is associated with the latter.
  • the display area 27 is in the form of a rectangular panel and is divided up into an array of imaginary elements arranged in the form of a matrix having a series of rows and columns wherein each element forms a cell of the matrix.
  • the rows extend in the horizontal direction of the display panel and the columns extend in the vertical direction.
  • the rows are arranged parallel to the intended direction of move ⁇ ment of the image to be displayed on the display area, and the columns are arranged orthogonal to this intended direction of movement.
  • the image sources 28 are located in selected columns of the matrix and in the preferred arrangement are disposed in lines so that any image source located on the display area is disposed within a column having a series of other image sources therein.
  • the image sources 28 are further arranged into two distinct groups. For simplicity of description, reference should be made to Figures 3 and 4 wherein the first group of elements having associated image sources shall hereinafter be referred to as the even group 30 and the second group of elements having associa ⁇ ted image sources shall hereinafter be referred to as the odd group 31.
  • the distinguishing feature between the even and odd groups is that the even groups have image sources located in selected rows which in the present embodiment are the even rows of the matrix.
  • the odd group has image sources located in other selected rows which in fact are the odd rows of the matrix.
  • the characterisation of the present invention is related to the relative positioning of the image sources of the respective even and odd groups of elements. This is achieved by locating the respective groups of image sour ⁇ ces in an interlacing fashion in the matrix. That is, each column of the odd group of elements, except maybe for the last column thereof in the matrix, is interposed between a pair of excessive elements in a common row of the first group and vice versa. For example, column 32 containing an odd group of elements is interposed between columns 33 and 34 of the even group of elements.
  • a cell of the matrix occupied by an image source in one group of elements can partially over ⁇ lap with an immediately adjacent cell in the same column, wherein the adjacent cell is a member of a row containing image sources of the other group of elements.
  • the immediately adjacent cells of an image source are defined by blank elements to facilitate this over ⁇ lapping effect.
  • the present invention relies upon separating and mitigating the density of image sources within a column containing the same by alternating the rows of the column with elements containing an image source and blank ele ⁇ ments.
  • the image sources that would normally have been engrossed within the blank elements of a column of image sources, as described in Australian Patent Speci ⁇ fication No. 493435 (21004/76) are separated out into an additional column positioned mid-way between succeeding columns of a group of elements.
  • This further column would be of similar density of image sources to its adjacent columns but all columns are compensated for this reduced density by the improved spatial effect of the distribution of image sources.
  • the activating means 29 is shown in Figure 2 and is asso ⁇ ciated with each column of image sources 28.
  • the activat ⁇ ing means consists of a storage means 35, an activating circuit means 36 and a further storage means 37.
  • the storage means 35 is in the form of a pair of shift regis ⁇ ters which receive serial data from the controller means 13 and store the same in storage elements within the register for subsequent parallel output of the data.
  • two shift registers of 8 bits each are provided in series to receive two successive 8 bit bytes of encoded data which make up a 16 bit word of encoded data for a column of the matrix.
  • the parallel outputs of the shift registers are connected to the ac ⁇ tivating circuit means 36, which is in the form of a LED driver.
  • the output of the driver is in turn connected to each of the image sources 28 within a particular column. wherein each image source is LED.
  • encoded data is received serially from the controller means by the registers and is stored within storage elements located therein.
  • the registers output the encoded data contained therein in parallel manner to the driver which in turn activates appropriate LED's within a column in accordance with the encoded data.
  • the further storage means 37 is in the form of a further shift register and is serially connected to the storage means 35 and to the next storage means 35' which forms part of the activating circuit for the successive column of image sources of the matrix.
  • the further register is provided with a series of storage elements arranged to accept bytes of encoded data for each of the columns of the matrix disposed between successive columns having image sources. That is, the further register 37 is provi ⁇ ded with bytes of storage each capable of handling 16 bits of encoded data and which are allocated one to each column of blank elements interposed between successive columns of image sources. For example, in one arrangement there may be 6 blank columns between successive columns of image sources, thereby in effect providing storage for 96 bits ' of data.
  • the further storage means 37 is arran ⁇ ged such that data stored therein is shifted in bytes serially through the register so that the last bytes of data therein is serially output in one such shift to the next shift register 35* wherein data is stored serially therein for display at the next display state period.
  • each column of image sources is provided with its own local storage means 35 and activating circuit 36. Furthermore, successive columns of image sources are interconnected by the further storage means 37 which is serially connected between the respective storage means 35 and 35' of the columns.
  • the computing means is a Z80A processor
  • data is stored into bytes of 8 bits. Accord ⁇ ingly the column height is a multiple of 8 elements high.
  • the storage means 35 is divided into two separate 8 bit shift registers (the display is divided into two separate 16 bit sections merely to keep the duty cycle as high as posible). Thus, in one transaction of encoded data, two shifts of 8 bits each are required to make up a 16 bit word of data.
  • the display area is in fact divided into two halves 27a and 27b each having 8 image sources per column therein.
  • the display area is divided into sections 38, wherein each section contains two columns of image sources and the columns of blank elements succeeding the same. It should also be apprecia ⁇ ted that the height of the display, and thus the resolu ⁇ tion may be increased simply by the stacking of more sections 27a and 27b on top of each other.
  • the timing means 17 is arranged to commence the timing of the display state period at timing mark 39. Consequent to this a series of 16 clock pulses is issued whereupon 16 bits of encoded data representing a sample portion of a graphic to be represented by the first column of image sources at the display means are clocked to the display means. Each clocking pulse is used to serially load each bit of data in to the storage means 35 associated with the first column of image sources. Upon completion of the loading procedure, an actuating signal is generated by the computing means 14 at timing mark 40, which consequently outputs the encoded data stored within the storage means 35 to the activating means 36 and thus activates the LED's in the column at this prescribe ⁇ instant.
  • the actuating signal is applied to the storage means of each of the columns having image sources so that the data contained within each of these storage means is simultaneously displayed with the first column.
  • a sequential shift of the displayed informa ⁇ tion is generated at the end of each display state period and during the display state period a static representa ⁇ tion of the graphic is displayed.
  • the image of the graphic character is seen to move across the area, apparently in its complete form.
  • the aforementioned embodiment relates principally to the use of a serial version of displaying encoded data of a graphic. It should be appreciated, however, that the particular mode of transferring data from the controller means to the display means is not an essential ingredient of the present invention and that a parallel version of transferring data is still embraced within the scope of the present invention.
  • a parallel version which can be easily adapted to the present invention is described in Australian Patent Specification No. 493435 (21004/76).
  • the present invention may be adapted to operate bidirectionally, wherein data may be applied to the display means so that the apparent movement of the graphic image may progress selectively in either direction along the display area.
  • the image sources for LED's are of such a size that each element in one matrix overlaps vertically with its nearest neighbours in adjacent rows of the matrix. This vertical overlap has the effect of enhancing beta apparent motion so minimising the tendency of the image to break into momentary fragments and in extending the separation between image elements centered on a line parallel to the direction of movement of the image. Furthermore, the interlacing effect of image sources also makes possible the display of stationary graphics of lower resolution by improving the spatial distribution of- image sources and hence allowing limited resolution of a stationary graphic.
  • the interlacing effect enables up to 20 intermediate columns of blank elements to be provided between successive image sources in any row of the matrix, without severely debilitating the resoluting the resolution of the graphic image displayed.
  • the number of blank columns should number from anywhere between 7 to 14. This is a significant improvement when compared with the number of blank columns that could be provided in the previous invention described in Australian Patent Specification No. 493435 (21004/76).
  • a specific image source may in fact .comprise a number of light sources of different colours to achieve full colour graphics in accordance with the laws of colour mixture.
  • Another feature of the present arrangement is that by adopting a computer system of the type hereindescribed, it is possible to connect the display system into networks via the SCC 18. Accordingly, this may be encrypted and thus accessible only by password so that a particular display system may display a mixture of messages derived from a local source and messages transmitted via a network from a central controller. Furthermore, the overlapping arrangement of image sources in successive rows mitigates the tendency for the image to jitter or wobble in the direction orthogonal to the direc ⁇ tion of movement of the image.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)

Abstract

Système d'affichage de graphiques (11) utilisant le phénomène connu sous le nom de mouvement apparent bêta. Ledit système d'affichage utilise un écran d'affichage (27) comprenant un ensemble d'éléments disposés selon deux matrices similaires, lesquelles s'entrelacent et se chevauchent. Les éléments de chaque matrice sont divisés en éléments vierges et en éléments ayant une source d'image (28) disposée en rangées et en colonnes régulièrement espacées. Les deux matrices se chevauchent partiellement l'une par rapport à l'autre selon une direction orthogonale par rapport à la direction prise par le mouvement d'un graphique devant être affiché par les éléments d'image, de telle sorte que les sources d'image d'une matrice disposée en une série de colonnes, séparées chacune par une série de colonnes d'éléments vierges, chevauchent les rangées adjacentes de l'autre matrice. Afin d'afficher le caractère graphique, des colonnes successives sont activées séquentiellement en affichant une partie du graphique, une image du graphique n'étant affichée que par des colonnes d'échange comportant des sources d'image.
EP85904399A 1985-08-29 1985-08-29 Systemes d'affichage de graphiques Withdrawn EP0270524A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
PCT/AU1985/000205 WO1987001493A1 (fr) 1985-08-29 1985-08-29 Systemes d'affichage de graphiques
ZA856733A ZA856733B (fr) 1985-08-29 1985-09-03

Publications (1)

Publication Number Publication Date
EP0270524A1 true EP0270524A1 (fr) 1988-06-15

Family

ID=25578050

Family Applications (1)

Application Number Title Priority Date Filing Date
EP85904399A Withdrawn EP0270524A1 (fr) 1985-08-29 1985-08-29 Systemes d'affichage de graphiques

Country Status (3)

Country Link
EP (1) EP0270524A1 (fr)
WO (1) WO1987001493A1 (fr)
ZA (1) ZA856733B (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CA2140893A1 (fr) * 1992-07-21 1994-02-03 Amedeo Filiberto Sala Systeme de traitement d'images
KR100293240B1 (ko) * 1998-01-06 2001-09-17 장지호 영상표시장치

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU493435B2 (en) * 1976-01-13 1978-06-15 Roycol Electronics Pty. Limited Improvements in graphic display systems
GB2132400A (en) * 1982-11-18 1984-07-04 Meldisc Investments Pty Ltd Visual display device

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO8701493A1 *

Also Published As

Publication number Publication date
ZA856733B (fr) 1986-03-03
WO1987001493A1 (fr) 1987-03-12

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