EP0286623A2 - Arrangement de circuit pour l'acquisition de signaux chirp-modulés en particulier pour l'acquisition de signaux ultrasonique chirp-modulés - Google Patents

Arrangement de circuit pour l'acquisition de signaux chirp-modulés en particulier pour l'acquisition de signaux ultrasonique chirp-modulés Download PDF

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Publication number
EP0286623A2
EP0286623A2 EP19880890059 EP88890059A EP0286623A2 EP 0286623 A2 EP0286623 A2 EP 0286623A2 EP 19880890059 EP19880890059 EP 19880890059 EP 88890059 A EP88890059 A EP 88890059A EP 0286623 A2 EP0286623 A2 EP 0286623A2
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EP
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Prior art keywords
input
signal
counter
output
frequency
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EP19880890059
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German (de)
English (en)
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EP0286623A3 (fr
Inventor
Alexander Dipl.-Ing. Dr. Metchev
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METCHEV, ALEXANDER, DIPL.-ING. DR.
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B23/00—Generation of oscillations periodically swept over a predetermined frequency range
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01S—RADIO DIRECTION-FINDING; RADIO NAVIGATION; DETERMINING DISTANCE OR VELOCITY BY USE OF RADIO WAVES; LOCATING OR PRESENCE-DETECTING BY USE OF THE REFLECTION OR RERADIATION OF RADIO WAVES; ANALOGOUS ARRANGEMENTS USING OTHER WAVES
    • G01S7/00—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00
    • G01S7/52—Details of systems according to groups G01S13/00, G01S15/00, G01S17/00 of systems according to group G01S15/00
    • G01S7/534—Details of non-pulse systems
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B2200/00—Indexing scheme relating to details of oscillators covered by H03B
    • H03B2200/006—Functional aspects of oscillators
    • H03B2200/0068—Frequency or FM detection

Definitions

  • the invention relates to a circuit arrangement for the detection of chirp-modulated signals, in particular for the detection of chirp-modulated ultrasound signals.
  • the task is to record frequency-variable signals and to evaluate their signal contents or to determine frequency-modulated signals contained in a specific frequency band.
  • this task relates to chirps-modulated signals. These are signals whose frequency changes with time, increasing or decreasing.
  • the present invention has for its object to provide a circuit arrangement by means of which chirp-modulated signals can be correlatively detected and evaluated within frequency bands lying in the acoustic range and in the ultrasound range. No value should be set for the lower limit of the frequency bands, whereas the upper limit of the frequency bands can be between 1 MHz and 10 MHz.
  • phase-sensitive PLL circuits phase-locked loops
  • the term “snap-in” is understood to mean the synchronization of the frequency and the phase of the signal emitted by the PLL circuit with the frequency and the phase of the received signal, which enables further processing of the received signal by the PLL circuit.
  • Known circuit arrangements which serve to find certain signals in predetermined frequency ranges contain a large number of filter banks, by means of which signal analyzes can be carried out.
  • the invention is therefore based on the object of providing a circuit arrangement which, using digital technology, enables rapid and accurate detection of signals, in particular transient, frequency-variable signals.
  • This object is achieved according to the invention by the combination of a digital frequency discriminator with a sequential pulse detector, associated threshold value circuits, a priority decoder and a signal display and / or a memory, by means of which combination a chirp-modulated signal is determined in a predetermined frequency range and evaluated correlatively.
  • the digital frequency discriminator preferably contains a flip-flop, a scan generator, at least two counters, a decoding circuit and also a phase detector, a control switch and a low-pass filter, the latter components with the counters being a PLL circuit for regulating the frequency of the scan generator on the basis of a reference signal form.
  • a bandpass filter can be assigned to the input of the flip-flop, the center frequency of which can be set by a frequency-voltage converter or a frequency-current converter, which can be controlled by the sampling generator.
  • the output of the bandpass filter is preferably connected to a voltage comparator, the output of which is led via an AND gate and an OR gate to the set input of the flip-flop.
  • the outputs of a first counter can be connected to the inputs of a coding switch, by means of which the length of the counting process in the first counter can be set.
  • the outputs of a second counter can be connected to the inputs of a buffer, which is used to store the current measured values and whose outputs are connected to the decoding circuit.
  • the outputs of the decoding circuit can be connected to the sequential pulse detector.
  • Two further counters are preferably provided for controlling the sequential pulse detector, a monoflop for controlling an intermediate store and another monoflop for controlling the threshold value circuits.
  • the sequential pulse detector can be formed by a chain of shift registers, between which OR gates are arranged, and the threshold circuits can be formed by a group of counting circuits, in which AND gates, OR gates and counters are arranged.
  • each output of the decoding circuit is preferably connected, on the one hand, to an input of the associated OR gate located between two shift registers and, on the other hand, to an input of the assigned threshold value circuit, the output of the assigned shift register being led to a second input of the threshold value circuit.
  • the outputs of a part of the memory elements located in the shift registers are led out and connected to inputs of tri-state buffer circuits and the outputs of one of the tri-state buffer circuits are connected to one input of a comparator via resistors, a voltage divider is connected to its other input and its output is connected to a feedback input of this tri-state buffer circuit.
  • a first signal input 1 of the circuit according to FIG. 1 is applied to a bandpass filter 6, the output of which is led to a voltage comparator 7.
  • the bandpass filter 6 determines the frequency range in which signals are to be sought.
  • the incoming sinusoidal signal is converted into a square wave signal by the voltage comparator 7.
  • the output of the voltage comparator 7 is connected via an AND gate 11 and an OR gate 12 to the set input 101 of a reset set flip-flop 10 (RS flip-flop) and via an inverter 13 to the one input of an AND Gate 14 placed.
  • the Q output 103 of the RS flip-flop 10 is via the other input of the AND gate 14 to the reset input 301 of a second counter 30 and further to the one input 25 of a phase detector 24, the other input 26 of a second Signal input 2 forth can be acted upon with a reference signal.
  • the general partner Q -Output 104 of the RS flip-flop 10 is also at the reset input 201 of a first counter 20, further to an input of an AND gate 15, the output of which is led to the counting or clock input 302 of the second counter 30 to reset inputs 401 and 501 of a third counter 40 and a fourth counter 50 and to the input of a first monoflop 29.
  • the output of the phase detector 24 is connected to the input 28 of an electronically controllable switch 27, which can be acted upon by a third signal input 3 for reference control with a rectangular signal via its control input 28a.
  • the output of the switch 27 is connected to the input of a low-pass filter 35, the output of which is connected to the control input 37 of a voltage-controlled oscillator 36 (VCO), which serves as a clock and sampling signal generator.
  • VCO voltage-controlled oscillator
  • the output of the oscillator 36 is connected to the counter or clock input 202 of the first counter 20, to a second input of the AND gate 15, to the counter or clock input 402 of the third counter 40 and to the input of as a control circuit for the Low-pass filter 6 serving frequency-voltage converter 8 placed.
  • the output of the first monoflop 29 is connected to the input of a second monoflop 31, to the control input 46 of a buffer memory 45, to the control input 63 of a decoder 60 and to the control input 102 of a result memory 100.
  • the second counter 30 is formed with a multiplicity of outputs 304 lying in parallel, all of which are led to further inputs 47 of the intermediate store 45. At least one middle output of the second counter 30 is led to an input of a further AND gate 16, the output of which is connected to a second input of the OR gate 12.
  • the control input 3 for the reference control is also connected to an input of the AND gate 16 and via an inverter 19 to a further input of the AND gate 11.
  • Another output 303 of the second counter 30 is connected to a third input of the AND gate 15 via an inverter 18.
  • the outputs 203 of the first counter 20 are connected to a coding switch 21 with a large number of adjustable contacts 22.
  • the first counter 20 can be preprogrammed to a specific counter content by the coding switch 21.
  • the outputs of the coding switch 21 are connected to the reset input 102 of the flip-flop 10 via an AND gate 23.
  • the individual outputs 48 of the buffer store 45 are led to assigned inputs 61 of the decoder 60, the N + 1 outputs 62 of which are connected to first inputs 76 of OR gates 75 assigned to these outputs 62.
  • the OR gates 75 are each located between two shift registers 70 and form a chain with them.
  • the outputs 73 of the shift register 70 are connected to second inputs 77 of the OR gate 75.
  • the outputs 78 of the OR gates 75 are led to the respective inputs 71 of the shift register 70 following in the chain.
  • the outputs 62 of the decoder 60 and the outputs 73 of the shift register 70 are connected to assigned counter circuits 80.
  • the outputs 85 of the individual counter circuits 80 are connected to inputs 91 of a priority decoder 90 assigned to the individual counter circuits 80.
  • the outputs 92 of the priority decoder 90 are led to the inputs 101 of the result memory 100.
  • the output 403 of the third counter 40 is at the counter input 502 of the fourth counter 50 and at Steuer proceedings. Take inputs 72 of shift register 70 are placed.
  • the output 503 of the fourth counter 50 is connected to control inputs 83 of the counter circuits 80.
  • the individual shift registers 70 contain a multiplicity of memory cells.
  • the number of memory cells provided in the individual shift registers 70 must be equal to the number N of shift registers 70.
  • 16 shift registers 70 are provided, each shift register 70 containing exactly 16 memory cells.
  • the outputs 73 of the shift register 70 are connected to first inputs 81 of the assigned counter circuits 80 and the outputs 62 of the decoder 60 are connected to second inputs 82 of the assigned counter circuits 80.
  • the output 503 of the fourth counter 50 is connected to control inputs 83 of the counter circuits 80 and the output of the second monoflop 31 is connected to reset inputs 84.
  • the counter circuits 80 contain an OR gate 801, the output of which is connected to a first input of an AND gate 802.
  • the input 81 is present at a second input of this AND gate 802.
  • the output of this AND gate 802 is led to the counter input of a counter 803.
  • the outputs 00, 01, 02 of the counter 803 are connected to the inputs of the OR gate 801 and to the inputs of a further AND gate 804.
  • the input 82 is connected to one of the inputs of the AND gate 804.
  • the output of the AND gate 804, which forms the output 85 of the counter circuit 80 is connected to the input 91 of the priority decoder 90 assigned to this counter circuit.
  • the outputs 92 of the priority decoder 90 are connected on the one hand to the inputs 101 of the result memory 100 and on the other hand to the inputs 111 of an AND gate 110.
  • the clock scanning signals generated by the oscillator 36 arrive at the input 202 of the first counter 20 and are counted therein. Although these clock scanning signals are also output to the AND gate 15, they remain ineffective with this, since at its second input the low signal from Q - Output 104 of the flip-flop 10 is present.
  • the clock scanning signals are further counted in the third counter 40. As soon as the counter 40 has counted completely or is full, it outputs an output signal to the input 502 of the fourth counter 50, which is counted by this counter 50. Accordingly, the third counter 40 and the fourth counter 50 effect pulse controls in predetermined ratios.
  • the counting of the clock scanning signals in the first counter 20 is initiated by the positive edge of the square-wave signal on the basis of a signal occurring at the first signal input 1.
  • the reset input 102 of the flip-flop 10 is switched on via the coding switch 21 and the AND gate 23 Issued signal by which the flip-flop 10 is reset, so that at its Q output 103 a low signal and at its Q -Output 104 a high signal occurs.
  • the first counter 20 as well as the third counter 40 and the fourth counter 50 are reset to zero. Since this also results in a high signal at the AND gate 15, the clock sampling pulses arrive from the oscillator 36 at the counter input 302 of the second counter 30, whereby the latter begins to count.
  • the counting in the second counter 30 continues until the next positive edge, ie the next edge of the rectangle signals, due to a signal from the first signal input 1. With this positive edge, the first counter 20 begins to count again and the counting in the second counter 30 is interrupted.
  • the result of the previous count is briefly stored in that the outputs 304 of the second counter 30, each of which represents a specific counter reading, are connected to the assigned inputs 47 of the buffer store 45.
  • the duration of the storage of the output signals of the second counter 30 in the buffer 45 is determined by the output signal of the monoflop 29, which has a short duration.
  • the monoflop 29, which on the falling edge of the signal on Q Output 104 of the RS flip-flop 10 is triggered, thus causing the output signals of the second counter 30 to be stored in the intermediate memory 45.
  • the state of the intermediate memory 45 is retained until the next storage.
  • the counter content of the second counter 30 is cleared during the following counting process by the trailing edge of the square-wave signal output by the voltage comparator 7.
  • the second counter 30 As soon as a signal occurs at the first signal input 1, its period is determined by counting the sampling pulses emitted by the oscillator 36 first by the first counter 20 and then by the second counter 30. If the input signal has a length close to the lower limit of the measuring range, the counter result of the second counter 30 causes only small values, namely at least one pulse. If the input signal has a longer length, the second counter 30 counts a larger number of sampling pulses. In order to enable this mode of operation, the frequency of the sampling pulses emitted by the oscillator 36 must be substantially higher, for example approximately 100 or 1000 times higher than the frequency of the signal occurring at the first signal input 1.
  • the count values output by the second counter 30 are output to the first buffer 45, for example in dual or BCD form.
  • the individual output values of the second counter 30 or the values at the inputs of the buffer store 45 represent certain assigned frequencies. These values are in consequently output at the decoder 60 and, at its outputs 62, which likewise represent certain frequencies, cause output signals corresponding to the frequencies.
  • the comparator 7 serves to convert the sinusoidal input signals into square-wave signals, the period of which is determined by the zero crossings of the input signals.
  • the measuring range for the duration of these signals is determined, on the one hand, by the minimum count, which is caused by the first counter 20, and, on the other hand, by the maximum count, which is carried out by the second counter 30.
  • the count values of the first counter 20 are programmed into it by means of the coding switch 21.
  • the frequency of the sampling pulses emitted by the oscillator 36 must be adjustable by means of a reference signal and a reference control, by means of which a calibration of the oscillator 36, that is to say an adjustment of its operating frequency, is possible.
  • the second signal input 2, to which a reference signal that is emitted by a reference generator is present, and the third signal input 3, to which the reference signal is present, are used for this purpose.
  • the reference signal has the target frequency, which indicates the frequency range in which the frequency response of the input signal is to be determined.
  • the control of the oscillator 36 takes place during a time period which is determined by the reference control signal.
  • the AND gate 11 is blocked via the inverter 19, as a result of which the input signal no longer reaches the flip-flop 10.
  • output signals occur at those outputs 304 which are connected to the AND gate 16 and which represent average count values. Since the reference control signal is also applied to the AND gate 16, a pulse is sent to the set input 101 of the flip-flop 10 via the OR gate 12, through which the first counter 20 begins to count in the manner described above. As soon as the negative edge of the input signal occurs, the counter reading of the second counter 30 deleted. The first counter 20 counts up to that value which is determined by the coding switch 21.
  • the second counter 30 also begins to count again and counts up to that value which is determined by that middle output 304 which is connected to the AND gate 16, whereupon the above-described sequence is repeated.
  • a square-wave signal occurs at the Q output 103 of the flip-flop 10, the frequency of which is in exact relation to the frequency of the sampling pulses emitted by the oscillator 36.
  • This square-wave signal which is applied to the phase detector 24, is compared in this with the reference signal.
  • This generates a differential signal, which is applied via the switch 27, which is also acted upon by the reference control signal, and the low-pass filter 35 is applied to the control input 37 of the oscillator 36 as a control signal, whereby its frequency is regulated until the same in a predetermined ratio to Frequency of the reference signal is.
  • the measurement resolution is determined directly by this ratio. With a ratio of 1: 100, a resolution of 1% is achieved. With a ratio of 1: 1000, a resolution of 0.1% is achieved. An exact relationship is aimed for.
  • the second counter 30 counts a smaller number of scanning pulses. If, on the other hand, the input signal has a greater period length than the reference signal, a larger number of sampling pulses are counted in the second counter 30. In any case, changes in the period length, ie in the frequency, of the input signal compared to the reference signal are determined by the count in the second counter 30.
  • the low-pass filter 35 Since the low-pass filter 35 is actively designed with an operational amplifier, it acts as a sample and hold circuit when switched off. As a result, the voltage value is held precisely at the output for a predetermined period of time, as a result of which a measurement phase with short-term stabilization is achieved, within which the oscillator 36 emits scanning signals at the desired frequency. Due to the above-described mode of operation of the circuit, the frequency of the oscillator 36 is briefly and precisely determined by the frequency of the reference signal, the setting of which takes place during the signal duration of the reference control signal.
  • the frequency of this signal lies in the frequency range which is determined by the bandpass filter 6. Accordingly, in order to be able to detect a multiplicity of ranges by means of the bandpass filter 6, on the one hand it is necessary that the frequency of the oscillator 36 can be changed. This change is effected via the control input 37 by the reference signal. However, since this signal can lie outside the bandwidth of the bandpass filter 6 for a predetermined frequency range of the bandpass filter 6, the center frequency of the bandpass filter 6 must also be adjusted in the required manner. This is achieved in that the center frequency of the bandpass filter 6 is tuned to the frequency of the reference signal by means of the frequency-voltage converter 8.
  • bandpass filters 6 In order to be able to continuously evaluate incoming signals, at least two such bandpass filters 6 must be provided, one bandpass filter being effective and during which the second bandpass filter is changed in its center frequency, whereupon this is brought into effect and at the same time the first bandpass filter in its center frequency is regulated.
  • the entire frequency range is covered, in which those chirp signals that are to be found are located.
  • the bandwidth of the bandpass filter 6 has approximately one eighth of the frequency range of an ultrasound chirp signal, as a result of which two bandpass filters 6 are brought into effect alternately approximately four times for the entire measuring process.
  • the control inputs 72 of the individual shift registers 70 are supplied with shift pulses by the third counter 40. Given a predetermined number of N memory elements in the shift registers 70, N + 1 shift pulses emitted by the third counter 40 are required in order to shift the input signals through the individual shift registers 70, whereupon they occur at the output of the shift register 70 in question.
  • the individual shift registers 70 each contain 16 memory elements.
  • the clock pulses emitted by the oscillator 36 are divided by the third counter 40 by a predetermined factor. In the exemplary embodiment, this factor is formed by the value 20. If 340 clock pulses are counted by the first counter 20, for example, 17 clock pulses are emitted by the third counter 40 during this period. These 17 clock pulses are applied to the individual shift registers 70 via the control inputs 72 and cause the data contents read into them to be shifted. With each occurrence of a clock pulse, the data contained in the individual memory cells are shifted further by one memory cell. Thus, when 17 clock pulses occur, the data contained in the individual shift registers 70 are simultaneously pushed through them.
  • a measurement result is considered to be achieved if, in a successive group of seven pulses, an initial pulse, an end pulse and at least three further pulses occur between these two pulses.
  • a prerequisite for a usable measurement result is therefore that at least five pulses are contained in a group which is in a period of seven shifting pulses, whereby an initial pulse and an end pulse must occur in any case.
  • the memory cells located in the individual shift registers 70 are sequentially occupied with signal pulses. If signal pulses have occurred at successive outputs 62 of the decoder, a single memory cell thus becomes after a first period in a first shift register 70, becomes two memory cells after two periods in a second shift register and subsequently become further memory cells of the shift registers following in the chain 70 consecutively occupied with signal pulses. Accordingly, e.g. the fifth shift register 70 can be occupied with signal pulses in its five first memory cells.
  • the signal pulses occurring at the outputs of the shift register 70 are present at the input 81 of the associated counter circuit 80, which is shown in FIG. 2.
  • a sample pulse is applied to the sample input 83 of the counter circuit 80 by the fourth counter 50, by means of which the OR gate 801 is activated.
  • the individual values in the memory elements can subsequently be output to the counter 803 via the AND gate 802, whereupon they are counted by this.
  • signal pulses occur at the dual-coded counter outputs of the counter 803, which hold the OR gate 801 in its open position and which cause the AND gate 802 to open, as a result of which all assignments of the memory elements are counted by the counter 803.
  • the element 80 Due to its function, the element 80 can be referred to as a pulse detector.
  • the coded values present at the outputs of the counter 803 arrive at the AND gate 804 and at a dual output 86.
  • this signal arrives at the end of the scanning from the decoder 60 via the input 82 to the pulse detector 80, this signal the AND gate 804 is opened, as a result of which the pulse detector 80 outputs a signal at its output 85, which signal is fed to the assigned input of the priority decoder 90. So if a predetermined minimum number of signal pulses occurs within a sequence of seven signal pulses with an initial pulse and with an end pulse, an output pulse is produced at the pulse detector 80 and is supplied to the priority decoder 90.
  • Monoflop 31 emits pulses at different times from monoflop 29, by means of which the signal contents of pulse detectors 80 are deleted.
  • the outputs 85 of the individual pulse detectors 80 represent, compared to a central output 88, the deviations of the frequencies of the input signals from the frequency of the reference signal, which deviations in radar or sonar technology are referred to as Doppler frequency shift. These deviations are determined in the decoder 90 after their arrival in time, the first pulse received being binary coded and stored in the result memory 100.
  • 3 and 4 show a variant for determining the data values contained in the shift registers 70.
  • the data values are not sampled serially, as is the case with the circuit according to FIG. 1, but rather parallel.
  • a chain of shift registers 70, between which OR gates 75 are located, is also provided in this circuit. However, a group of storage elements of each of these individual shift registers 70 is led out via outputs, these individual outputs being connected to second inputs 122 of controlled buffer circuits 120.
  • These buffer circuits 120 have tri-state outputs 123.
  • Controlled buffer circuits 120 include two AND gates 124 and 125 and a plurality of tri-state buffers 126.
  • this circuit is as follows: During the measuring process, only one output 62 of the decoder 60 is assigned a signal. This signal arrives in one of the shift registers 70 via one of the OR gates 75 in the manner described. Furthermore, this signal is applied via the first input 121 to the AND gate 124 located in the associated buffer circuit 120. If the last relevant output of the assigned shift register 70 is occupied with a signal, this reaches the second input of the AND gate 124 via the assigned one of the second inputs 122 of the buffer circuit 120, as a result of which a signal occurs at the output thereof Individual buffers 126 provided in the buffer circuit 120 are activated, as a result of which the signals possibly present at their inputs are forwarded to the assigned outputs 123 of the buffer circuit 120.
  • the individual tri-state buffers 126 are converted from their high-resistance state to the active state, as a result of which the signals which may be present at their inputs are forwarded to the outputs 123 of the buffer circuit 120.
  • Clock pulses or scanning pulses are emitted by the oscillator 36 in accordance with the selected or determined frequency.
  • a square wave signal (line 3) is generated by the voltage comparator 7 by means of a chirp signal (line 2) coming in the predetermined frequency range, the edges of which - with a slight delay - are determined by the zero crossings of the signal. Due to its positive edge, the counting of the scanning pulses over a length of time l0 (line 4), which is determined by the coding switch 21, is initiated in the first counter 20.
  • a reset signal (line 5) reaches the second counter 30, by means of which the counter content of the second counter 30 is cleared.
  • an output signal of the first counter 20 reaches the reset input 102 of the flip-flop 10 via AND gate 23, this is switched over.
  • This causes a signal (line 6), on the one hand, to clear the content of the first counter 20 and, on the other hand, to pass the clock scanning signals to the second counter 30 via the AND gate 15, which subsequently result from the second counter be counted (line 7).
  • the counting in the second counter 30 is interrupted and thereupon whose counter content is taken from the buffer 45 and stored.
  • the first monoflop 29, which is controlled by the flip-flop 10 through the positive edges of the input signal, outputs control pulses (line 8) to the buffer 45 and to the decoder 60, and the signals contained in the memory 45 pass to the decoder over their duration 60 forwarded.
  • the positive edges of these pulses determine the point in time at which the signal values are stored in the buffer memory 4.
  • the signal duration of these pulses determines the period of time within which an output signal is output by the decoder 60 at one of its outputs.
  • the length of the output signals occurring at one of the outputs 62 of the decoder 60 thus corresponds to the length of those pulses which are emitted by the first monoflop 29.
  • the second monoflop 31 emits pulses (line 9) which are offset in time from the pulses emitted by the first monoflop 29, following them, and by which the signal contents of the counter 80 are cleared.
  • Shift pulses (line 10) are emitted by the third counter 40, the number of which is in a predetermined ratio to the number of clock pulses and through which the signals contained in the memory elements of the shift registers 70 are shifted through the shift registers 70.
  • the fourth counter 50 outputs pulses (line 11) to the pulse detectors 80 for sampling their contents and for forwarding them to the priority decoder 90.
  • the circuit arrangement up to the decoder 60 serves as a digital frequency discriminator. With this circuit, a frequency-constant signal can be determined and detected and the relative change from its frequency to the center frequency f0 can be measured and displayed.

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  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Remote Sensing (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Ultra Sonic Daignosis Equipment (AREA)
EP19880890059 1987-04-09 1988-03-17 Arrangement de circuit pour l'acquisition de signaux chirp-modulés en particulier pour l'acquisition de signaux ultrasonique chirp-modulés Withdrawn EP0286623A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT87887A AT389950B (de) 1987-04-09 1987-04-09 Schaltungsanordnung zur erfassung von chirpmodulierten signalen, insbesondere von chirpmodulierten ultraschallsignalen
AT878/87 1987-04-09

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EP0286623A2 true EP0286623A2 (fr) 1988-10-12
EP0286623A3 EP0286623A3 (fr) 1990-11-28

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EP19880890059 Withdrawn EP0286623A3 (fr) 1987-04-09 1988-03-17 Arrangement de circuit pour l'acquisition de signaux chirp-modulés en particulier pour l'acquisition de signaux ultrasonique chirp-modulés

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DE4224035A1 (de) * 1992-07-21 1994-01-27 Siemens Ag Ultraschallprüfverfahren
US10495731B2 (en) * 2016-01-08 2019-12-03 James Francis Harvey Waveform peak detection and timing for radar applications

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US3750152A (en) * 1972-04-17 1973-07-31 Gen Electric Pulse-echo phase discriminator using deltic processing
US4030096A (en) * 1975-12-05 1977-06-14 Westinghouse Electric Corporation Automatic target detector
WO1981000456A1 (fr) * 1979-07-30 1981-02-19 Dorian Ind Pty Ltd Procede et dispositif de mesure de distance
GB2094010B (en) * 1981-03-04 1984-10-03 Secr Defence A detector for periodic signals bursts
GB8334394D0 (en) * 1983-12-23 1984-02-01 Czajowski S B Electrical circuits
US4535297A (en) * 1984-01-09 1985-08-13 General Electric Company Binary signal demodulator with comparative value decision circuitry

Cited By (2)

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Publication number Priority date Publication date Assignee Title
DE4224035A1 (de) * 1992-07-21 1994-01-27 Siemens Ag Ultraschallprüfverfahren
US10495731B2 (en) * 2016-01-08 2019-12-03 James Francis Harvey Waveform peak detection and timing for radar applications

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EP0286623A3 (fr) 1990-11-28
ATA87887A (de) 1989-07-15
AT389950B (de) 1990-02-26

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