Classifications

• • G—PHYSICS
  • G08—SIGNALLING
  • G08C—TRANSMISSION SYSTEMS FOR MEASURED VALUES, CONTROL OR SIMILAR SIGNALS
  • G08C15/00—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path
  • G08C15/06—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division
  • G08C15/12—Arrangements characterised by the use of multiplexing for the transmission of a plurality of signals over a common path successively, i.e. using time division the signals being represented by pulse characteristics in transmission link

Definitions

• the present invention relates to a system for trans ⁇ ferring binary information between a plurality of trans- mitters and receivers connected to a common. communication line.
• the system is primarily intended to serve as a com ⁇ munication system for transferring on and off commands to different electrical components in a machine or different electrical units of an installation, but can also be used for a great many other applications where there is need of binary information transfer, and it should be emphasised that the system is not restricted to electrical trans ⁇ mitters or receivers, nor to an electrical communication line.
• Prior art systems for transferring on and off com ⁇ mands in a machine usually operate with a central unit in the form of a computer which, via an address line and a data line, are connected to all of the transmitters and receivers of the machine.
• the transmitters may, of course, be switches, photoelectric cells and relays supplying in ⁇ formation, on the basis of which the central unit shall supply commands to different receivers, for example re ⁇ lays, motors and solenoid valves.
• each transmitter and each receiver are connected to the communication line via a coupling unit of their own comprising a counting device, the counting de- vices of the coupling units pertaining to a group of a transmitter and at least one receiver being adapted, after reception of a unique number of pulses predetermined for that group, to couple the transmitter and the receiver(s) of that group to the communication line for transferring binary information from the transmitter to the receiver(s) of the group; and in that a clock device is coupled to si- multaneously supply pulses to said counting devices for sequentially coupling the different transmitter and re ⁇ titiver groups to said communication line.
• This system makes it possible to install the diffe ⁇ rent components of a machine together with a single com ⁇ munication line and a current supply line before the ma ⁇ chine function is finally specified.
• the coupling units can be installed and the final machine function established by programming of the coupling units. Further components can be added by supplementary wiring and suit ⁇ able programming of additional coupling units and any existing coupling units.
• the communication line can be branched in optional manner, such that e.g. looping will not be necessary.
• the coupling units are thus generally designed and given their final function by programming.
• the clock device therefore is integrated into the coupling units, at least one coup- ling unit of each group being adapted, during transfer of a binary information bit, also to provide a clock pulse supplied to all counting devices.
• At least one of the coupling units preferably comprises a mo ⁇ nitoring device which, in the absence of a clock pulse during a predetermined time interval greater than the nor- mal time interval between clock pulses, supplies a clock pulse to the communication line, such that the defective coupling unit is skipped in the operating sequence of the system.
• at least one of the coupling units may comprise a resetting device supplying a resetting signal to all counting de ⁇ vices as soon as the main switch of the machine is switched on, i.e. when voltage occurs in the current supply line. Consequently, the system also will always be ⁇ gin operating in one and the same step of its operating sequence.
• the coupling unit of the transmitter in the last group coupled in the sequence to the communication line may comprise a resetting device which supplies a resetting signal to all counting devices via the communication line when that coupling unit couples the associated transmitter to the communication line.
• the associated receiver When one of the transmitters of the system changes its state, the associated receiver will be supplied with a change command which can be delayed maximally by the time it takes to traverse the operating sequence. According to the invention, however, the reaction time for effecting a transmitter change can be reduced considerably if the coupling unit to a transmitter in a group requiring a very short reaction time, is provided with an interrupt device which, substantially immediately when the transmitter dhanges its state and independently of the position of the system in the operating sequence, produces a resetting signal supplied to all counting devices via the communi ⁇ cation line. Normally, this group should be connected as early in the operating sequence as possible so that, when the associated transmitter changes its state, the accom ⁇ panying change command will always be carried out within a fraction of the time it takes to traverse the entire ope ⁇ rating sequence.
• a logical network for example a combinatory network, which has a - plurality of inputs, optionally has time delays, and has at least one output, and in which each output can be re ⁇ lodged as a transmitter and each input as a receiver whic then must first receive its command before the composite condition can be formed.
• the coupling units pertaining to the inputs of the combinatory network must be placed at an earlier stage in the operating sequence than the coupling units pertaining to the outputs of the combinatory net ⁇ work.
• one coupling unit may be common to several transmitters and/or receivers which form several groups of transmitters and receivers. This is made possible by con ⁇ necting, a counting device which is common to the groups, to a decoder having a plurality of outputs. The different groups are distinguished by that decoder output which is activated. If use is made of decoders having several ouputs, the system according to the invention is also capable of sup- lying, in a simple manner, a receiver with information re ⁇ presenting a digital value consisting of several binary bits, in that one and the same output from the decoder is consecutively and in several steps of the sequence coupled to the communication line for successively receiving the binary bits.
• the group affi- lation of transmitters and receivers can be changed, even during traversing of the operating sequence, in that the programming is controlled by the state of one or more transmitters.
• the operating sequence can also be made to traverse any one of several parallel branches in response to the state of one or more transmitters.
• a decoder of the above type also makes it possible to connect the inputs/outputs of a computer to the communication line without complicated input/output circuits.
• Fig. 1 illu- strates schematically an information transfer system ac ⁇ cording to prior art technique.
• Fig. 2 illustrates sche ⁇ matically an information transfer system according to the invention.
• Fig. 3 illustrates a simple embodiment of a coupling unit comprised by the system of the invention.
• Fig. 4 illustrates the signal waveforms appearing in
• Fig. 5 illustrates a more complete embodiment of a coupling unit comprised by the system of the invention.
• Fig. 6 is a block diagram of a coupling unit for several groups of transmitters and receivers.
• Fig. 7 is a block diagram showing the connection of a computer to the sys ⁇ tem.
• Fig. 8 illustrates an alternative clock device.
• the prior art control system as shown in Fig. 1 com ⁇ prises a central unit 1 in the form of a computer from which an address line 2 and a data line 3 extend.
• a re- ceiver 5 and a transmitter 6 are connectible to the data line 4 via connecting units 4, 4' .
• the connecting units 4, 4' are connected both to the address line 2 and to the data line 3 and comprise, more particularly, an address decoder 7, 7' and a gate 8, 8'.
• the address decoder 7, 7' also controls the state of the gate 8, 8'.
• the transmitter 6 may be, for example, a switch, and the receiver 5 a solenoid valve.
• the central unit 1 controls the on-off switching of the receiver 5 connected to the output of the gate 8 by • transmitting the unique address of the address decoder 7 on the address line 2 and by transmitting, at the same time as the address decoder 7 opens the gate 8, a data signal on the data line 3.
• the data signal indicates whether on-switching or off-switching is to occur, and is supplied, via the gate 8, to the receiver 5.
• the central unit 1 can thus control on-off switching of an optional number of electrical components or units connected, each via one connecting unit responding to a unique address, to the data line 3 and the address line 2.
• the central unit 1 can also draw information*from the transmitter 6.
• the connect- ing unit 4' is similar to the connecting unit 4, but the communication direction through the gate 8' is opposite to the direction through the gate 8.
• the addresses of all address decoders 7; 7' are mutually different, such that the central unit 1 communicates only via one connecting unit 4, 4* at a time.
• the data line 3 is di ⁇ vided into two lines, one of which serves to feed data from the central unit 1, while the other serves to trans ⁇ fer data into the central unit 1.
• the information transfer system of the present inven ⁇ tion which is schematically illustrated in Fig. 2, is, - like the prior art system, intended for a plurality of re ⁇ vavers, of which only the receiver 5 is shown, and a plu ⁇ rality of transmitters, of which only the transmitter 6 is shown. Furthermore, it comprises a data line 9 and a clock line 9- on which clock pulses are supplied by a clock 10.
• the receiver 5 and the transmitter 6 are/ connectible to the data line 9 by means of a coupling unit 11 and ll', respectively, also connected to the clock line 9*.
• The- coupling units 11, 11' include a counting device compris ⁇ ing a counter 12, 12' and a decoder 13, i3'.
• the ' counting devices control the state of a gate 14 arid 14* , respec ⁇ tively, by which the receiver 5 and the lransmitter 6 can be connected to the data line 9.
• the de ⁇ coders 13, 13" are set to detect one and the same unique address. This means that the gate 14 in the coupling unit 11 is opened at the same time as the gate 14' of the per- taining coupling unit 11', and an input signal from the transmitter 6 is transferred via the data line 9 to the receiver 5.
• the receiver 5 thus is switched on or off in response to the value of the input signal from the trans ⁇ mitter 6.
• the system according to the invention makes it possible to arrange a very large number of pairs of coupling units 11, 11' in optional po ⁇ sitions along the data and clock lines 9, 9'.
• the coupling units of several receivers can have the same address so that one transmitter can control several receivers at the same time. In a special case, there need be no receiver for a transmitter.
• coupling units belonging together need not be positioned adjacent one another, but may be placed at optional distances from one another along the lines 9, 9' .
• the communica ⁇ tion line therefore comprises a data line (line 9), a clock line (line 9' ) and a reset line (not shown) .
• the clock 10 is preferably integrated in all coupling units, each data pulse being utilised also as a clock pulse, while the resetting signal is a specially shaped signal.
• the information transfer system according to the invention operates sequentially in a number of suc ⁇ cessive steps, and in each step a group of coupling units having the same address are connected to one another for a short time interval via the communication line, where ⁇ upon the next group of coupling units in the same way con ⁇ nects' the associated transmitters and receivers to the communication line etc.
• FIG. 3 One embodiment of the coupling units 11, 11' included in the system of the invention is shown in Fig. 3, and some of the signal waveforms occurring therein are shown in Fig. 3.
• the coupling unit shown in Fig. 3 is switchable so that it can operate either as the coupling unit 11 or as the coupling unit 11' in Fig. 2. This is achieved by setting the logical value in a point 15 of the unit. A transmitter or a receiver is connectible in a connecting point 16 forming the output to a receiver, if the logical value in point 15 is.set to equal "1", and the input from a transmitter if the logical value in the point 15 is set to equal "0".
• the coupling unit transfers signals to a communi ⁇ cation line 17 which is a single-wire conductor, via a transistor unit 8 with an output connected to the commu- nication line 17 and two inputs connected to a line 19 and a line 20, respectively. Furthermore, the coupling unit receives information from the communication line 17 via an optocoupler unit 21 having an input connected to the com ⁇ munication line 17 and two outputs each connected to one line 22 and 23, respectively.
• the signals occurring on the communication line 17 are either positive pulses or nega ⁇ tive pulses. A. positive pulse on the communication line 17 results in a positive pulse on the line 23, while a nega ⁇ tive pulse on the line 17 results in a positive pulse on thejline 22. Inversely, a positive pulse on the line 19 will generate a negative pulse on the line 17, while a po ⁇ sitive pulse on the line 20 generates a positive pulse on the line 17.
• the pulses supplied from the line 17 are fed via the lines 22 and 23 on the one hand to the reset input 24 and the clock input 25 of the counter 12 and, on the other hand, to.an input to an AND gate 26.
• the pulses on the line 23 are supplied to j a data input 27 to a latch circuit 28. All pulses on the lines 22 and 23 are supplied to the clock input 25 of the counter 12, while the reset input 24 receives a pulse only when a pulse on the line 22 and a pulse on the line 23 occur with a short time interval determined by a time circuit 29.
• the time circuit 29 is, like the other time circuits of the coup- ling unit, a monostable flip-flop which is triggered on the downward flank of incoming trigger pulses and on its output supplies a positive pulse of predetermined length, said pulse being supplied to an input to an AND gate 30, the other input of which is supplied with the pulses, com- bined via an OR gate 31, on the lines 22 and 23.
• the output of the decoder 13 is connected to the other input to the gate 26, the output of which is con ⁇ nected to the trigger input to a second time circuit 32.
• the time circuit 32 can be actuated by the output signal from the gate 26 if it is activated because the point 15 has been set to logical "0".
• the output of the decoder 13 is also connected to the read input to the latch circuit 26, the output of which is connected to the input to a NAND circuit 33.
• the other input to the gate 33 is con- nected to the point 15.
• the input of the gate 33 is con ⁇ nected to the base of a transistor 34, the collector of which is connected to the output/input 16.
• One input of an OR gate 35 is connected to the output from the time cir ⁇ cuit 32, and the other input to the output from an AND gate 36, one input of which is connected to a RC circuit 37, the other input of which is connected to a programming point 38, the logical value of which decides whether or not the coupling unit pertains to the last step of the operating sequence.
• the output of the gate 35 is connected to the trigger input -to a third time circuit 37, the output of which is connected to the trigger input to a fourth time circuit 40 and to one input of each " of two AND gates 41 and 42.
• the time circuit 40 is active-or inactive depending upon the logical value in point 38. Its output is connected to one input to an OR gate 43, the output of which is connected to the line 19.
• the input/output 16 is also connected to the input to an inverter 44 and to the other input to the gate 42.
• the output of the inverter 44 is connected to the other input to the gate 41.
• the output pulse from the time circuit 39 is supplied to the trigger input to the time circuit 40, the output pulse from the time circuit 40 will be supplied to the line 19 via the gate 43 and thus cause a negative pulse on the communication line 17 immediately after the positive pulse.
• This pulse combination is utilised as a resetting signal in the system and is shown in Fig. 4 in the signal waveform I.
• the resetting signal will reset, in the manner described above, the counter 12 in all coupling units of the system. Reference is now made to the coupling unit whose de ⁇ coder 13 is set at the count 0 in the counter 12, and the circuit point 15 of which is "0", i.e. where the circuit point 16 is the input from a transmitter not shown.
• the signal on the output of the decoder 13 will thus have a high level (logical 1) during the interval from the re ⁇ setting of the counter 12 until the next clock pulse is • supplied to the counter, as illustrated by the waveform II in Fig. 4.
• the resetting pulse which is also supplied to the clock input 25 of the counter 12, but which is sup ⁇ pressed, occurs also on one input of the gate 26 and now also on the output of this gate.
• This output pulse which is shown as waveform III in Fig. 4, triggers the time cir ⁇ cuit 32.
• the output signal from the time circuit 32 has the appearance shown as waveform IV in Fig.
• This pulse is supplied to all counters 12 as a clock pulse, and in the coupling unit whose decoder is set at count 0 and whose circuit point 15 has.
• the logical level 1 i.e. where the circuit point 16 is the output to a recei ⁇ ver not shown
• the downward flank of waveform II will read in the value of the signal waveform VI in the latch circuit 28, in this case "1".
• the signal waveform VII in Fig. 4 will appear on the output of the latch circuit 28, the output of the gate 33 will be lo ⁇ gical "0", and a high level will be generated on the out ⁇ put 16.
• Fig. 5 of the coupling unit 11, 11' contains essentially the same components as the coupling unit according to Fig. 3 and, in addition, two further component blocks A and B. Where applicable, the same reference numerals have been used in Figs. 3 and 5.
• the block A primarily replaces the circuit point 38 in Fig. 3, but has also a starting function and a monitoring function.
• the block B enables interruption and restarting of the operating sequence before this has reached its normal end.
• the RC circuit 37 in Fig. 5 is connected to the re ⁇ set input to a bistable flip-flop 45, the set input of which is connected to the outpu from the gate 30.
• the Q output of the flip-flop 45 is connected to the input to an AND gate 46, the other input of which is connected to the output from the gate 31, and the output of which is con ⁇ nected to the clock input 25 of the counter 12.
• the Q out ⁇ put of the flip-flop 45 is connected to an input to an OR gate 47, the other input of which is connnected to the output from the gate 30, and the output of which is con- nected to the reset input of the counter 12 and, further ⁇ more, to the reset input to a counter 48 in the block A.
• the RC circuit 37 is further connected to an inverter 49, the output of which is connected to an input to an AND gate 50, the other input of which is connnected to the output of the gate 31, and the output of which is con ⁇ nected to an input 51 to the block A.
• the block A has outputs 52-55 and contains, besides the counter 48 with a clock input 56, four time circuits 57-60, two OR gates 61, 62 and a selector circuit 63 with e.g. two settable final value circuit points 64, 65. These components are connected in the manner shown in Fig. 5.
• the block B has inputs 66, 67 which are connnected to the lines 22 and 23, respectively, and an input 68 which is connected to the circuit point 16.
• the block B also has an output 69 connected to the input side of the OR gate 43, and an output 70 connected to the input side of an OR gate 71 connected between the gate 42 and the line 20.
• the block B comprises three time circuits 72-74, eight gates 75-82 and a settable interrupt circuit point 83 intercon ⁇ nected in the manner shown in Fig. 5.
• the coupling unit in Fig. 5, finally, comprises three gates 84-86 on the input side of the time circuit 40 and a gate 87 on the output side thereof.
• Fig. 5 does not show the communication line 17, the transistor unit 18 and the optocoupler unit 21.
• each RC cir ⁇ cuit When the voltage in the system comprising the coup ⁇ ling unit according to Fig. 5 is switched on, each RC cir ⁇ cuit generates a pulse which, via the flip-flop 45, di ⁇ rectly resets the counters 12 and 48 and blocks the clock input 25 to the counter 12.
• the pulse from the RC circuit 37 furthermore prevents, via the gates 49, 50, triggering of the time circuits 58-60 in the block A.
• the input 16 has the logical value "0", and one of the circuit points 64, 65 has the logical value "1", for which reason the time circuit 39 is trig ⁇ gered on the downward flank of the pulse of the RC circuit 37, and then also the time circuit 40.
• Two pulses of oppo ⁇ site polarities are thus supplied successively via the gates 43 and 71 and the lines 19, 20 to the communication line 17 and from there to the lines 22, 23 of all coupling units, whereby the selected time circuit or circuits 58-60 are started on the downward flank of the first recurring pulse and open the gate 87 for feeding the second pulse to the communication line 17.
• the block A can also operate as a monitoring device in case one or more clock pulses fail to appear on the communication line.
• the signal level on the output from any of the time circuits 58, 60 will, con ⁇ trary to what is normal, change to "0", whereby the time circuit 57 is triggered and a clock pulse is fed to the communication line 17 via the gate 43 and the line 19. In this manner, the defective coupling unit is skipped, and the operating sequence continues. If the last coupling unit of the sequence should be passed, for example because of an interference, the counter 48 will be indexed and, together with the time circuit 57, generate a resetting signal so that the operating sequence is restarted from its first step.
• the block B in Fig. 5 constitutes an interrupt device which substantially immediately when the signal level on the input 16 changes, and independently of the position of the system in the operating sequence, produces a resetting signal supplied to all counters 12 via the communication line 17. This is achieved by imparting to the circuit point 83 of a coupling unit the logical value "1". Such a change in the signal level on the input 16 causes a trig ⁇ gering of the time circuit 72 and then of the time circuit 73 or 74 in response to the level on the inputs 66 and 67, respectively.
• a pulse having a polarity oppo ⁇ site to that of the pulse that caused the triggering of the time circuit 73 or 74 is supplied via the outputs 69 and 70, respectively, to the communication line 17 so that a resetting signal is generated.
• Fig. 6 illustrates a further embodiment of a coupling unit in the system of the invention.
• all components between the lines 19, 20, 22, 23, a decoder 13" and an output/input 16 with transistor 34 and optocoupler 88 are shown only in the form of a block 89.
• a coun ⁇ ter 12 and indicators 90 are shown which indicate the sig ⁇ nal level on the inputs/outputs 16.
• the decoder 13" has a plurality of outputs connected to the block 89, and the block 89 has a corresponding number of outputs connected each to one transistor 34, and a corresponding number of inputs which, via the optocouplers 88, are connectible each to one of the inputs 16 and each to one indicator 90.
• one coupling unit can be common to a plu ⁇ rality of transmitters and/or receivers which form several transmitter and receiver groups.
• the coupling unit shown in Fig. 6 is also capable of transferring information representing a digital value formed by several binary bits, by connecting one and the same output from the decoder 13" and thus from the block 89 to the communication line 17 in several consecutive steps in the operating sequence of the system, whereby the receiver at issue can be successively supplied with the binary information bits.
• the coupling unit shown in Fig. 6 can also be used for repeatedly connecting one or more transmitter and receiver groups during one and the same, operating sequence, i.e. at intervals which are shorter than the sum of the clock pulse intervals during an ope ⁇ rating sequence.
• the group affiliation of transmitters and receivers can be changed dynamically, i.e. while the operating sequence is traversed and in response to the development thereof.
• the programming inputs 91 can be controlled by the state of one or more trans ⁇ mitters.
• Fig. 7 illustrates an embodiment of a coupling unit suitable for connection of an external computer 92 to the system according to the invention.
• the decoder 13" controls a data exchange 93 having its input side connect ⁇ ed to a plurality of latch circuits 94 via which the computer 92 can carry out two-way communication with the system according to the invention.
• Fig. 8 shows an alternative clock device which also is integrated into the coupling units, but consists of a preferably crystal-controlled oscillator 95 in each coup ⁇ ling unit.
• the oscillator 95 is connected to the clock input of the counter 12 via a divider 96 which is reset every time a resetting signal appears on the output of the gate 30.
• system according to the invention is applicable to several sub-systems which can operate independently of one another, but can also communicate with one another via the coupling units ac ⁇ cording to the invention.
• one or more of the transmitters and the associated receivers can be arranged, upon activation via their counting device and decoder, to transmit and receive binary information consisting of se ⁇ veral binary information bits.
• the individual circuits of the system according to the invention can, of course, be replaced by equivalent circuits; for example, the time circuits may comprise counters. It will be appreciated that a number of modifications and alternative uses of the above-described system for transferring binary information are possible, and the in- vention should therefore be regarded as variable within the scope of the appended claims.

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• Physics & Mathematics (AREA)
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• 1988
  • 1988-03-14 SE SE8800896A patent/SE460751B/sv not_active IP Right Cessation
• 1989
  • 1989-03-13 WO PCT/SE1989/000123 patent/WO1989008958A1/en not_active Ceased
  • 1989-03-13 DE DE68915759T patent/DE68915759T2/de not_active Expired - Fee Related
  • 1989-03-13 EP EP89903830A patent/EP0407423B1/de not_active Expired - Lifetime
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