EP0417547A2 - Dispositif pour l'acquisition exacte des limites d'un interval de temps relatif à une horloge de référence - Google Patents

Dispositif pour l'acquisition exacte des limites d'un interval de temps relatif à une horloge de référence Download PDF

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Publication number
EP0417547A2
EP0417547A2 EP90116588A EP90116588A EP0417547A2 EP 0417547 A2 EP0417547 A2 EP 0417547A2 EP 90116588 A EP90116588 A EP 90116588A EP 90116588 A EP90116588 A EP 90116588A EP 0417547 A2 EP0417547 A2 EP 0417547A2
Authority
EP
European Patent Office
Prior art keywords
current
clock
comparator
latch
arrangement according
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP90116588A
Other languages
German (de)
English (en)
Other versions
EP0417547B1 (fr
EP0417547A3 (en
Inventor
Waldemar Dr. Dr.-Ing. Frühauf
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to AT90116588T priority Critical patent/ATE88027T1/de
Publication of EP0417547A2 publication Critical patent/EP0417547A2/fr
Publication of EP0417547A3 publication Critical patent/EP0417547A3/de
Application granted granted Critical
Publication of EP0417547B1 publication Critical patent/EP0417547B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/10—Apparatus for measuring unknown time intervals by electric means by measuring electric or magnetic quantities changing in proportion to time
    • G—PHYSICS
    • G04—HOROLOGY
    • G04F—TIME-INTERVAL MEASURING
    • G04F10/00—Apparatus for measuring unknown time intervals by electric means
    • G04F10/04—Apparatus for measuring unknown time intervals by electric means by counting pulses or half-cycles of an AC

Definitions

  • Integrating digital-to-analog converters are widespread (e.g. in digital voltmeters).
  • a capacitor is first charged for a constant time with a current proportional to the analog value to be measured. Then it is discharged again with a constant current to the initial value. The time required for this is the measure for the analog value.
  • Another example is the measurement of the transit time that an ultrasound pulse takes to get from the emission level of the transmitter to the receiving level of the receiver.
  • metastable flip-flop states are possible. These must be prevented using suitable aids. Metastable conditions and their causes as well as measures to reduce the probability of their occurrence in the construction of an edge-controlled flip-flop are described in the German patent application P 37 31 294.4.
  • a low-pass filter 5 and a Schmitt trigger 6 are therefore arranged between the AND gate 1 and the frequency divider 4. This solves the problem, but the clock frequency must inevitably be much lower than that theoretically possible by the AND gates 1 and flip-flops CL1 to CL4 used.
  • the circuit according to FIG. 3 shows a digital alternative in which the signal for the time interval before the AND gate is synchronized with the inverted clock by means of an auxiliary flip-flop 7.
  • the clock frequency is to be chosen so low that possible metastable states of the auxiliary flip-flop 7 have decayed in the inactive clock phase.
  • the circuit according to FIG. 4 can bring about a possible improvement.
  • a current-state-controlled bistable multivibrator instead of the AND gate, a current-state-controlled bistable multivibrator, a so-called transparent current latch 9, serves as a switch for the clock.
  • This is followed by low pass 5 and Schmitt trigger 6 again in order to screen out possible metastable vibrations of the latch 9.
  • the state of the clock (“0" or "1") is also recorded and the time resolution of the measurement is approximately doubled.
  • the usable clock frequency must be significantly lower than that which the latch 9 could switch.
  • the object of the invention is: - capture the end of the time interval (and possibly also the start of it) as precisely as possible, - to make the theoretically possible clock frequency fully usable despite the necessary consideration of excluding the influence of metastable states, - After the end of the time interval to save a measure of the current phase situation of the clock and not only a digital ("0" or "1"), but also the analog component of the time interval in a "0" or "1" period to capture.
  • Current-voltage converters 12, 13, 14 generate the voltage levels necessary for the logical further processing.
  • a clock driver generates the clock signals in phase opposition.
  • the necessary data manipulations are carried out without going through voltage levels, the generation of which takes up valuable time because of the stray capacities that are always present.
  • the current cycle state is frozen in the current range with the aid of minimal voltage levels.
  • the mixer monitors the correspondence of the clock phases at the outputs of the current latch 9 already in the current range with the clock phases at the input.
  • the circuit principle of the comparator 8 is shown in FIG. 6. It consists of a conventional PNP transistor differential stage T1, T2 with the signal input “Event” and the reference input “U ref ", the outputs of which are loaded by NPN multiple current mirrors. These, in turn, provide the required current outputs.
  • a complementary pair T5, T11 together with the current mirror T12, T13 form a current-voltage converter and provide a voltage output signal "KOMP".
  • T4 supplies the currents I clock and I latch for supplying the current latch 9
  • a single output T3 supplies the analog fine evaluation with the current I ramp
  • a further pair of transistors T6, T9 effect a positive feedback, which is in the switching range of Comparator 8 provides an infinitely large gain (especially without hysteresis) and ensures that each output current starts immediately with 50% of its end value or switches off immediately below 50%.
  • Fig. 7 shows the basic circuit structure of the current latch 9.
  • the latch function is similar to that in a circuit shown in the book “Semiconductor Circuit Technology” by Tietze and Schenk, 1989, page 776, with complementary voltage outputs, but with transistors connected as diodes instead of the load resistors that form the voltage outputs in the known example, control several current outputs.
  • the clock is at the inputs of a first transistor differential stage T14 and T15 in the form of the components CL1 and CL2 in phase opposition and, as long as I clock flows and I latch does not, causes the current outputs I mix 1 at T19 and I mix 2 at T20. Further current outputs of the transistors T18 and T21 following the clock generate a single-phase voltage output via the current-voltage conversion with the current mirror from the transistors T23 and T24, which, for example, can directly drive a frequency divider. The latch is therefore switched to pass (transparent).
  • the second transistor differential stage T16 and T17 becomes active, introduces it (still) existing clock phase position by comparing the minimum voltage difference across the transistors connected as diodes and reinforces this tendency through the positive feedback caused by their cross-coupled outputs.
  • the current clock phase state is thus "frozen", the latch is closed.
  • the current latch therefore functions in the current range and the result is initially flowing or frozen currents. Only very small voltage changes occur and extremely small delays in the logical operation due to parasitic capacitances.
  • the current state corresponding to the input clock or recorded is made evaluable by a current-voltage conversion, the switching delays due to technical reasons becoming fully effective again. This is not a disadvantage, because data manipulation has followed long before.
  • the low-pass function described in FIG. 4 is advantageously realized.
  • a Schmitt trigger is not necessary because the slope steepness already corresponds to the usual in the chosen technique.
  • the criterion is the first change of clock phase after freezing the clock in the latch, ie the deviation of the clock manipulated in the latch from the original clock.
  • the first clock phase change is determined with the aid of a mixer (FIG. 8); the fact of freezing is known to the comparator 8.
  • the AND combination of the signals KOMP and MIX thus provides the above criterion.
  • the capacitor voltage is expediently evaluated by back-integration with a constant current and measuring the time with a similar arrangement and a frequency divider or the same arrangement together with a multiplexer.
  • the previous considerations essentially relate to the determination of the end of a time interval. With similar means, it is also possible to store and evaluate the instantaneous phase situation of the clock at the beginning when the interval is not synchronized, but the circuitry effort can double.

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  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Measurement Of Unknown Time Intervals (AREA)
  • Electric Clocks (AREA)
  • Analogue/Digital Conversion (AREA)
EP90116588A 1989-09-11 1990-08-29 Dispositif pour l'acquisition exacte des limites d'un interval de temps relatif à une horloge de référence Expired - Lifetime EP0417547B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AT90116588T ATE88027T1 (de) 1989-09-11 1990-08-29 Anordnung zur genauen elektronischen erfassung der grenzen eines zeitintervalls in bezug auf einen referenztakt.

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE3930333 1989-09-11
DE3930333 1989-09-11

Publications (3)

Publication Number Publication Date
EP0417547A2 true EP0417547A2 (fr) 1991-03-20
EP0417547A3 EP0417547A3 (en) 1991-05-29
EP0417547B1 EP0417547B1 (fr) 1993-04-07

Family

ID=6389189

Family Applications (1)

Application Number Title Priority Date Filing Date
EP90116588A Expired - Lifetime EP0417547B1 (fr) 1989-09-11 1990-08-29 Dispositif pour l'acquisition exacte des limites d'un interval de temps relatif à une horloge de référence

Country Status (5)

Country Link
EP (1) EP0417547B1 (fr)
JP (1) JPH03100488A (fr)
AT (1) ATE88027T1 (fr)
CA (1) CA2024878A1 (fr)
DE (1) DE59001166D1 (fr)

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR1520487A (fr) * 1967-01-24 1968-04-12 Onera (Off Nat Aerospatiale) Procédé et appareil de chronométrie
US4598375A (en) * 1983-04-22 1986-07-01 Hagiwara Denki Kabushiki Kaisha Time measuring circuit
DE3612686A1 (de) * 1986-04-15 1987-10-22 Nukem Gmbh Verfahren und vorrichtung zur messung von zeitintervallen

Also Published As

Publication number Publication date
EP0417547B1 (fr) 1993-04-07
EP0417547A3 (en) 1991-05-29
CA2024878A1 (fr) 1991-03-12
DE59001166D1 (de) 1993-05-13
JPH03100488A (ja) 1991-04-25
ATE88027T1 (de) 1993-04-15

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