EP0452117A2 - Système d'affichage d'images - Google Patents

Système d'affichage d'images Download PDF

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Publication number
EP0452117A2
EP0452117A2 EP91303179A EP91303179A EP0452117A2 EP 0452117 A2 EP0452117 A2 EP 0452117A2 EP 91303179 A EP91303179 A EP 91303179A EP 91303179 A EP91303179 A EP 91303179A EP 0452117 A2 EP0452117 A2 EP 0452117A2
Authority
EP
European Patent Office
Prior art keywords
memory means
information
lines
displayed
image
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91303179A
Other languages
German (de)
English (en)
Other versions
EP0452117A3 (en
Inventor
Peter Evans
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Afe Technologies Ltd
Original Assignee
Afe Technologies Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Afe Technologies Ltd filed Critical Afe Technologies Ltd
Publication of EP0452117A2 publication Critical patent/EP0452117A2/fr
Publication of EP0452117A3 publication Critical patent/EP0452117A3/en
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2352/00—Parallel handling of streams of display data

Definitions

  • This invention relates to an image display system.
  • Such systems are known in which a plurality memory means have information written into them by a processing means such that each memory means stores information to enable a portion of an image to be displayed on the screen, the portion containing a plurality of lines less than the total number of lines displayed by the screen, and a plurality of pixels less than the total number of pixels displayed by the screen on each line.
  • Such systems enable blocks of image to be manipulated on the screen but because the processor means has to process a signal from an upstream central processing unit (CPU) to enable the correct information to be stored in the individual memory means, this is a slow process.
  • CPU central processing unit
  • an image display system comprising a screen on which, in use, an image is displayed in the form of a plurality of lines of information, a plurality of memory means each of which contains information to be displayed on the screen, processing means to process an input signal from a CPU and to write into the memory means the information to be displayed, characterised in that the image is displayed as a plurality of groups of information of N lines where N is the number of memory means, each memory means storing information relating to one line only of each group of lines.
  • a second aspect of the invention we provide a method of operating an image display system according to the first aspect of the invention the method comprising the steps of feeding to the processing means the input signal from the CPU, causing the processing means to write into each of the plurality of memory means information relating to one line of each group of N lines to be displayed on the screen, and feeding the stored information from each of the memory means to the screen where the composite image is displayed.
  • an image display system comprises a screen 10 (e.g. a visual display unit (VDU) ) on which in use an image I is displayed in the form of a plurality of lines 11,12, of information each comprising a row of pixels.
  • VDU visual display unit
  • the system further comprises a plurality of memory means, in this example, two memory means indicated at 14 and 15.
  • Each memory means 14,15 stores information which is repeatedly sent to the screen 10 preferably simultaneously, to provide the image I for as long as is required.
  • memory means 14 stores information relating to part of the image 1 to be displayed
  • memory means 15 stores information relating to the remainder of the image I to be displayed.
  • each memory means 14,15 may comprise a VRAM comprising a parallel data bus and a serial data bus with the serial data bus being used for the output stream of data to the screen 10.
  • the information is written into the respective memory means 14,15, by processing means comprising a first processor 16 which writes information into the memory 14, and a second processor 17 which writes information into the memory means 15.
  • the processors 16,17 are preferably generally identically constructed but alternatively configured such that the processors 16 and 17 are each arranged to respond only to part of an input signal from an upstream central processing unit (CPU) 21 which is also connected to each of the processors 16,17, by a bus 20.
  • CPU central processing unit
  • the input signal will comprise a stream of information which is to be displayed on the screen 10 as the plurality of lines 11,12.
  • the system operates so that the processor 16 is responsive to those parts of the input signal relating to every other line 11 of the image I to be displayed, whilst processor 17 is responsive to those parts of the input signal relating to each of the other lines 12 of the image I.
  • processor 16 then writes into the memory means 14 information relating only to the lines 11, whilst processor 17 writes into the memory means 15 information relating to the lines 12 only and the memory means 14,15, under the control of their respective processors 16,17, then together provide all the necessary information to the screen 10 to enable the entire composite image I to be displayed.
  • the memory means 14,15 may be provided as physically separate units but alternatively, may comprise different areas of a single memory unit which are separately addressable and into which the appropriate line information can individually be written.
  • the processors 16,17 may be separate physical units as shown, but alternatively may be provided as a single unit comprising a plurality of processing areas which are each individually responsive to their individual respective line information. However, separate processors 16,17, are preferred.
  • processors 16,17 may be individually constructed so as to respond to address or scan information contained in the input signal from the CPU 21 so that the processors 16,17, write only the appropriate line information in the corresponding memory 14,15.
  • the screen will display the image I as a plurality of groups of N lines, each memory means storing information relating to one line only of each group of N lines.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
EP19910303179 1990-04-11 1991-04-10 Image display system Withdrawn EP0452117A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9008279A GB2243519B (en) 1990-04-11 1990-04-11 Image display system
GB9008279 1990-04-11

Publications (2)

Publication Number Publication Date
EP0452117A2 true EP0452117A2 (fr) 1991-10-16
EP0452117A3 EP0452117A3 (en) 1992-07-01

Family

ID=10674316

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19910303179 Withdrawn EP0452117A3 (en) 1990-04-11 1991-04-10 Image display system

Country Status (2)

Country Link
EP (1) EP0452117A3 (fr)
GB (1) GB2243519B (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000065565A1 (fr) * 1999-04-23 2000-11-02 Opti, Inc. Controleur d'ecran a haute resolution a frequence de fonctionnement reduite, destine au circuit traitant les donnees d'affichage

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5357606A (en) * 1992-02-25 1994-10-18 Apple Computer, Inc. Row interleaved frame buffer

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4648045A (en) * 1984-05-23 1987-03-03 The Board Of Trustees Of The Leland Standford Jr. University High speed memory and processor system for raster display
WO1988000751A2 (fr) * 1986-07-18 1988-01-28 Sigmex Limited Appareil d'affichage graphique a balayage recurrent
US4967392A (en) * 1988-07-27 1990-10-30 Alliant Computer Systems Corporation Drawing processor for computer graphic system using a plurality of parallel processors which each handle a group of display screen scanlines

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2000065565A1 (fr) * 1999-04-23 2000-11-02 Opti, Inc. Controleur d'ecran a haute resolution a frequence de fonctionnement reduite, destine au circuit traitant les donnees d'affichage

Also Published As

Publication number Publication date
GB2243519A (en) 1991-10-30
EP0452117A3 (en) 1992-07-01
GB9008279D0 (en) 1990-06-13
GB2243519B (en) 1994-03-23

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