EP0455360B1 - Verfahren zur Herstellung einer Solarzelle - Google Patents

Verfahren zur Herstellung einer Solarzelle Download PDF

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Publication number
EP0455360B1
EP0455360B1 EP91303176A EP91303176A EP0455360B1 EP 0455360 B1 EP0455360 B1 EP 0455360B1 EP 91303176 A EP91303176 A EP 91303176A EP 91303176 A EP91303176 A EP 91303176A EP 0455360 B1 EP0455360 B1 EP 0455360B1
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Prior art keywords
substrate
layer
layers
gaas
front surface
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English (en)
French (fr)
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EP0455360A1 (de
Inventor
Takahiko Oohara
Yoshiro Ohmachi
Yoshiaki Kadota
Kotaro C/O Mitsubishi Denki K.K. Mitsui
Nobuyoshi C/O Mitsubishi Denki K.K. Ogasawara
Takashi C/O Mitsubishi Denki K.K. Nishimura
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Mitsubishi Electric Corp
NTT Inc
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Mitsubishi Electric Corp
Nippon Telegraph and Telephone Corp
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Priority to EP92201966A priority Critical patent/EP0509615B1/de
Priority to EP92201963A priority patent/EP0507420B1/de
Priority to EP92201965A priority patent/EP0509614B1/de
Publication of EP0455360A1 publication Critical patent/EP0455360A1/de
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F10/00—Individual photovoltaic cells, e.g. solar cells
    • H10F10/10—Individual photovoltaic cells, e.g. solar cells having potential barriers
    • H10F10/14—Photovoltaic cells having only PN homojunction potential barriers
    • H10F10/144—Photovoltaic cells having only PN homojunction potential barriers comprising only Group III-V materials, e.g. GaAs,AlGaAs, or InP photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F19/00—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules
    • H10F19/20—Integrated devices, or assemblies of multiple devices, comprising at least one photovoltaic cell covered by group H10F10/00, e.g. photovoltaic modules comprising photovoltaic cells in arrays in or on a single semiconductor substrate, the photovoltaic cells having planar junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F71/00—Manufacture or treatment of devices covered by this subclass
    • H10F71/127—The active layers comprising only Group III-V materials, e.g. GaAs or InP
    • H10F71/1276—The active layers comprising only Group III-V materials, e.g. GaAs or InP comprising growth substrates not made of Group III-V materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10F—INORGANIC SEMICONDUCTOR DEVICES SENSITIVE TO INFRARED RADIATION, LIGHT, ELECTROMAGNETIC RADIATION OF SHORTER WAVELENGTH OR CORPUSCULAR RADIATION
    • H10F77/00—Constructional details of devices covered by this subclass
    • H10F77/20—Electrodes
    • H10F77/206—Electrodes for devices having potential barriers
    • H10F77/211—Electrodes for devices having potential barriers for photovoltaic cells
    • H10F77/215—Geometries of grid contacts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/29—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by the substrates
    • H10P14/2901—Materials
    • H10P14/2902—Materials being Group IVA materials
    • H10P14/2905—Silicon, silicon germanium or germanium
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3202—Materials thereof
    • H10P14/3214—Materials thereof being Group IIIA-VA semiconductors
    • H10P14/3221—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/32—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by intermediate layers between substrates and deposited layers
    • H10P14/3242—Structure
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/34—Deposited materials, e.g. layers
    • H10P14/3402—Deposited materials, e.g. layers characterised by the chemical composition
    • H10P14/3414—Deposited materials, e.g. layers characterised by the chemical composition being group IIIA-VIA materials
    • H10P14/3421—Arsenides
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/20—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials
    • H10P14/36—Formation of materials, e.g. in the shape of layers or pillars of semiconductor materials characterised by treatments done before the formation of the materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/544—Solar cells from Group III-V materials
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/933—Germanium or silicon or Ge-Si on III-V

Definitions

  • the present invention relates to a method for manufacturing a GaAs solar cell on a Si substrate.
  • Figures 9(a) & (b) are views showing a structure of a conventional GaAs solar cell on an Si substrate, in which figure 9(a) is its plan view and figure 9 (b) is a sectional view taken along a line A-A in figure 9(a).
  • reference numeral 1 designates an Si substrate.
  • An n type GaAs layer 2 and a p type GaAs layer 3 which serve as active layers are laminated on a first main surface 1a of the Si substrate 1 and then an anode electrode (p type electrode) 6 is formed on the p type GaAs layer 3 and a cathode electrode (n type electrode) 5 is provided on a second main surface 1b of the Si substrate 1.
  • a solar cell 21 is formed.
  • the GaAs solar cell 21 on the Si substrate is normally manufactured by the following method.
  • the n type GaAs layer 2 and the p type GaAs layer 3 are sequentially formed on the first main surface 1a of the n type Si substrate 1 having a surface orientation of approximately (100) by a method of crystal growth of a compound semiconductor, such as MOCVD method.
  • a pn junction 4 which generates a photovoltaic effect is formed.
  • the anode electrode (p side electrode) 6 is selectively formed on the p type GaAs and the cathode electrode (n side electrode) 5 is formed on the whole surface of the second main surface 1b of the Si substrate 1.
  • the anode electrode 6 comprises collecting electrodes 6a for collecting a photoelectric current and a common electrode 6b for connecting the collecting electrodes to an outside circuit.
  • these electrodes are formed by sputtering or a vapour deposition method and Ti/Ag is normally used as their materials.
  • the conventional GaAs solar cell on the Si substrate has the following problems. That is, since the n type GaAs layer 2 and the p type GaAs layer 3 are usually formed at a high temperature of 700 to 800°C, when a wafer on which the above GaAs layers are formed is taken out at a room temperature, a large warpage is generated because of a difference in thermal expansion coefficient between GaAs and Si as shown in figure 9(b).As the thickness of the GaAs layer is increased, the degree of this warpage becomes large. When the thickness of the GaAs layer exceeds 3 ⁇ m, a crack is generated. On the other hand, as the thickness of the GaAs layer is increased, dislocation density in the GaAs layer is reduced.
  • the thickness should be 4 to 5 ⁇ m.
  • the crack is generated in the operation layer (active layer) of the conventional solar cell.
  • a region surrounded by a crack 7 on which the collecting electrode 6a is not provided, which region is shown by slanting lines in figure 9(a) is a loss region because the generated photoelectric current cannot be collected.
  • Japanese Kokai 63-236308 has addressed the problem of wafer warpage and cracking.
  • a silicon nitride film is grown on the rear surface of the silicon substrate at a low temperature of the order of 300°C by plasma CVD, thermal CVD or sputtering.
  • the silicon substrate is plastically deformed convexly on the substrate side when the substrate is heated to a temperature equal to or higher than approximately 800°C.
  • the silicon nitride film is removed and a compound semiconductor layer of GaAs is grown by MOCVD while the substrate is still plastically deformed and maintained at a temperature of between 600 and 750°C.
  • the substrate is then cooled to room temperature.
  • Japanese Kokai 61-225816 has also addressed the problem of reducing wafer warpage.
  • An auxiliary layer of material having a coefficient of thermal expansion similar to that of a gallium arsenide active layer is first formed on the rear surface of the silicon substrate at a temperature which is the same as that for forming the gallium arsenide active layer.
  • the present invention is intended as a solution to the problems aforesaid.
  • a method of manufacturing a gallium arsenide on silicon solar cell comprises: providing a silicon substrate having front and rear surfaces; depositing on the rear surface of said substrate a layer of material of lower thermal expansion coefficient than silicon; raising the temperature of said substrate so that the front surface thereof becomes convex; growing on the convex front surface of said substrate successive first and second layers of gallium arsenide, which layers are doped p or n-type and n or p-type respectively; and causing said substrate and successive first and second layers to cool to room temperature; which method is characterised in that: the step of depositing said layer of material is performed at a temperature at or close to room temperature; the thickness of said layer of material deposited is such that upon performing the step of raising the temperature of said substrate, the substrate is deformed elastically to produce said convex front surface; and the respective thickness of the grown first and second layers, the substrate, and the deposited layer of material, are such that upon said cooling to room temperature the substrate is substantially flat and said first
  • the layer formed of the material having a thermal expansion coefficient smaller than that of the Si substrate warps the Si substrate into a convex shape at a temperature when the GaAs layer is formed, that is, a stress is generated on the first main surface of the Si substrate.
  • a stress is generated on the first main surface of the Si substrate.
  • a layer comprising a conductive material having a thermal expansion coefficient smaller than that of Si can be formed on the second main surface of the Si substrate at a temperature close to the room temperature before the first and second GaAs layers of the first and second conductivity types, which serve as the active layers, are formed on the first main surface of the first conductivity type Si substrate. This can be used as an electrode.
  • a GaAs buffer layer to which a first conductivity type impurity of high concentration is applied can be formed on the first main surface of the first conductivity type Si substrate before the layer comprising a material having a thermal expansion coefficient smaller than that of the Si substrate is formed on the second main surface of the Si substrate at a temperature close to the room temperature and the first and second GaAs layers of first and second conductivity types are sequentially formed on the buffer layer.
  • an active layer can be formed on a clean surface of the Si substrate having no thermal stress.
  • Figures 1(a) to (d) are sectional views showing a method for manufacturing a solar cell in accordance with a first embodiment of the present invention.
  • reference numeral 1 designates an n type Si substrate
  • reference numeral la designates a first main surface of the Si substrate
  • reference numeral 1b designates a second main surface opposite to the first main surface 1a.
  • An n type GaAs layer 2 is arranged on the first main surface la of the Si substrate 1.
  • a p type GaAs layer 3 is arranged on the n type GaAs layer 2.
  • A, pn junction 4 is formed between the n type GaAs layer 2 and the p type GaAs layer 3.
  • Reference numeral 10 designates an auxiliary layer comprising a material having a thermal expansion coefficient smaller than that of Si, which is formed on the second main surface of the Si substrate 1.
  • the auxiliary layer 10 comprising a material having a thermal expansion coefficient smaller than that of Si is formed on the second main surface 1b of the n type Si substrate 1 of a (100) surface whose surface orientation is inclined by 2 degrees in the ⁇ 111> direction at a temperature close to the room temperature as shown in figure 1(a).
  • a material of this auxiliary layer 10 boron nitride (BN), carbon (C), silicon dioxide (SiO2) or the like is used.
  • the auxiliary layer 10 is formed by sputtering or a photo-assisted chemical vapor deposition.
  • n type GaAs layer 2 and the p type GaAs layer 3 are formed by an MOCVD method, MBE method or the like as shown in figure 1(c).
  • an epitaxial wafer which is not warped and has no residual stress in the GaAs layer can be provided as shown in figure 1(d).
  • the GaAs solar cell 22 on the Si substrate shown in figure 2 can be formed using the above epitaxial wafer by the room method for manufacturing the solar cell.
  • reference numeral 5 designates an n side electrode which is formed on the second main surface of the Si substrate by vapour deposition, sputtering, plating method or the like using a metal material such as Ti/Au after the layer 10 having a thermal expansion coefficient smaller than that of Si is removed.
  • reference numeral 6 designates a p side electrode which is selectively formed on a part of the surface of the p type GaAs layer 3 by photolithography or the like so that light may be input into the pn junction 4 which generates photoelectromotive force.
  • the p side electrode 6 comprises collecting electrodes 6a for collecting a photoelectric current and a common electrode 6b for connecting the collecting electrode 6a to the outside circuit.
  • the p side electrode 6 may be formed using the same material and method as those of the n side electrode 5.
  • a flat epitaxial wafer can be formed in accordance with the first embodiment of the present invention, it is not necessary to apply stress from the outside to flatten the wafer in the step of photolithography which requires flatness or the step of grinding the back surface for adjusting the thickness while the solar cell is manufactured. As a result, crack generation is prevented in the GaAs layers 2 and 3. In addition, since it is also not necessary to apply stress from the outside to flatten the wafer at the time of interconnecting to the electrodes 5 and 6 in an assembling step for modulation, again crack generation is prevented.
  • FIG 3 is a schematic view showing a state of the wafer shown in figure 1(b).
  • reference character R designates a radius of curvature of warpage
  • reference character D designates a thickness of the Si substrate
  • reference character d designates a thickness of BN formed at the room temperature.
  • a neutral surface N of strain and stress exists in the wafer and its position is obtained as follows.
  • Y D 2 1 + 2t 1 + et
  • t d/D
  • e ( E BN 1 - ⁇ BN ) / ( E Si 1 - ⁇ Si )
  • E BN and ⁇ BN are Young's modulus and Poissons ratio of BN, respectively.
  • extension ⁇ l on the surface la is as follows. ⁇ Y R l More specifically, when BN is formed on the back surface 1b of the Si substrate at the room temperature and then heated up at the GaAs growing temperature, the 1a surface of the Si substrate on which GaAs is to be grown up is extended to l + ⁇ l.
  • the thickness of BN is approximately 38 ⁇ m and the thickness of the Si substrate is 100 ⁇ m.
  • n electrode is formed on the second main surface 1b of the Si substrate after the layer 10 comprising a material whose thermal expansion coefficient is smaller than that of Si is removed in the above first embodiment of the present invention
  • a conductive material may be used as a material whose thermal expansion coefficient is smaller than that of Si, which serves as the n type electrode as it is in the second embodiment of the present invention.
  • a BN film to which carbon is applied in high concentration may be used.
  • This is formed by a reactive sputtering method using acetylene as reactive gas or photo-assisted chemical vapour deposition using diborane and ammonia as main gases and acetylene as doping gas in which a BN sintered body is used as a target.
  • resistivity of the Si substrate is high, contact resistance between BN and Si becomes high.
  • it is possible to reduce the contact resistance by selectively forming through holes on the BN film 10′ and forming a metal electrode 11 comprising a material such as Ti/Au on the exposed second main surface of the Si substrate as shown in figure 4.
  • an interconnecting part for modulation may be formed on the metal electrode 11. In this case, welding of the interconnector or the like can be performed on the metal electrode 11 more easily than on the BN film 10′.
  • Figures 5(a) to (d) are sectional views showing a method for manufacturing a solar cell in accordance with the third embodiment of the present invention.
  • the same references as in figure 1 designate the same or corresponding parts and reference numeral 12 designates an n+ GaAs buffer layer.
  • a n+ GaAs layer 12 having a thickness of approximately 2 ⁇ m is formed on the first main surface 1a of the Si substrate 1.
  • the BN film 10 is formed at the room temperature.
  • the substrate is warped a little by thermal stress of the n+ GaAs layer.
  • the thickness of the n+ GaAs layer is 2 ⁇ m or less, the degree of warpage can be disregarded.
  • the wafer is heated up at a temperature when the GaAs layer is grown, it is warped like in figure 1(b).
  • the degree of warpage is smaller than that shown in figure 1(b) because of the n+ GaAs layer.
  • figure 5(c) type GaAs layer 2 and the p type GaAs layer 3 which are necessary for the solar cell are formed and then the wafer is taken out at the room temperature.
  • the degree of warpage can be considerably reduced as compared with a conventional example where there is no BN film.
  • the warpage is generated a little, there are the following advantages as compared with the first embodiment of the present invention.
  • the GaAs layer is formed on the Si substrate in general, it is necessary to clean the surface of the Si substrate at a high temperature of 900 to 1000°C before the GaAs layer is grown thereon.
  • a foreign material such as BN is formed on the second main surface of the Si substrate, the first main surface of the Si substrate is polluted at the above high temperature processing, with the result that epitaxial growth of GaAs is not uniformly implemented.
  • the GaAs layer is formed on the.Si substrate, GaAs can be epitaxially grown on the clean Si substrate having no foreign material, so that a uniform grown layer is obtained.
  • the GaAs layer is formed at a temperature of 700 to 800°C after the BN is formed at the room temperature, because the n+ GaAs layer 12 is already formed, homoepitaxial growth can be implemented and then the GaAs layer is uniformly formed in a relatively easy manner. In addition, because it is grown at a considerably low temperature of 900 to 1000°C, the element can be prevented from being polluted by BN.
  • Figure 6 are sectional views showing a method for manufacturing a solar cell in accordance with a variation of the third embodiment of the present invention.
  • the same reference numerals as in figure 5 designate the same or corresponding parts and reference numerals 13 and 14 designate mesa grooves formed in the vicinity of the wafer.
  • the wafer is formed like in figure 5(a).
  • the BN film 10 is formed and then the mesa groove 13 is formed by selectively etching the n+ GaAs layer 12 so that a part of the Si substrate surface may be exposed.
  • the wafer is heated up at 700 to 800°C and then it is warped.
  • the n type GaAs layer 2 and the p type GaAs layer 3 are formed.
  • a natural oxide film is formed on the Si surface which is exposed by the mesa groove, a GaAs crystal is not grown but the GaAs layer is selectively grown thereon.
  • figure 6(e) when the wafer is taken out of the GaAs crystal growing apparatus at the room temperature, the degree of warpage is reduced as compared with that by the conventional method.
  • the mesa groove 14 whose width is larger than that of the mesa groove 13 is formed by selectivity removing the GaAs layer in the vicinity of the mesa groove 13 formed after the n+ GaAs layer 12 is formed.
  • the reason why the mesa groove 14 is formed is described hereinafter.
  • the GaAs layer is not grown on the Si substrate surface of the mesa groove in the step shown in figure 6(d). In this GaAs layer growing process, since reactive gas applied to the mesa groove is not deposited on the Si substrate, it is used for GaAs growth in the vicinity of the mesa groove.
  • a grown layer becomes thick in the vicinity of the mesa groove and specially its edge part is sharply swollen. Since mechanical stress is concentrated in this swollen part, many cracks are generated from this part. Therefore, the mesa groove 14 shown in figure 6(e) are formed by selectively removing the swollen part.
  • Figure 8 is a view showing an example of a sectional structure of the GaAs layer in the vicinity of the mesa groove, in which stress concentration in the vicinity of the element can be reduced as much as possible in accordance with the variation of the third embodiment of the present invention.
  • the angle formed between a side surface of the p type GaAs layer 2 and the n type GaAs layer 3 and a p type GaAs layer surface 3a is set at 90° or more to prevent the stress from being concentrated in an acute angle part.
  • This configuration can be easily formed by a method such as forward mesa etching in the GaAs layer having a growing surface in the vicinity of (100) surface.
  • the above structure can be formed by reducing adhesive strength between the photoresist and the GaAs layer in the vicinity of the mesa groove to accelerate etching at an interface between the photoresist and GaAs.
  • the contact angle formed between the n+ GaAs layer and an interface against the Si substrate is an obtuse angle, the stress is prevented from being concentrated.
  • This configuration can be easily formed by using nature of etchant in which etching speed depends on the stress.
  • the configuration shown in figure 8 can be etched away using solution of sulphuric acid, hydrogen peroxide and water as etchant for GaAs.
  • a layer comprising a material having a thermal expansion coefficient smaller than that of the Si substrate is formed on the second main surface of the first conductivity type Si substrate at a temperature close to the room temperature and then the first and second GaAs layers of first and second conductivity types which serve as active layers are formed on the first main surface of the Si substrate.
  • residual stress in the GaAs layer can be reduced and the degree of warpage can be also reduced, so that a more flat epitaxial wafer can be obtained and there is provided a GaAs solar cell on the Si substrate which has no or few cracks.
  • a layer comprising a conductive material having a thermal expansion coefficient smaller than that of Si is formed on the second main surface of the Si substrate at a temperature close to the room temperature, then as a result, in addition to the effect obtained as above the steps of removing the auxilliary layer and then forming the first electrode are not necessary and the manufacturing process is simplified.
  • a temperature becomes lower than the room temperature in a thermal shock test or the like a compressed stress is applied to the GaAs layer, which offsets the residual tensile stress. As a result, crack generation is prevented.
  • the GaAs buffer layer to which an impurity of the first conductivity type of high concentration is applied is formed on the first main surface of the first conductivity type Si substrate and then the layer comprising a material having a thermal expansion coefficient smaller than that of the Si substrate is formed on the second main surface of the substrate at a temperature close to the room temperature and then the first and second GaAs layers of the first and second conductivity types are sequentially formed on the buffer layer.
  • the GaAs active layer which has no thermal stress on the clean Si substrate surface.

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  • Photovoltaic Devices (AREA)

Claims (13)

  1. Ein Verfahren zur Herstellung einer Galliumarsenidauf-Solarzelle, wobei das Verfahren aufweist:
       Bereitstellen eines Siliziumsubstrates (1) mit vorden und rückwärtigen Obeflächen (1a, 1b);
       Abscheiden einer Schicht (10) eines Materiales von geringerem thermischen Ausdehnungskoeffizienten als Silizium auf der rückwärtigen Oberfläche (1b) des Substrates (1);
       Anheben der Temperatur des Substrates (1), so daß die vordere Oberfläche (1a) hiervon konvex wird;
       Aufeinanderfolgendes Aufwachsen erster und zweiter Schichten (2, 3) von Galliumarsenid auf der konvexen vorderen Oberfläche (1a) des Substrates (1), wobei die Schichten (2, 3) p- oder n-dotiert bzw. n- oder p-dotiert sind; und
       Abkühlenlassen des Substrates (1) und der aufeinanderfolgenden ersten und zweiten Schichten (2, 3) auf Raumtemperatur;
       wobei das Verfahren dadurch gekennzeichnet ist, daß:
       der Schritt des Abscheidens der Schicht (10) des Materiales bei einer Temperatur bei oder nahe bei Raumtemperatur durchgeführt wird;
       die Dicke der Schicht (10) des abgeschiedenen Materiales so ist, daß beim Durchführen des Schrittes des Anhebens der Temperatur des Substrates (1) das Substrat (1) elastisch deformiert wird, um die konvexe vordere Oberfläche (1a) zu erzeugen; und
       die jeweiligen Dicken der aufgewachsenen ersten und zweiten Schichten (2, 3), des Substrates (1) und der abgeschiedenen Schicht (10) des Materiales so sind, daß bei Abkühlen auf Raumtemperatur das Substrat (1) im wesentlichen flach ist und die ersten und zweiten Schichten (2, 3) im wesentlichen frei von verbleibenden thermischen Belastungen sind.
  2. Ein Verfahren nach Anspruch 1, wobei dem Schritt des Abscheidens der Schicht (10) des Materials ein Schritt vorausgeht, in dem eine Dünnfilmschicht (12) aus Galliumarsenid, welches n⁺- oder p⁺-dotiert ist auf der vorderen Oberfläche (1a) des Substrates (1) aufgewachsen wird.
  3. Ein Verfahren nach einem der vorhergehenden Ansprüche, wobei nach dem Abkühlen auf Raumtemperatur die Schicht (10) des Materials durch eine Schicht des Elektrodenmaterials ersetzt wird.
  4. Ein Verfahren nach Anspruch 3, wobei die Schicht (10) des Materiales Siliziumoxid, Siliziumnitrid, Bornitrid, Kohlenstoff, oder eine Kombination hiervon aufweist.
  5. Ein Verfahren nach einem der vorhergehenden Ansprüche 1 oder 2, wobei die Schicht (10) des Materiales elektrisch leitfähig ist und als Elektrodenschicht geeignet ist.
  6. Ein Verfahren nach Anspruch 5, wobei die Schicht (10) des Materiales Bornitrid aufweist und eine hohe Konzentration von Kohlenstoff-Dotiermittel zur Verbesserung der elektrischen Leitfähigkeit beinhaltet.
  7. Ein Verfahren nach einem der vorhergehenden Ansprüche 1 oder 2, wobei Durchgangsbohrungen in der Schicht (10) des Materiales gebildet werden und metallisches Elektrodenmaterial (11) an der rückwärtigen Oberfläche hiervon abgeschieden wird und die Durchgangsbohrungen hiermit gefüllt werden.
  8. Ein Verfahren nach Anspruch 7, wobei die Schicht (10) des Materiales kohlenstoffdotiertes Bornitrid ist und das metallische Elektrodenmaterial (11) aus Titan und Gold ist.
  9. Ein Verfahren nach Anspruch 2 oder einem Anspruch, der von Anspruch 2 abhängig ist, wobei die Dicke der Dünnfilmschichten (12) 2 µm oder weniger beträgt.
  10. Ein Verfahren nach Anspruch 2, oder irgend einem Anspruch, der vom Anspruch 2 abhängt, bei dem:
       nach dem Aufwachsen der Dünnfilmschicht (12) aus Galliumarsenid aber vor dem Aufwachsen der ersten und zweiten Schichten (2, 3) eine Ausnehmung (13) in der Dünnfilmschicht (12) gebildet wird, welche die darunter liegende Oberfläche (1a) des Siliziumsubstrates (1) freilegt, wobei auf dieser freiliegenden Oberfläche (1a) ein natürliches Oxid gebildet wird; und
       der Schritt des Aufwachsens der ersten und zweiten Schichten (2, 3) so durchgeführt wird, daß das Material nur auf dem verbleibenden Teil der Dünnfilmschicht (12) aufgewachsen wird.
  11. Ein Verfahren nach Anspruch 10, wobei Material von den Kantenbereichen der ersten und zweiten Schichten (2, 3) entfernt wird.
  12. Ein Verfahren nach Anspruch 11, wobei nach dem Entfernen des Materiales der Winkel, der zwischen der Kantenoberfläche der ersten und zweiten Schichten (2, 3) und der vorderen Oberfläche (1a) des Substrates (1) eingeschlossen ist, 90° oder weniger beträgt.
  13. Ein Verfahren nach Anspruch 12, wobei der Kontaktwinkel, der an der Schnittstelle der Dünnfilmschicht (12) und der vorderen Oberfläche (1) des Substrates (1) eingeschlossen wird, 90° oder mehr beträgt und der Winkel, der zwischen der Kantenoberfläche der Dünnfilmschichten (12) und der ersten und zweiten Schichten (2, 3) und der vorderen Oberfläche (1a) des Substrates (1) eingeschlossen ist, eine kontinuierlich graduell abnehmende Funktion des Abstandes von der vorderen Oberfläche (1a) des Substrates (1) ist.
EP91303176A 1990-04-13 1991-04-10 Verfahren zur Herstellung einer Solarzelle Expired - Lifetime EP0455360B1 (de)

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EP92201963A EP0507420B1 (de) 1990-04-13 1991-04-10 Verfahren zur Herstellung einer Solarzelle
EP92201965A EP0509614B1 (de) 1990-04-13 1991-04-10 Solarzelle

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JP2098802A JP2542447B2 (ja) 1990-04-13 1990-04-13 太陽電池およびその製造方法
JP98802/90 1990-04-13

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EP92201963.3 Division-Into 1992-07-01
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EP91303176A Expired - Lifetime EP0455360B1 (de) 1990-04-13 1991-04-10 Verfahren zur Herstellung einer Solarzelle
EP92201963A Expired - Lifetime EP0507420B1 (de) 1990-04-13 1991-04-10 Verfahren zur Herstellung einer Solarzelle
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DE69120524D1 (de) 1996-08-01
DE69120524T2 (de) 1996-10-31
DE69114760D1 (de) 1996-01-04
EP0666602A3 (de) 1996-01-10
EP0511718A3 (de) 1992-11-19
EP0455360A1 (de) 1991-11-06
DE69114760T2 (de) 1996-04-11
EP0666602B1 (de) 1998-06-24
EP0511718A2 (de) 1992-11-04
DE69129667D1 (de) 1998-07-30
EP0509614B1 (de) 1996-12-11
DE69129667T2 (de) 1999-03-11
DE69120525T2 (de) 1996-10-31
EP0507420A1 (de) 1992-10-07
EP0666602A2 (de) 1995-08-09
DE69120525D1 (de) 1996-08-01
EP0509615B1 (de) 1996-06-26
JP2542447B2 (ja) 1996-10-09
JPH03296278A (ja) 1991-12-26
EP0509614A1 (de) 1992-10-21
EP0509615A2 (de) 1992-10-21
DE69123567T2 (de) 1997-04-10
DE69123567D1 (de) 1997-01-23
EP0509615A3 (de) 1992-11-19
EP0507420B1 (de) 1996-06-26
US5145793A (en) 1992-09-08

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