EP0492718A2 - Circuit de verrouillage automatique par balayage pour une boucle à verrouillage de phase - Google Patents

Circuit de verrouillage automatique par balayage pour une boucle à verrouillage de phase Download PDF

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Publication number
EP0492718A2
EP0492718A2 EP91203333A EP91203333A EP0492718A2 EP 0492718 A2 EP0492718 A2 EP 0492718A2 EP 91203333 A EP91203333 A EP 91203333A EP 91203333 A EP91203333 A EP 91203333A EP 0492718 A2 EP0492718 A2 EP 0492718A2
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EP
European Patent Office
Prior art keywords
sweep
lock
output
circuit
voltage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP91203333A
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German (de)
English (en)
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EP0492718A3 (en
Inventor
John Daniel Foell
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Magnavox Electronic Systems Co
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Magnavox Electronic Systems Co
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Publication date
Application filed by Magnavox Electronic Systems Co filed Critical Magnavox Electronic Systems Co
Publication of EP0492718A2 publication Critical patent/EP0492718A2/fr
Publication of EP0492718A3 publication Critical patent/EP0492718A3/en
Withdrawn legal-status Critical Current

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
    • H03L7/095—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal using a lock detector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/10—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range
    • H03L7/12—Details of the phase-locked loop for assuring initial synchronisation or for broadening the capture range using a scanning signal
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S331/00—Oscillators
    • Y10S331/02—Phase locked loop having lock indicating or detecting means

Definitions

  • the present invention relates generally to phase-locked loops and, more particularly, to a novel sweep-to-lock circuit for a phase-locked loop of the type having an analog phase detector, which circuit causes rapid locking and provides automatic initiation of sweeping and resweeping, prevention of false locks, detection of correct lock, and halting of sweep at correct lock.
  • Phase-locked loops are widely employed in electronic circuitry and are used, for example, in satellite communication systems, airborne navigation systems, and FM communication systems, providing the functions of, for example, phase detection, frequency modulation/demodulation, frequency division/multiplication (frequency synthesis), filtering, and voltage-controlled oscillator stabilisation.
  • the basic technique compares the frequency and phase of the incoming signal to the output of a voltage controlled oscillator (VCO). If the two signals differ in frequency and/or phase, an error voltage is generated and applied to the VCO, causing it to correct in the direction required for decreasing the difference. The correction procedure continues until lock is achieved, after which the VCO will continue to track the incoming signal as long as it remains within the bandwidth and operational frequency range of the loop.
  • VCO voltage controlled oscillator
  • such a circuit may employ a digital phase/frequency detector which ensures that loop lock is achieved no matter how far off frequency the system initially is.
  • a disadvantage with such a detector is that, although it is power efficient at low frequencies of hundreds KHz or less, it consumes excessive power at higher frequencies of 10's of Mhz or more and is unsuitable for applications such as in the transmit circuits of portable radios, for example.
  • the use of a frequency divider placed in front of the phase/frequency detector reduces the power problems somewhat, but the frequency divider generates a series of frequencies at multiples of the phase comparison frequency.
  • the transmit frequency can leak into the frequency divider to produce frequencies which mix with multiples of the phase comparison frequency.
  • the resulting frequency is often within the bandwidth of the loop, thus resulting in unwanted frequency modulation or the generation of spurious outputs.
  • analog phase detectors typically mixers
  • an auxiliary sweeping circuit is used to drive the transmit VCO to the proper transmit frequency.
  • a tracking loop is a loop which when, locked, provides an output frequency which equals the input frequency.
  • this false frequency would be the image of the correct frequency.
  • a translation loop is a loop which, when locked, provides an output frequency which is offset from the input frequency by a constant difference over a range of operating frequencies.
  • the image frequency is equal to the correct frequency plus or minus twice the frequency of phase comparison (the constant offset frequency referred to above), depending on whether the input frequency is above or below the output frequency when the loop is correctly locked.
  • This type of false lock problem is solved by always sweeping in the proper direction.
  • sweep In the case of harmonic false locking (tracking loop) or where the image frequency (translation loop) is above the desired frequency, sweep always starts with the VCO at much less than the correct frequency, and the frequency increases with the sweep. This ensures that the VCO never sweeps through the false frequency, since it sweeps to the correct frequency first. The loop then locks and the sweep is stopped before the VCO reaches the false frequency.
  • the VCO is swept in the other direction.
  • the other type of false lock is much more subtle and much more damaging than the harmonic or image false lock discussed above, as it is harder to detect.
  • This type of false lock occurs when there is an interaction between the phase detector (which commonly has a sinusoidal or triangular phase characteristic in which the output polarity or slope alternates positive and negative for each 180 degrees of phase difference at the inputs), the VCO, and the entire loop filter's phase shift versus frequency characteristic.
  • the "entire loop filter” includes the “classical” or “intended design” loop filter or integrator and any phase shift resulting from intermediate frequency amplifiers and filters, if present, and all extra, possibly unwanted but unavoidable poles which cause additional phase shift.
  • the phase detector begins to generate a beat frequency equal to the difference of the two frequencies at its inputs.
  • This beat frequency appears as a ripple voltage at the phase detector output and frequency modulates the VCO.
  • the beat frequency approaches zero Hertz, or correct lock, the levels of the FM sidebands and their frequencies, which are offset from the VCO carrier frequency by multiples of the beat frequency, and the total phase shift around the loop create a situation where one of the FM sidebands is at the desired (correct) VCO frequency and is of sufficient amplitude that the loop locks on it.
  • the loop is in a stable oscillatory mode where the phase detector "thinks” it is properly locked (i.e., sweeping stops), but it is only locked on a sideband caused by the beat frequency.
  • the loop's output signal or the constant offset frequency in the case of translation loops
  • it may also participate in the problem to some extent. This is not usually of serious concern if the loop is properly designed to prevent false locks when no modulation is present .
  • This problem is exacerbated if the loop is made to have a very high gain (which is good for other reasons, such as a low steady-state phase error when the loop is locked), as the false lock only has to generate a very small DC component at the phase detector to hold the loop at the incorrect condition.
  • phase-locked loops with analog detectors functions such as initiating sweeping, false lock avoidance, lock detection and sweeping termination, and re-sweep (if needed) are provided by auxiliary circuitry such as lock detectors, sweep generators, discriminators, and microprocessors.
  • auxiliary circuitry such as lock detectors, sweep generators, discriminators, and microprocessors.
  • the present invention achieves the above objects, among others, by providing a sweep-to-lock circuit for a phase-locked loop, which circuit includes, in a preferred embodiment, a resistor to unbalance phase detector outputs to an operational amplifier to cause the voltage output of the operational amplifier to sweep and thus cause the frequency output of a voltage controlled oscillator to sweep.
  • Simple circuity detects correct lock and terminates sweeping; or, if lock is not achieved, causes the output of the operational amplifier to remain at a low level until the operational amplifier is reset and then permits resweep. Very little auxiliary circuitry is required.
  • FIG. 1 is a tracking loop in which the output frequency is equal to the input frequency over the design range of input frequencies when the loop is locked.
  • Figure 2 is a translation loop in which the output frequency is equal to the input frequency offset by the auxiliary input frequency over the design range of input and auxiliary frequencies.
  • block 1 represents the "classical” or “intended design” loop filter or integrator which usually contains some type of high gain DC amplifier such as an operational amplifier. Almost all practical phase-locked loops contain circuitry analogous to block 1. This filter is typically intended to control the dynamic properties of the loop including, but not limited to, stability, loop bandwidth transient response, and operating ("bias") points of the loop components such as the phase detector.
  • Blocks 2 and 3 if present, represent the additional phase shift added to the open loop transfer function ("open loop gain”) by other elements in the loop.
  • radio frequency bypass components may include radio frequency bypass components, the voltage control circuitry in the VCO, the load on the VCO (may cause "load pull” of frequency and/or phase), any additional noise or spurious signal filters, and the intermediate frequency amplifier/filter of translation loops.
  • the voltage control circuitry in the VCO may cause "load pull” of frequency and/or phase
  • any additional noise or spurious signal filters may include radio frequency bypass components, the voltage control circuitry in the VCO, the load on the VCO (may cause “load pull” of frequency and/or phase), any additional noise or spurious signal filters, and the intermediate frequency amplifier/filter of translation loops.
  • Figure 3 illustrates a sweep-to-lock circuit for a phase-locked loop filter, generally indicated by the reference numeral 10, which achieves the objects of the present invention and which is intended to be employed as block 1 in the phase-locked loops illustrated on figures 1 and 2.
  • Circuit 10 is intended for use with a double ended (differential) output phase detector; although, it may be used with a single ended output phase detector with minor modifications.
  • resistors 12, 14, 16, and 18, capacitors 20 and 22, and operational amplifier 24 comprise a conventional loop filter which is modified by the additional components to achieve the objects of the present invention.
  • resistors 12 and 14 are equal to each other as are resistors 16 and 18.
  • capacitors 20 and 22 are usually equal to each other.
  • Circuit 10 results in a classic high gain loop and is an integrator having a high frequency zero to prevent excessive phase shift at higher frequencies which can (and usually does) cause the loop to oscillate.
  • the components controlling the "sweep-to-lock" function are the conventional loop filter described above (it does double duty, as resistors 12 and 14 and capacitors 20 and 22 partially determine the rate of sweep) and resistors 30, 32, 34, 36, 38, and 40, a capacitor 42, a transistor 44, a diode 46, and a comparator 48.
  • Resistor 30 is connected to the inverting input of operational amplifier 24.
  • Resistors 32 and 34 are connected in series between the output of operational amplifier 24 and ground, with the inverting input of comparator 48 being connected between the resistors.
  • One end of resistor 40 is connected to the output of comparator 48 and the other end of that resistor is connected to one end of resistor 38, the other end of the later being connected to the base of transistor 44.
  • the collector of transistor 44 is connected to the inverting input of operational amplifier 24.
  • Capacitor 42 is connected between ground and the junction of resistors 38 and 40.
  • Resistor 36 is connected between that junction and the emitter of transistor 44 and diode 46 is connected to conduct current from that junction to the output of comparator 48.
  • components 36, 38, 40, 42, and 46 comprise a "ratcheting" circuit, generally indicated by the reference numeral 50, the function of which is described below.
  • a reference voltage is supplied to comparator 48 to determine the trip point thereof. This voltage may be developed in one of several conventional ways depending on the actual application.
  • Resistor 30 is used to unbalance the inputs to the loop filter to cause a positive going sweep at the output of operational amplifier 24.
  • the configuration shown assumes that the phase detector is a differential output device having some finite impedance and zero DC differential voltage at "zero phase error".
  • the invention is not limited by this assumption, however, as any method which allows for the unbalancing of the inputs to the loop filter while allowing the phase detector to re-balance those inputs upon lock may be used. Such methods include, but are not limited to, the use of voltage dividers, offsetting diode drops, and/or auxiliary voltages applied to one or both of the loop filter inputs.
  • Transistor 44 is used to reset the sweep. If it is on, the non-inverting input of the loop integrator is pulled high. This causes the output of the integrator to rapidly slew toward ground (the reset condition in this case).
  • the loop integrator input unbalancing circuit (resistor 30 in the case of figure 3) is permanently in the circuit while transistor 44 is switched on and off as required. When transistor 44 is off, the sweep direction is positive, but, when the transistor is on, the sweep direction is negative going and much faster, due to the connection of the inverting input of operational amplifier 24 to a relatively large positive voltage. This rapid negative going sweep is used to reset the sweep-to-lock circuit.
  • Other devices may be used to perform the function of transistor 44 including, but not limited to, field effect transistors, semiconductor controlled rectifiers, and relays. The object is to be able to rapidly reset the sweep.
  • Comparator 48 compares the output voltage to a reference voltage.
  • Resistors 32 and 34 may be used to reduce the output voltage so that, at correct lock, the relationship of the output voltage to the reference voltage may be set as required.
  • Various other circuits active or passive may be placed in either or both lines (to the inverting and non-inverting inputs of comparator 48) to maintain any desired relationship of the reference and output voltages at correct lock.
  • comparator 48 When the voltage at the inverting input of comparator 48 is less than the voltage at the non-inverting input, the comparator output will be high (near +VCC) and transistor 44 will be held off. When the reverse situation is present at the inputs, the output of comparator 48 will be low (near ground) and the transistor will be turned on, thus resetting the sweep.
  • Examples of the treatment of the reference voltage include, but are not limited to, the following:
  • circuit 50 is needed to prevent the sweep circuit from oscillating as follows: When the output of comparator 48 is low, transistor 44 is on and the loop rapidly resets. Diode 46 discharges capacitor 42 rapidly through its low “on” resistance, and resistors 36, 38, and 40 are chosen so as to maintain this condition. As soon as the sweep voltage (output voltage to VCO) falls below the trip point of comparator 48, the comparator's output goes high. Diode 46 is now reverse biased, thus capacitor 42 must charge through resistors 36, 38, and 40.
  • transistor 44 may be kept on until the output voltage sweeps to essentially zero volts. If the ratcheting circuit were not present (if the output of comparator 48 were connected to the transistor base through simple resistive network with no capacitor and diode), as soon as the sweep voltage fell below the trip point of the comparator, transistor 44 would be turned off and normal (positive) sweep would occur up to the point at which resweep would be initiated. Since the sweep would never be fully reset, the sweep circuit would oscillate around a point near the trip point of comparator 48 and the loop would not be brought to the correct lock, but, rather, would be "hung up" at an unlocked condition.
  • diode 46 must also be added to ensure proper reset of the sweep.
  • Diode 46 along with resistor 40 act as a "leaky flap valve” by allowing capacitor 42 to be rapidly discharged when comparator 48 goes low, but slowly charged when comparator 48 goes high. This provides a "ratcheting” action to ensure that transistor 44 remains on long enough to fully reset the sweep.
  • resistors 36, 38, and 40 usually perform a secondary function of preventing transistor breakdown (when transistor 44 is off) and limiting base current drive (when transistor 44 is on). A specific application of this circuit may only need one or two resistors depending on the actual components, supply voltages, etc. employed.
  • ratcheting circuit 50 The action of ratcheting circuit 50 is mainly to ensure that sweep is fully reset. Other, more complicated circuits (such as one-shot multivibrators) may be used to perform this function, but, in any case, the sweep should be fully reset (or at least brought below the point of correct lock so it can sweep up to correct lock) on each sweep cycle.
  • Other, more complicated circuits such as one-shot multivibrators
  • the offset due to resistor 30 (or through other means 85 indicated above) is set so that, at any of the false lock frequencies, there is not enough DC signal generated at the inputs to the loop integrator to overcome the designed in offset, thus the circuit continues sweeping; but, at the correct lock condition, the DC signal generated by the phase detector is more than enough to overcome the offset and the loop automatically locks. What actually happens is that the sweep brings the loop to a condition where the loop is within the lock-in range of the loop and loop locks up.
  • the lock-in range of a phase-locked loop is that range of frequencies, above and below the correct lock frequency, where the absolute value of the frequency difference (actual minus correct) is less than the loop's bandwidth. In this case, the loop will lock up almost instantaneously without skipping cycles (no beat frequency present at the output of the phase detector).
  • the action of the offset voltage causes the loop to operate, when locked, with a steady state phase error sufficient to overcome the offset.
  • the offset required to prevent false lock results in a small (usually less than 20 degrees) steady state phase error. If any frequency modulation is present (for example, in a translation loop which adds the modulation to the output frequency by using a modulated auxiliary frequency), this causes slight perturbations around the steady state point, especially in high gain loops.
  • a mixer type phase detector requires the "zero phase error" condition to exist when the inputs to the phase detector are actually in quadrature (90 degrees out of phase). All references to phase error when discussing this type of detector are with respect to this perfect quadrature condition. With other types of phase detectors, the "zero phase error" condition may or may not be when the inputs to the phase detector are in phase coincidence; however, this is not central to the invention.
  • the "auto-sweep-to-lock" action of the circuit of Figure 3 is as follows: assume that the output voltage to VCO is at a point which is below correct lock. Offset caused by the offset circuit (resistor 30) causes the loop integrator to sweep the output voltage to the correct lock (avoiding false locks) as described above. If the output voltage is initially above correct lock, the voltage continues to sweep until comparator 48 senses the oversweep condition and pulses transistor 44, thus resetting and reinitiating the sweep. In all cases, the offset causes sweep until the correct lock is obtained and the offset is overcome. The sweep then stops and the loop is locked. The entire process is completely automatic. One design which has been reduced to practice takes less than 20 milliseconds to achieve correct lock from any starting condition.
  • Figure 4 illustrates the output waveforms of loop integrator 24 and comparator 48 during sweeping and reset as described above.
  • the action of ratcheting circuit 50 is also further illustrated here where it can be seen that the ratcheting circuit holds transistor 44 on for a period of time after the output of comparator 48 drops to zero, so that the output of operational amplifier 24 can drop to zero before resweeping is initiated.
  • Typical figures for an actual circuit are a sweep cycle of 20 milliseconds total with a reset time of 5 milliseconds (transistor 44 is on during reset).

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EP19910203333 1990-12-21 1991-12-18 Automatic sweep-to-lock circuit for a phase-locked loop Withdrawn EP0492718A3 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/631,522 US5091702A (en) 1990-12-21 1990-12-21 Automatic sweep-to-lock circuit for a phase-locked loop
US631522 1990-12-21

Publications (2)

Publication Number Publication Date
EP0492718A2 true EP0492718A2 (fr) 1992-07-01
EP0492718A3 EP0492718A3 (en) 1992-11-25

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EP19910203333 Withdrawn EP0492718A3 (en) 1990-12-21 1991-12-18 Automatic sweep-to-lock circuit for a phase-locked loop

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US (1) US5091702A (fr)
EP (1) EP0492718A3 (fr)
JP (1) JPH05160725A (fr)
CA (1) CA2058005A1 (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1059730A3 (fr) * 1999-06-11 2003-11-05 Philips Intellectual Property & Standards GmbH Dispositif de compensation du courant de décalage d'un détecteur de phase

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5210509A (en) * 1992-05-29 1993-05-11 Unisys Corporation Dual loop phase locked circuit with sweep generator and compensation for drift
US5394115A (en) * 1994-04-01 1995-02-28 Conifer Corporation Automatic sweep acquisition circuit for a phase-locked-loop
US6064273A (en) * 1998-06-04 2000-05-16 Adc Telecommunications Phase-locked loop having filter with wide and narrow bandwidth modes
US6766154B2 (en) * 2001-03-07 2004-07-20 Northrop Grumman Corporation Fast settling fine stepping phase locked loops
EP3276538B1 (fr) * 2016-07-25 2020-01-01 STMicroelectronics International N.V. Circuit de génération de signal de support pour un dispositif de transpondeur d'identification par radiofréquence et procédé pour générer un signal de support

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2368178A1 (fr) * 1976-10-15 1978-05-12 Thomson Csf Circuit de commande automatique de frequence
US4240076A (en) * 1978-06-05 1980-12-16 Raytheon Company Starting circuit for automatic frequency control arrangement

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1059730A3 (fr) * 1999-06-11 2003-11-05 Philips Intellectual Property & Standards GmbH Dispositif de compensation du courant de décalage d'un détecteur de phase

Also Published As

Publication number Publication date
EP0492718A3 (en) 1992-11-25
CA2058005A1 (fr) 1992-06-22
JPH05160725A (ja) 1993-06-25
US5091702A (en) 1992-02-25

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