EP0499657B1 - Régulateur shunt intégrable - Google Patents

Régulateur shunt intégrable Download PDF

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Publication number
EP0499657B1
EP0499657B1 EP91102283A EP91102283A EP0499657B1 EP 0499657 B1 EP0499657 B1 EP 0499657B1 EP 91102283 A EP91102283 A EP 91102283A EP 91102283 A EP91102283 A EP 91102283A EP 0499657 B1 EP0499657 B1 EP 0499657B1
Authority
EP
European Patent Office
Prior art keywords
transistor
shunt regulator
supply voltage
transistors
terminals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP91102283A
Other languages
German (de)
English (en)
Other versions
EP0499657A1 (fr
Inventor
Günter Dipl.-Ing. Donig
Bruno Dipl.-Ing. Scheckel
Karl-Reinhard Dipl.-Ing. Schön
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Priority to EP91102283A priority Critical patent/EP0499657B1/fr
Priority to DE59105528T priority patent/DE59105528D1/de
Priority to ES91102283T priority patent/ES2071849T3/es
Priority to US07/837,278 priority patent/US5229708A/en
Publication of EP0499657A1 publication Critical patent/EP0499657A1/fr
Application granted granted Critical
Publication of EP0499657B1 publication Critical patent/EP0499657B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current 
    • G05F1/46Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/613Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in parallel with the load as final control devices
    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F3/00Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
    • G05F3/02Regulating voltage or current
    • G05F3/08Regulating voltage or current wherein the variable is DC
    • G05F3/10Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics
    • G05F3/16Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices
    • G05F3/20Regulating voltage or current wherein the variable is DC using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
    • G05F3/30Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities

Definitions

  • the invention relates to an integrable shunt regulator with a controllable semiconductor component, the load path of which is connected between the poles of a supply voltage source and the control input of which is connected to the output of a differential amplifier.
  • Such a shunt regulator serves as a voltage regulator and is e.g. from GB-A-2226664 also known as a so-called parallel regulator.
  • the load path of a semiconductor device z. B. a power transistor lies between the poles of the supply voltage to be regulated.
  • the power transistor is controlled by an operational amplifier, which in turn is fed by a reference voltage source.
  • a so-called bandgap reference usually serves as the reference voltage. This is e.g. B. from semiconductor circuit technology, Tietze Schenk, 8th edition 1986, page 534 ff known.
  • a shunt controller having a bandgap reference and a parallel controller is known from the Linear Circuits Data Book by Texas Instruments, 1984 on pp. 6-99 ff.
  • This adjustable shunt regulator has three connections, the anode and cathode of the shunt regulator being connected to the poles of a supply voltage and a reference voltage, for example, having to be supplied to the reference input via a voltage divider.
  • the shunt controller shown in the circuit on p. 6-99 has a relatively complicated structure and has a regulated bandgap reference, the voltage value of which can be adjusted from the outside, and an operational amplifier coupled to it. This solution has the disadvantage of an increased tendency to oscillate due to the two coupled operational amplifiers.
  • a series regulator is usually connected downstream of the shunt regulator for precise regulation of the operating voltage.
  • the shunt controller is only used for pre-stabilization.
  • the object of the invention is therefore to provide an integrable shunt regulator which keeps the output voltage in a defined range with as little effort as possible.
  • the advantage of the shunt regulator according to the invention is that it has only two supply voltage connections without a control or reference input.
  • the reference voltage is generated by means of a bandgap reference in such a way that the output variable of the control amplifier is the voltage to be controlled itself.
  • the shunt regulator shown in FIG. 1 has two connection terminals 1, 2 to which the supply voltage source can be connected.
  • the positive pole of the supply voltage source is at connection 1 and the negative pole of the supply voltage source at connection 2.
  • a semiconductor component for. B. a MOSFET 3 is provided, the load path between the terminals 1 and 2 is connected.
  • an operational amplifier 9 is used, the output of which is connected to the gate of the MOSFET 3.
  • the operational amplifier has a positive and a negative input.
  • two NPN transistors 4, 5 are provided. The base connections and the collector connections of the two transistors 4, 5 are connected to one another and connected to the input terminal 1.
  • the emitter connection of the first transistor 4 is connected to the second connection 2 via a resistor 6.
  • the emitter connection of the first transistor 4 is connected to the negative input 20 of the operational amplifier 9.
  • the emitter connection of the second transistor 5 is connected to the connection 2 via the series connection of a second and third resistor 7, 8.
  • the series connection of the two resistors 7, 8 has a connection node which is connected to the positive input 19 of the operational amplifier 9.
  • the bandgap reference is formed by transistors 4, 5 and resistors 6, 7, 8.
  • the output voltage of this bandgap reference is fed to the operational amplifier 9, which in turn controls the MOSFET 3.
  • the regulation of the differential output voltage of the bandgap reference is thus connected to the supply voltage regulation.
  • the value of the output voltage can be selected by selecting the resistance values of resistors 6 and 8. If the output voltage at terminals 1 and 2 corresponds to the value defined by resistors 6 and 8, the input reference voltage of the operational amplifier becomes 0.
  • a disadvantage of the bandgap reference shown in FIG. 1 is that the temperature response of the output voltage at terminals 1 and 2 deteriorates to the same extent that the output voltage deviates from the bandgap reference voltage.
  • the operating point setting of the operational amplifier 9 is difficult because of the small threshold voltage of the bipolar transistors.
  • FIG. 2 shows an improvement of the bandgap reference circuit shown in FIG. 1.
  • the band gap reference shown in FIG. 2 has four additional transistors 10, 11, 12, 13 in addition to that shown in FIG.
  • the emitter of the first additional transistor 10 is connected to the two base connections of the first and second transistors 4, 5.
  • the emitter of the second additional transistor 11 is connected to the base of the first additional transistor 10, the emitter of the third additional transistor 12 to the base of the second additional transistor 11 and the emitter of the fourth additional transistor 13 to the base of the third additional transistor 12.
  • the collectors of all four additional transistors 10, 11, 12, 13 are connected to the collectors of the first and second transistors 4, 5. Furthermore, the base of the fourth additional transistor 13 is connected to its collector.
  • a fourth, fifth and sixth resistor are also provided, the fourth resistor 14 between the emitter of the second additional transistor 11 and the emitter of the first additional transistor 10, the second resistor between the emitter of the third additional transistor 12 and the emitter of the first additional transistor 10 and the third resistor 16 is connected between the emitter of the fourth additional transistor 13 and the emitter of the first additional transistor 10.
  • a seventh and eighth resistor 17 and 18 between the connected base connections of the first and second transistors 4, 5 and the connection 2.
  • the other components shown in FIG. 2 correspond 1 and have the same designation. 19 and 20 in turn denote the connections which lead to the two inputs of the operational amplifier 9 from FIG. 1.
  • the differential input voltage of the subsequent operational amplifier 9 is favorably reduced by the potential present at terminal 1 shifted, on the other hand the point of complete temperature compensation is shifted by approx. 5 times.
  • the bandgap reference voltage here has a value of approximately 6V. Deviations from this are less significant.
  • An expansion as shown in FIG. 2 is not limited to four transistors, but can be enlarged or reduced as desired within a reasonable range.
  • Essential to the invention is the increase in the bandgap reference voltage by means of n transistors connected in series, the collectors of which are connected to the positive supply potential. The output voltage is then temperature compensated at n + 1 times the bandgap reference voltage.
  • resistors 17 and 18 were chosen in FIG. These can be replaced by one or possibly several resistors.
  • the circuit including the bipolar npn transistors can be implemented particularly in CMOS technology with an n-substrate.
  • the collector connections of the bipolar npn transistors are formed by the common substrate. This is possible because only bipolar transistors are used that are connected as emitter followers. Such transistors are also referred to as parasitic "substrate npn transistors".
  • the circuit shown is particularly suitable for transportable data carriers, for. B. so-called chip cards and chip keys, which do not have their own power supply and whose energy is supplied by means of two coils.

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Control Of Electrical Variables (AREA)

Claims (4)

  1. Régulateur shunt intégrable comportant un composant à semiconducteurs commandable (3), dont la section de charge est branchée entre les bornes (1,2) d'une source de tension d'alimentation et dont l'entrée de commande est reliée à la sortie d'un amplificateur différentiel (9), caractérisé par le fait que
    - il est prévu des premier et second transistors (4,5), dont les bornes de base et les bornes de collecteur sont reliées entre elles et à une borne (1) de la source de tension d'alimentation,
    - trois résistances (6,7,8) sont prévues,
    - la borne d'émetteur du premier transistor (4) est reliée, d'une part, par l'intermédiaire d'une première résistance, (6) à l'autre borne (2) de la source de tension d'alimentation et, d'autre part, à la première entrée (20) de l'amplificateur différentiel (9),
    - la borne d'émetteur du second transistor (5) est reliée, par l'intermédiaire d'un circuit série formé de seconde et troisième résistances (7,8), à l'autre borne (2) de la source de tension d'alimentation,
    - le circuit série des deux résistances (7,8) possède un noeud de liaison, qui est relié à la seconde entrée (19) de l'amplificateur différentiel (9).
  2. Régulateur Shunt intégrable suivant la revendication 1, caractérisé par le fait que
    - il est prévu n (n ≧ 1) autres transistors (10,11,12,13), qui sont branchés entre les bornes de base et les bornes de collecteur des premier et second transistors (4,5),
    - la borne d'émetteur du premier des autres transistors (10) est reliée aux bornes de base des premier et second transistors (4,5),
    - la borne d'émetteur du (n+1)-ème des autres transistors (11,12,13) est reliée respectivement, d'une part, à la borne de base du n-ème des autres transistors (10,11,12) et d'autre part, par l'intermédiaire respectivement d'une résistance (14,15,16), aux bornes de base des premier et second transistors (4,5),
    - la borne de base du dernier des autres transistors (13) est reliée à sa borne de collecteur,
    - des bornes de collecteur des n autres transistors (10,11, 12,13) sont reliées aux bornes de collecteur des premier et second transistors (4,5),
    - une résistance (17,18) est branchée entre les bornes de base des premier et second transistors (4,5) et l'autre borne (2) de la source de tension d'alimentation.
  3. Régulateur Shunt intégrable suivant la revendication 1 ou 2, caractérisé par le fait que le régulateur shunt est agencé selon la technologie CMOS, les transistors bipolaires étant formés par des structures parasites.
  4. Régulateur Shunt intégrable suivant l'une des revendications précédentes, caractérisé par le fait que le régulateur shunt est prévu dans une carte à puce ou dans une clé à puce.
EP91102283A 1991-02-18 1991-02-18 Régulateur shunt intégrable Expired - Lifetime EP0499657B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP91102283A EP0499657B1 (fr) 1991-02-18 1991-02-18 Régulateur shunt intégrable
DE59105528T DE59105528D1 (de) 1991-02-18 1991-02-18 Integrierbarer Shunt-Regler.
ES91102283T ES2071849T3 (es) 1991-02-18 1991-02-18 Regulador shunt integrable.
US07/837,278 US5229708A (en) 1991-02-18 1992-02-18 Integrable shunt regulator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP91102283A EP0499657B1 (fr) 1991-02-18 1991-02-18 Régulateur shunt intégrable

Publications (2)

Publication Number Publication Date
EP0499657A1 EP0499657A1 (fr) 1992-08-26
EP0499657B1 true EP0499657B1 (fr) 1995-05-17

Family

ID=8206418

Family Applications (1)

Application Number Title Priority Date Filing Date
EP91102283A Expired - Lifetime EP0499657B1 (fr) 1991-02-18 1991-02-18 Régulateur shunt intégrable

Country Status (4)

Country Link
US (1) US5229708A (fr)
EP (1) EP0499657B1 (fr)
DE (1) DE59105528D1 (fr)
ES (1) ES2071849T3 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB9417267D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Current generator circuit
DE4439707A1 (de) * 1994-11-05 1996-05-09 Bosch Gmbh Robert Spannungsreferenz mit Prüfung und Eigenkalibrierung
US5701071A (en) * 1995-08-21 1997-12-23 Fujitsu Limited Systems for controlling power consumption in integrated circuits
US5949212A (en) * 1997-06-05 1999-09-07 The Boeing Company Integrated solar cell array and power regulator
JP3488054B2 (ja) * 1997-09-12 2004-01-19 Necエレクトロニクス株式会社 液晶駆動用装置
US6134130A (en) * 1999-07-19 2000-10-17 Motorola, Inc. Power reception circuits for a device receiving an AC power signal
JP2001101364A (ja) * 1999-10-01 2001-04-13 Fujitsu Ltd 非接触icカード用lsi
US6259324B1 (en) * 2000-06-23 2001-07-10 International Business Machines Corporation Active bias network circuit for radio frequency amplifier
WO2004107077A1 (fr) * 2003-05-28 2004-12-09 Koninklijke Philips Electronics N.V. Circuit destine a un support d'information et comportant des moyens de generation de parametre de reference incluant des moyens de limitation de tension d'alimentation
KR100812086B1 (ko) * 2006-11-30 2008-03-07 동부일렉트로닉스 주식회사 반도체 소자의 전압조절장치
US7969127B1 (en) 2008-04-25 2011-06-28 National Semiconductor Corporation Start-up circuit for a shunt regulator

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3617859A (en) * 1970-03-23 1971-11-02 Nat Semiconductor Corp Electrical regulator apparatus including a zero temperature coefficient voltage reference circuit
PL71890B1 (fr) * 1972-10-02 1974-06-29
US4088941A (en) * 1976-10-05 1978-05-09 Rca Corporation Voltage reference circuits
US4160201A (en) * 1978-06-08 1979-07-03 Rca Corporation Voltage regulators
US4743833A (en) * 1987-04-03 1988-05-10 Cross Technology, Inc. Voltage regulator
JPH03502380A (ja) * 1988-02-04 1991-05-30 マジエラン・コーポレーシヨン・(オーストラリア)・プロプライエタリイ・リミテツド 分路調整器
GB2226664B (en) * 1988-11-26 1992-09-09 Motorola Inc Shunt regulators
US5103160A (en) * 1991-04-25 1992-04-07 Hughes Aircraft Company Shunt regulator with tunnel oxide reference

Also Published As

Publication number Publication date
US5229708A (en) 1993-07-20
EP0499657A1 (fr) 1992-08-26
ES2071849T3 (es) 1995-07-01
DE59105528D1 (de) 1995-06-22

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