EP0565305B1 - Transmission d'un signal d'horloge sur un canal de données asynchrones - Google Patents

Transmission d'un signal d'horloge sur un canal de données asynchrones Download PDF

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Publication number
EP0565305B1
EP0565305B1 EP93302571A EP93302571A EP0565305B1 EP 0565305 B1 EP0565305 B1 EP 0565305B1 EP 93302571 A EP93302571 A EP 93302571A EP 93302571 A EP93302571 A EP 93302571A EP 0565305 B1 EP0565305 B1 EP 0565305B1
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EP
European Patent Office
Prior art keywords
clock signal
transmitter
input
rate
data
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Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
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EP93302571A
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German (de)
English (en)
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EP0565305A1 (fr
Inventor
William Keith Honea
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AT&T Inc
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AT&T Inc
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/062—Synchronisation of signals having the same nominal but fluctuating bit rates, e.g. using buffers
    • H04J3/0632—Synchronisation of packets and cells, e.g. transmission of voice via a packet network, circuit emulation service [CES]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/20—Servers specifically adapted for the distribution of content, e.g. VOD servers; Operations thereof
    • H04N21/23—Processing of content or additional data; Elementary server operations; Server middleware
    • H04N21/242—Synchronisation processes, e.g. processing of PCR [Programme Clock References]
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/40—Client devices specifically adapted for the reception of or interaction with content, e.g. set-top-box [STB]; Operations thereof
    • H04N21/43—Processing of content or additional data, e.g. demultiplexing additional data from a digital video stream; Elementary client operations, e.g. monitoring of home network or synchronising decoder's clock; Client middleware
    • H04N21/4302—Content synchronisation processes, e.g. decoder synchronisation
    • H04N21/4305—Synchronising client clock from received content stream, e.g. locking decoder clock with encoder clock, extraction of the PCR packets

Definitions

  • This invention relates to data transmission and, more particularly, to the transmission of synchronous clock signals over an asynchronous data channel.
  • Synchronization is needed to enable clock signals at the receiver to coincide with the center of the received data pulses, thus assuring that data bits are not added, lost or misinterpreted during data transmission.
  • the transmission of digital video data over a digital communications channel usually requires that the communications channel be synchronous to the video data rate for complete recovery of the video data and its associated clock at the receiver.
  • This requirement is due to the circuit (synchronous) rather than packet (asynchronous) nature of full motion video data.
  • the video data can be packetized and sent over an asynchronous channel using elastic stores at both the transmitter and receiver, the video source A/D clock must still be synchronized to the receiver D/A converter clock to ensure error-free video transmission.
  • Prior art methods of video data transmission require 1) synchronization to the communications channel (synchronous transmission), 2) sending the clock information over a separate synchronous channel, 3) synchronizing transmitter and receiver to a third (master) clock source, or 4) accepting video data errors at the receiver as a result of the differences in transmit and receive clocks.
  • the communication channel does not operate synchronously with the video data source, the resulting solutions add complexity and expense to providing video data transmission.
  • a transmitter apparatus transmits the logic state of an input data (e.g., video) clock signal, which has been divided-down by a predetermined integer N (N ⁇ 2), along with data over an asynchronous communication channel.
  • the integer N is selected so that the resulting "sub-rate" clock signal is at a frequency is less than or equal to one-half of the data word transmission rate of the asynchronous communication channel.
  • the asynchronous communication channel also has an average data word transmission rate which is greater than the input data rate.
  • the sub-rate clock signal is received at the receiver and the input data clock signal is regenerated.
  • the integer N is selected to minimize jitter caused by the asynchronous communication channel and to enable the input-data clock signal to be regenerated using practical bandpass filtering and phase lock loop operation.
  • Elastic stores in the transmitter and receiver apparatus accommodate the maximum delay between asynchronous data transmissions over the asynchronous communication channel.
  • each item or block of each figure has a reference designation associated therewith, the first number of which refers to the figure in which that item is first located (e.g., 110 is located in FIG. 1).
  • FIG. 1 shows a block diagram of the transmitter unit 100 of a transmission system. From the diagram, it is seen that there are two independent clocks, video sampling clock 102 with frequency f V (video sample word data rate) and transmit (TX) data word clock 110 with frequency f D . The only required relationship between the two clocks is that f D > f V .
  • the present invention thus enables the synchronization of data signals between a transmitter source and a receiver location over a data channel which operates asynchronously thereto.
  • the clock signal of the input data signal (f D ) is divided down to a frequency f D /N such that the transmit data word or average data packet rate (f D ) would be equal to or greater than the Nyquist rate (2f V /N).
  • the Nyquist rate is satisfied as long as N ⁇ 2.
  • Analog video signal 101 is sampled by video clock 102 in the analog to digital (A/D) converter 103 and generates a resulting 8-bit digital signal, on bus 104, having a data rate of f V words per second.
  • This digitized video information, on bus 104 is stored in the input side D_IN of elastic store 105 which operates as a FIFO (First In First Out) buffer.
  • the same video clock 102 used to sample the analog signal is also used to write the digitized video into the elastic store 105.
  • the out clock lead 106 clocks data out of the elastic store 105, via D_OUT when serializer/transmitter 107 is ready for a new word of data, and the elastic store 105 is not empty.
  • the ready signal 108 indicates when data is available in elastic store 105 to be transmitted.
  • serializer/transmitter 107 Since the frequency of transmit data word clock 110 (f D ) is greater than the frequency of the video clock 102 (f V ), serializer/transmitter 107 output data transmission rate is larger than the data rate of the outgoing digitized video on bus 104. Therefore, one or more data words will be periodically serialized containing "idle code" or no video information. This idle code information is encoded into the protocol at the serializer/transmitter 107 to enable the receiver to distinguish between data words and unused words.
  • This clock bit inserted into adjacent video data words represents the state of the video sampling clock 102, divided down, by divide-by-N circuit 113, to a lower rate clock having a frequency of f V /N.
  • the logic state of this "sub-rate" clock (0 or 1) is inserted together with the digitized video data words as part of the asynchronous serial data words transmitted by serializer/transmitter 107 over communication channel 120.
  • FIG. 2 shows a block diagram of the receiver unit 200 of a transmission system.
  • the serial data stream received over communication channel 120 from transmitter 100 is clocked, by receiver (RX) clock 220, into receiver/parallel converter 201.
  • the receiver (RX) clock 220 also clocks a 9-bit parallel data stream onto bus 202.
  • Receiver (RX) clock 220 is synchronized to transmitter (TX) clock 110 in accordance with the clock synchronization technique associated with the transmission system (FIG. 1 and 2), whose operation is not relevant to the present invention.
  • the read (RD) strobe, 203 of receiver/parallel converter 201 indicates the presence of a new data word and is used to load the 8 bits of video data on bus 204 into the input of the elastic store 220.
  • Elastic store 220 operates as a FIFO, in a manner similar to elastic store 105 of transmitter 100.
  • the 9th bit, lead 205, representing the state of the sampled sub-rate clock is routed to bandpass filter 206 with a center frequency of f V /N.
  • the purpose of the bandpass filter 206 is to remove most of the jitter from the received sampled sub-rate clock caused by the uncertainty between the time of transitions of the sub-rate clock at the transmitter (which is based on the video clock 102), and the time a data word is transmitted (based on the transmit data clock 110).
  • the output 207 of bandpass filter 206 is a sine wave signal due to the stripping of higher harmonics by bandpass filter 206.
  • the limiter 208 provides a de-jittered sub-rate clock signal, 209, to the phase locked loop 210 which recreates the video clock 102 by multiplying the sub-rate clock up by a factor of N.
  • the phase lock loop 210 includes a voltage controlled oscillator (VCO) 211 which generates the local video clock signal f V on lead 221.
  • the output of oscillator 211 is divided down by divider circuit 212 whose output 213 has the frequency of f V divided by N.
  • a switching phase comparator 214 compares the phase of the recovered f V /N signal on lead 209 with the reference f V /N signal on lead 213.
  • the output of comparator 214 passes through a low-pass filter 215 for removal of switching frequency components generated by the switching phase comparator 214.
  • the output of the low-pass filter 215 is then fed to the control input of VCO 211 for locking the phase of the recovered video clock signal 221 to the video clock signal generated by transmitter 100.
  • the recovered video clock 221 is used to clock data from elastic store 220, via bus 224, into the digital to analog converter (D/A) 225.
  • the D/A unit 225 is clocked by recovered video clock 221 to provide an analog video output on lead 226.
  • the present method of transmitting a synchronous clock asynchronously over communication channel 120 is independent of the transmission media used.
  • the transmission can take place over fiber, wired, or wireless communication channels.
  • the type of transmission system used to deliver the data words from the transmitter to the receiver can be a synchronous (constant rate) transmission system, or an asynchronous (packet) system.
  • the only restriction in a constant rate system is that the transmission data rate ( f D ) be greater than the video data rate (f V ).
  • the elastic store may be as small as one word.
  • the restriction is that the average data word transfer rate be greater than the video data rate f V .
  • the elastic store (105 and 220) size used in such a system would be determined depending on the maximum interval between packet bursts and the size of the packets. The minimum elastic store size would have to accommodate input data from the A/D converter 103 over the maximum time period between packet transmissions.
  • the choice of the division factor N is a design implementation choice which is dependent on several factors. In general, the larger the value of N, the less jitter will be realized in the recovered video clock. The disadvantage of larger values of N is that the bandpass filter at the receiver becomes more difficult to realize, and the acquisition time of the phase lock loop increases.
  • An illustrative example of a system where this method of clock transmission might be used is in transmitting 27 MByte (million word) video data between a transmitter unit 100 and receiver unit 200 over a serial communication channel or link operating at 500 Mb/s (million bits per second).
  • the 27 MHz video clock is completely asynchronous to the 500 MHz (million hertz) transmission channel clock. If N is chosen to be 256, the frequency of the transmitted sub-rate clock 111 is approximately 105 KHz, so the bandpass filter 206 at the receiver 200 is centered on 105 KHz, and the phase lock loop 210 synchronizes the recovered video clock of 27 MHz divided by 256 to the 105 KHz signal appearing on bit 9 of the received word.
  • the transmission system takes care of the synchronization and transmission of data at the 500 MHz rate over channel 120, independent of the 27 MHz data.
  • the disclosed clock adjustment method and apparatus enables a user to transmit data at its own synchronous data rate over a higher bit rate independently asynchronous communication system or packet communication system.
  • the jitter of the recovered clock signal could be much worse than with a continuous transmission (circuit) system which operates asynchronous to the input (source) clock signal.
  • an input clock transition would, in the worst case, be detected in adjacent data words transmitted by the system.
  • the input clock transition would, in the worst case, be detected in adjacent data words which themselves are in two different data packets.
  • the circuit system there is a regular jitter which is equal to plus or minus about one half of the system data word time period.
  • the jitter time can be plus or minus about one half of the sum of the system data word time period and maximum delay time between adjacent data packets.
  • this jitter is reduced substantially by filtering at the receiver.
  • clock information is transmitted as an extra bit of data, little channel capacity is utilized for clock information transmission resulting in efficient channel capacity utilization. Thus, no separate data channel is needed to send the clock signal to the receiver.
  • the commercial benefits of the present invention are the savings in cost of complexity by sending clock information along with the data, and eliminating the requirement that the communications channel be synchronous with the data source. This also gives greater flexibility and fewer restrictions when designing a data transmission system, allowing for a less expensive and less accurate timing mechanism to be utilized without increasing data errors.
  • Implementation of the disclosed apparatus can utilize one or more well-known standard integrated circuits to provide the disclosed functions. Moreover, the disclosed apparatus can be implemented as a custom integrated circuit or as a part of a microprocessor controlled system.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Multimedia (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Computer Hardware Design (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Dc Digital Transmission (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Claims (12)

  1. Appareil émetteur pour communiquer un mot de données numériques d'entrée et un signal d'horloge d'entrée sur un canal de communication à un débit de transmission de mots de données qui fonctionne de manière asynchrone par rapport audit signal d'horloge d'entrée, ledit émetteur comprenant
    un moyen pour diviser (113) ledit signal d'horloge d'entrée par un nombre entier prédéterminé pour obtenir un signal de fréquence d'horloge de débit secondaire qui est inférieur ou égal à la moitié du débit de transmission de mots de données dudit émetteur et étant CARACTERISE PAR
    un moyen (103, 105) pour générer ledit mot de données d'entrée à partir d'un signal analogique d'entrée échantillonné par ledit signal d'horloge d'entrée, ledit signal d'horloge d'entrée étant dérivé indépendamment dudit signal analogique d'entrée, et
    un moyen pour combiner (111, 107) un échantillon d'état logique dudit signal d'horloge de débit secondaire audit mot de données d'entrée pour former chaque mot de données à transmettre dans un format de données par paquets à partir dudit émetteur.
  2. Emetteur selon la revendication 1, dans lequel un débit de transmission de mots de données moyen est supérieur à un débit de génération de mots de données d'entrée moyen.
  3. Emetteur selon la revendication 1, dans lequel ledit signal d'horloge de débit secondaire est un Ne de la fréquence dudit signal d'horloge d'entrée, où N est supérieur ou égal à 2.
  4. Emetteur selon la revendication 1, dans lequel ledit signal d'horloge de débit secondaire est un Ne de la fréquence dudit signal d'horloge d'entrée, où N est choisi de telle sorte que le rapport du débit de transmission de mots de données dudit émetteur sur la fréquence du signal d'horloge de débit secondaire entraíne une gigue d'horloge de récepteur récupérée qui soit inférieure à une fréquence de gigue prédéterminée établie pour ledit signal d'horloge récupéré.
  5. Emetteur selon la revendication 1, comprenant en outre
       un moyen de mémorisation élastique (105) pour mémoriser des mots de données entrés en utilisant ledit signal d'horloge d'entrée et pour sortir lesdits mots de données mémorisés dans des mots de données adjacents transmis à partir dudit émetteur en utilisant une horloge de données d'émetteur qui fonctionne de manière asynchrone par rapport audit signal d'horloge d'entrée.
  6. Système de communication de données comprenant un émetteur et un récepteur connectés ensemble par un canal de communication,
    ledit émetteur comprenant
    un moyen pour réduire par division (113) ledit signal d'horloge d'entrée en vue d'obtenir un signal de fréquence d'horloge de débit secondaire qui soit substantiellement inférieur et fonctionne de manière asynchrone par rapport à un débit de transmission de mots de données dudit émetteur, le système étant caractérisé au niveau de l'émetteur par
    un moyen pour générer (103, 105) un mot de données d'entrée à partir d'un signal analogique d'entrée échantillonné par un signal d'horloge d'entrée, ledit signal d'horloge d'entrée étant dérivé indépendamment dudit signal analogique d'entrée, et
    un moyen pour combiner (111, 107) un échantillon d'état logique dudit signal d'horloge de sous-débit avec ledit mot de données d'entrée pour former chaque mot de données à transmettre dans un format de données par paquets à partir dudit émetteur; et au niveau
    dudit récepteur par
    un moyen pour extraire (201) ledit échantillon d'état logique à partir de chacun desdits mots de données reçus à partir dudit émetteur et
    une boucle asservie en phase (210) pour générer, à partir dudit échantillon d'état logique, un signal d'horloge récupéré de la même fréquence et substantiellement en phase avec ladite horloge d'entrée.
  7. Système selon la revendication 6, dans lequel ledit signal d'horloge de débit secondaire est un Ne de la fréquence dudit signal d'horloge d'entrée, où N est supérieur ou égal à 2.
  8. Système selon la revendication 6, dans lequel ledit signal d'horloge de débit secondaire est un Ne de la fréquence dudit signal d'horloge d'entrée, où N est choisi de telle sorte que le rapport du débit de transmission de mots de données dudit système sur la fréquence de signal d'horloge de débit secondaire entraíne une gigue d'horloge de récepteur récupérée qui soit inférieure à une fréquence de gigue prédéterminée établie pour ledit signal d'horloge récupéré.
  9. Emetteur selon la revendication 6, comprenant en outre
    un moyen de mémorisation élastique (105) pour mémoriser des mots de données entrés en utilisant ledit signal d'horloge d'entrée et pour sortir lesdits mots de données mémorisés dans des mots de données adjacents transmis à partir dudit émetteur sur ledit canal de communication en utilisant une horloge de données d'émetteur qui fonctionne de manière asynchrone par rapport audit signal d'horloge d'entrée et dans lequel ledit récepteur comporte en outre
    un moyen de numérisation élastique (220) pour mémoriser les mots de données adjacents reçus dudit canal de communication à partir de l'émetteur en utilisant un signal d'horloge de données de récepteur qui fonctionne de manière synchrone par rapport audit signal d'horloge de données d'émetteur et pour sortir lesdits mots de données adjacents en utilisant ledit signal d'horloge récupéré.
  10. Procédé d'exploitation d'un appareil émetteur pour communiquer un mot de données numériques d'entrée et un signal d'horloge d'entrée sur un canal de communication à un débit de transmission de mots de données qui fonctionne de manière asynchrone par rapport audit signal d'horloge d'entrée, ledit procédé comprenant l'étape de
    division dudit signal d'horloge d'entrée par un nombre entier prédéterminé pour obtenir un signal de fréquence d'horloge de débit secondaire qui est substantiellement inférieur à un débit de transmission de mots de données dudit émetteur et étant CARACTERISE PAR les étapes de
    génération dudit mot de données d'entrée à partir d'un signal analogique d'entrée échantillonné par ledit signal d'horloge d'entrée, ledit signal d'horloge d'entrée étant dérivé indépendamment dudit signal analogique d'entrée, et
    combinaison d'un échantillon d'état logique dudit signal d'horloge de débit secondaire audit mot de données d'entrée pour former chaque mot de données à transmettre dans un format de données par paquets à partir dudit émetteur.
  11. Procédé selon la revendication 10, dans lequel ledit signal d'horloge de débit secondaire est un Ne de la fréquence dudit signal d'horloge d'entrée, où N est choisi de telle sorte que le rapport du débit de transmission de mots de données dudit émetteur sur la fréquence du signal d'horloge de débit secondaire entraíne une gigue d'horloge de récepteur récupérée qui soit inférieure à une fréquence de gigue prédéterminée établie pour ledit signal d'horloge récupéré.
  12. Procédé d'exploitation d'un système de communication de données comportant un émetteur et un récepteur connectés ensemble par un canal de communication, ledit procédé, au niveau dudit émetteur, comprenant les étapes de
    acceptation d'un signal d'horloge d'entrée qui est asynchrone par rapport à une horloge de transmission de mots de données dudit émetteur, et
    réduction par division dudit signal d'horloge d'entrée en vue d'obtenir un signal de fréquence d'horloge de débit secondaire qui soit substantiellement inférieur et fonctionne de manière asynchrone par rapport à un débit de transmission de mots de données dudit émetteur, et étant CARACTERISE au niveau de l'émetteur par les étapes de
    génération d'un mot de données d'entrée à partir d'un signal analogique d'entrée échantillonné par un signal d'horloge d'entrée, ledit signal d'horloge d'entrée étant dérivé indépendamment dudit signal analogique d'entrée, et
    combinaison d'un échantillon d'état logique dudit signal d'horloge de débit secondaire audit mot de données d'entrée pour former chaque mot de données à transmettre dans un format de données par paquets à partir dudit émetteur, et
    au niveau dudit récepteur par les étapes de
    extraction dudit échantillon d'état logique à partir de chacun desdits mots de données reçus à partir dudit émetteur et
    génération, à partir dudit échantillon d'état logique, d'un signal d'horloge récupéré de la même fréquence et substantiellement en phase avec ladite horloge d'entrée.
EP93302571A 1992-04-10 1993-04-01 Transmission d'un signal d'horloge sur un canal de données asynchrones Expired - Lifetime EP0565305B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US07/866,721 US5353313A (en) 1992-04-10 1992-04-10 Transmission of a clock signal over an asynchronous data channel
US866721 1992-04-10

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EP0565305A1 EP0565305A1 (fr) 1993-10-13
EP0565305B1 true EP0565305B1 (fr) 1998-01-21

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EP0565305A1 (fr) 1993-10-13
US5353313A (en) 1994-10-04
DE69316424D1 (de) 1998-02-26
JP2813106B2 (ja) 1998-10-22
DE69316424T2 (de) 1998-05-28

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