Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W88/00—Devices specially adapted for wireless communication networks, e.g. terminals, base stations or access point devices
  • H04W88/02—Terminal devices
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/40006—Architecture of a communication node
  • H04L12/40013—Details regarding a bus controller
• • G—PHYSICS
  • G06—COMPUTING OR CALCULATING; COUNTING
  • G06F—ELECTRIC DIGITAL DATA PROCESSING
  • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
  • G06F13/38—Information transfer, e.g. on bus
  • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
  • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
  • G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
  • G06F13/423—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus with synchronous protocol
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/06—Receivers
  • H04B1/16—Circuits
  • H04B1/1607—Supply circuits
  • H04B1/1615—Switching on; Switching off, e.g. remotely
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/38—Transceivers, i.e. devices in which transmitter and receiver form a structural unit and in which at least one part is used for functions of transmitting and receiving
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/40052—High-speed IEEE 1394 serial bus
  • H04L12/40071—Packet processing; Packet format
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L12/00—Data switching networks
  • H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
  • H04L12/40—Bus networks
  • H04L12/4013—Management of data rate on the bus
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L69/00—Network arrangements, protocols or services independent of the application payload and not provided for in the other groups of this subclass
  • H04L69/22—Parsing or analysis of headers
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04W—WIRELESS COMMUNICATION NETWORKS
  • H04W52/00—Power management, e.g. Transmission Power Control [TPC] or power classes
  • H04W52/02—Power saving arrangements
  • H04W52/0209—Power saving arrangements in terminal devices
  • H04W52/0225—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal
  • H04W52/0245—Power saving arrangements in terminal devices using monitoring of external events, e.g. the presence of a signal according to signal strength
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
  • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
  • Y02D30/00—Reducing energy consumption in communication networks
  • Y02D30/70—Reducing energy consumption in communication networks in wireless communication networks

Definitions

• This invention is directed to a packet transmission system and is especially suited for a packet system which must accommodate a variety of different peripheral devices.
• digital information is segregated into packets each containing a packet header, digitized data corresponding to the information to be transmitted and error checking information so that a receiving node in the system can verify that the packet has been correctly received.
• These packets are transmitted from node to node in the network to the destination address contained in the packet. At the destination address device, the packets are disassembled and the information provided to the receiving device.
• Packet protocols become increasingly inefficient as the amount of data to be transmitted per packet decreases ' " because of the required packet overhead required for each packet.
• an embodiment includes a device connected to a network interface bus including a packet bus and control lines capable of transmitting packets to a communication controller.
• the device can be requested to transmit upon receipt of a command from the controller.
• the device determines if the network interface bus is available' to accept data by determining if a first and second control line have a predetermined binary state. If the network interface bus is available, the device causes the first control line to change to the other binary state. Data is then written on the packet bus for communication to the controller.
• the device causes a third control line that functions as a packet clock to change binary states and thereby provides the controller with a signal to read the written data. If additional data is to be transmitted from the device, it is written on the bus and the third control line toggled to cause it to be read by the controller.
• the device indicates the end of a packet by causing the first control line to change from the other state to the predetermined state.
• FIG. 1 illustrates a wireless packet communication system suited for incorporating the present invention.
• FIG. 2 is a block diagram of a packet device in accordance with the present invention and suited for use in the system shown in FIG. 1.
• FIGS. 3A and 3B illustrate preferred packet formats utilized by the communication controller and a peripheral device, respectively, to communicate to the other.
• FIG. 4 is a flow diagram illustrating the transmission of data from a communication controller to a peripheral device as shown in FIG. 2.
• FIG. 5 is a timing diagram illustrating control signals utilized in accordance with the flow diagram of
• FIG. 4 is a flow diagram illustrating the transmission of data from a peripheral device to the communication controller shown in FIG. 2.
• FIG. 7 is a timing diagram illustrating controls utilized to transmit information in accordance with the steps of FIG. 6. Description of a Preferred Embodiment
• FIG. 1 illustrates a wireless packet communication system in which a control module 10 utilizes RF communications to communicate with user modules 12 that are each coupled to one or more user devices 14 consisting of a terminal, personal computer, telephone, or other information input/output device.
• the control module 10 is also coupled by a data channel 16 to a data network.
• the control module controls communications within the illustrated network and passes information from the data network via channel 16 to user devices 14 via the associated user module.
• the control module also controls local communications by receiving information from one user module and relaying the information to a different user module.
• the wireless information is conveyed in the form of packets.
• the data network to which control module 10 is connected may consist of an Ethernet network.
• FIG. 2 illustrates a block diagram of an embodiment of a packet system in accordance with the present invention.
• the illustrative embodiment is for a user module of the system as shown in FIG. 1.
• a communications controller 17 includes a microprocessor 18, with associated read only memory 20, random access memory 22', and a network interface 24.
• the network interface consists of appropriate registers and line drivers for communication with peripheral devices connected by network interface (NI) bus 26.
• NI network interface
• a plurality of peripheral devices including two way RF radio 28, a Tl Gateway input/output device 30, an ISDN Gateway I/O device 32, and a telephone I/O device 34.
• the peripherals 28-34 each contain a NI bus interface 36, 38, 40, and 42, respectively. These interfaces provide the necessary registers and line drivers for communicating with NI bus 26 and will also include an PU, RAM, and ROM if these resources are not available in the peripheral device.
• the radio 28 includes one or more antennas 44 for RF communications with the control module 10 as shown in FIG. 1.
• the Tl Gateway I/O device 30 is coupled by wire 46 to a Tl line.
• ISDN Gateway I/O device 32 is coupled by wire 48 to an ISDN network.
• the telephone I/O device 32 is connected by wire 50 to a telephone instrument.
• the illustrative peripherals are merely representative that virtually any type of information can be coupled by means of an appropriate input/output device to the NI bus.
• the various peripherals reformat information communicated via the NI bus into the proper format for communication to other devices connected by paths 44-50.
• FIG. 3A illustrates a preferred embodiment of a packet format utilized for communications from the controller 17 to a peripheral device over the NI bus 26. It is generally segmented to contain a NI header and NI information.
• the NI address field contains the address of the destination peripheral.
• the NI length field contains the number of bytes in the NI command field.
• the command field is used to control a peripheral and contains a command for the peripheral device, for example, commands used to poll for status of the interface, poll for data received by an interface, or transmit/receive data.
• the information field may or may not be present depending on which command has been sent.
• a poll-for-status command might not have an information field because a peripheral may return a well-defined status byte or bytes every time polled.
• the poll-for-status command could be further qualified with information that requests particular- status information from a set of status information kept by a peripheral device.
• An example would be a peripheral device that controls several interface ports such as multiple telephone lines.
• the controller may wish to poll about the status of a particular line and the information field would be used to convey which line was of interest.
• the information field may also contain a well-formed data packet including header, data, and CRC field for transmission.
• the command field may contain a radio transmit command addressed to radio 28 in which case the NI information field contains the data to be transmitted.
• FIG. 3B illustrates a preferred embodiment of the NI bus packet format for Peripheral-to-Controller communication.
• the NI address field contains the address of the controller since all traffic in the preferred embodiment is routed through the controller. However, direct peripheral-to-peripheral communication is possible wherein the address field would contain the address of the destination peripheral, the NI data field contains the data requested by the controller, and the additional bytes field contains status information from the peripheral device. The additional bytes field is optional. Contrasting this format to that of FIG. 3A, the NI address constitutes the NI header and NI data, with or without the additional byte field, constitutes the NI information field.
• FIG. 4 is a flow diagram illustrating the steps implemented by the communications controller 17 to transmit data or commands to a peripheral connected to the NI bus.
• the timing diagram illustrated in FIG. 5 also relates to the transmission of packets of data from the communications controller to the peripherals and should be read in conjunction with the steps described in FIG. 4.
• the timing diagram in FIG. 5 represents the physical NI bus which consists of a packet bus having a plurality of lines for conveying a byte of data during each bus clock cycle and separate control lines for packet clock, packet start, NI source, and bus clock.
• the NI source and bus clock lines are always controlled by the communications controller; the remaining lines and packet bus are bi-directional, i.e. the communications controller and the peripherals are capable of writing to and reading these lines.
• the transmission of data from the communications controller to a peripheral is accomplished as follows. Beginning with entry at START 52, the controller drives the NI source line from high to low as indicated in step 54. This gives the controller control of the NI bus and communicates to all peripherals that they are to receive data which will be transmitted from the controller.
• the controller drives the packet start line from high to low which marks the beginning of the transmission of a packet to be transmitted by the controller to a peripheral.
• the controller writes a byte of data on the packet bus as indicated by step 58.
• the controller drives the packet clock line from high to low and back high. The peripherals read the data written on the packet bus during the high to low transition of the packet clock.
• decision step 52 the controller determines if all data has been transmitted.
• step 62 YES
• the controller drives the NI source line from low to high releasing control of the NI bus and packet start from low to high marking the end of the packet in step 64.
• This method terminates at END 66.
• the communications controller sent a single packet as illustrated in FIG. 3A to one or a predetermined group of peripherals.
• the NI header contains the NI address, i.e. the peripheral device address of a particular peripheral or a group address for a predetermined group of peripherals.
• each peripheral After receiving and decoding the peripheral address contained in the NI header, each peripheral can determine if the following information is intended for it. If the information is intended for a peripheral, then it will continue reading the data transmitted by the controller. If the packet is not intended for a peripheral, then it need not further process the information and can merely look for a low to high transition of the packet start line indicating the end of transmission of that packet.
• the controller may alternatively maintain the NI source line low, indicate the end of the packet transmission by driving the packet start line from low to high and then begin transmission of another packet by driving packet start from high to low thereby not relinquishing control of the NI bus between the transmission of successive packets.
• the packet clock line is controlled by the transmitting device with the high to low transition being a signal to the receiving device that data on the packet bus is stable and should be read.
• FIG. 6 shows a flow diagram illustrating steps performed by a peripheral device in transmitting data to the communications controller. These steps should be read in conjunction with the timing diagram shown in FIG. 7.
• the timing diagram in FIG. 7 illustrates one additional control line, packet end, not shown in FIG. 5.
• the packet bus, packet clock, and packet start lines were sourced by the communications controller.
• the packet bus, packet clock, and packet start lines are sourced by a peripheral.
• the packet end, NI source, and bus clock are sourced by the controller.
• a flag (F) is set to zero. This flag generally relates to the ability of the controller to allow certain additional bytes or data to be transmitted after the end of the packet as marked by packet start. The operation of this flag is explained in detail below.
• step 69 a determination is made by the peripheral if it has been instructed by a command from the controller on the packet bus to transmit data. A NO determination by step 69 results in a return to
• step 70 determines if packet start is high. A NO decision results in the termination of the method at END 72 since packet start must be high in order for a peripheral to initiate data transmission.
• step 74 determines if NI source is high. A NO decision by step 74 results in the termination of the method at END 72 since NI source must be high to allow transmission by a peripheral device. A YES decision by step 74 indicates that the NI bus is available for data transmission by the peripheral.
• step 78 the peripheral drives packet start line from high to low thereby advising the controller to receive data.
• the peripheral then proceeds to write data on the packet bus in step 80.
• the peripheral then drives the packet clock line from high to low which provides a timing signal to the controller to read the data on the packet bus.
• step 84 a decision is made if packet end is low.
• the packet end line is controlled by the controller and can be utilized to ' terminate transmission by a peripheral at any time.
• a NO decision in step 84 leads to a determination in step 86 if flag F is high.
• a YES decision results in the peripheral initiating a stop sending data sequence 88 in which transmission of data is stopped.
• a NO determination by step 86 i.e.
• step 90 results in a determination by the peripheral as to whether all data has been transmitted in step 90.
• a NO decision returns control to step 80 in which additional data is transmitted to the controller.
• a YES determination by step 90 indicating the end of desired data transmission by the peripheral, results in the peripheral driving the packet start from low to high as indicated in step 92. This tells the controller that the peripheral has finished transmitting the packet. Following step 92 the method terminates at END 94.
• step 96 the peripheral responds to this command by setting flag equal to 1.
• step 98 a determination is made by the peripheral if more data remains to be sent to the controller. A NO decision results in terminating the transmission by return to steps 92 and 94.
• step 98 indicating that more data is to be sent, causes a return to step 80 in which the next byte of data is written to the packet bus and the packet clock is incremented in step 82.
• step 84 If the packet end line remains low as determined by step 84 the same sequence of steps will proceed until the peripheral has transmitted all of its data as determined by step 98. However, if the controller has caused the flag F to be reset by driving packet end from low to high, a NO determination will be made by step 84. In this case, step 86 will result in a YES determination since the flag has been set thereby implementing the immediate stop function by step 88.
• the controller can terminate the transmission of data by a peripheral by driving packet end from high to low to high.
• the packet start line is driven by the peripheral from low to high prior to a packet end line termination command, i.e. from high to low to high.
• a packet end line termination command i.e. from high to low to high.
• the peripheral completed the transmission of its data without an interruption by the controller.
• the heavy dashed line associated with the packet start line in FIG. 7 illustrates an alternative example in which the peripheral continued to have data to send but was interrupted by the packet end command, whereby the packet start line remains low until the beginning of the heavy dashed line and returns high concurrent with the packet end line being driven from low to high by the controller.
• This mechanism is advantageous in that it permits the possibility of additional bytes of data to be transmitted beyond a predefined packet as determined by the packet start line.
• a peripheral can immediately send a number of bytes of additional information following a packet.
• Such bytes of information can be utilized to monitor conditions of the peripheral or may correspond to general update information provided by the peripheral following the transmission of the packet. This permits such information to be communicated without requiring it being carried within a packet. This provides additional flexibility of communications which is especially advantageous when a plurality of peripherals each communicate with a common controller.
• the controller will process the packet and reformat a packet with a NI header addressed to the destination peripheral and transmit it over the NI bus.
• the communications controller acts as a traffic cop in routing packets and information between peripherals as well as providing a common point of coordination of communications.

Landscapes

• Engineering & Computer Science (AREA)
• Signal Processing (AREA)
• Computer Networks & Wireless Communication (AREA)
• Theoretical Computer Science (AREA)
• General Physics & Mathematics (AREA)
• Physics & Mathematics (AREA)
• General Engineering & Computer Science (AREA)
• Quality & Reliability (AREA)
• Computer Security & Cryptography (AREA)
• Multimedia (AREA)
• Small-Scale Networks (AREA)
• Communication Control (AREA)
• Circuits Of Receivers In General (AREA)
• Superheterodyne Receivers (AREA)
• Mobile Radio Communication Systems (AREA)

Applications Claiming Priority (2)

Publications (2)

Family

ID=24595018

Family Applications (1)

Country Status (5)

Families Citing this family (7)

Family Cites Families (8)

• 1992
  • 1992-01-24 WO PCT/US1992/000595 patent/WO1992013395A1/en not_active Ceased
  • 1992-01-24 JP JP4505855A patent/JP2678690B2/ja not_active Expired - Lifetime
  • 1992-01-27 JP JP50571592A patent/JPH06505600A/ja active Pending
  • 1992-01-27 WO PCT/US1992/000646 patent/WO1992013414A1/en not_active Ceased
  • 1992-01-27 KR KR1019930702234A patent/KR970007257B1/ko not_active Expired - Fee Related
  • 1992-01-27 EP EP92905769A patent/EP0569512A4/en not_active Withdrawn
  • 1992-01-27 BR BR9205487A patent/BR9205487A/pt not_active Application Discontinuation

Also Published As

Similar Documents

Legal Events