EP0586558A1 - Module d'interconnexion multipuce comprenant des materiaux supraconducteurs - Google Patents

Module d'interconnexion multipuce comprenant des materiaux supraconducteurs

Info

Publication number
EP0586558A1
EP0586558A1 EP92913021A EP92913021A EP0586558A1 EP 0586558 A1 EP0586558 A1 EP 0586558A1 EP 92913021 A EP92913021 A EP 92913021A EP 92913021 A EP92913021 A EP 92913021A EP 0586558 A1 EP0586558 A1 EP 0586558A1
Authority
EP
European Patent Office
Prior art keywords
superconducting
module
intercon
nect
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92913021A
Other languages
German (de)
English (en)
Other versions
EP0586558A4 (en
Inventor
Timothy Walton James
Roger James Forse
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Clearday Inc
Original Assignee
Superconductor Technologies Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Superconductor Technologies Inc filed Critical Superconductor Technologies Inc
Publication of EP0586558A1 publication Critical patent/EP0586558A1/fr
Publication of EP0586558A4 publication Critical patent/EP0586558A4/en
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/66—Conductive materials thereof
    • H10W70/668—Superconducting materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H10W72/07251—Connecting or disconnecting of bump connectors characterised by changes in properties of the bump connectors during connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps

Definitions

  • Multichip Interconnect Module Including Superconductive Materials
  • This invention relates to the manufacture of useful devices from high-temperature superconducting thin films.
  • the invention relates to the use of superconductive thin films to form multichip interconnect modules.
  • Multichip interconnect modules are devices for providing electrical connection between a number of integrated circuit chips. Most currently available multichip interconnect modules utilize electrical interconnects which have non-zero resistance. Typically, a multilayer structure is utilized in which electrical interconnections run in various directions at different levels to provide sufficient connection between the chips.
  • a silicon substrate utilizes aluminum interconnections with a silicon dioxide (Si0 2 ) dielectric.
  • Si0 2 silicon dioxide
  • this microstrip wave guide structure consists of parallel aluminum interconnections separated by a Si0 2 dielectric, with the wave guide being disposed on a silicon substrate. In some devices, the amount of Si0 2 is reduced in order to reduce the overall dielectric constant of the device.
  • Thallium containing superconducting films have been successfully grown on a variety of substrates such as lanthanum aluminate, magnesium oxide, yttria stabilized zirconia and sapphire, with the films being epitaxial in the first three cases.
  • Widely recognized benefits of superconducting materials are their essentially zero resistance to electrical current flow, which in turn means virtually zero resistive power losses. Additionally, transmission speeds through superconducting conductors are higher than through resistive materials. There is a general expecta ⁇ tion that superconducting materials would be useful in connection with high speed computers and electronics. It is further expected that fast integrated circuit devices in the future will operate at low temperatures, on the order of those required for high temperature superconduc ⁇ tors.
  • the conventional multichip interconnect module structure is incompatible with high temperature superconductor materials.
  • One principal problem is that the conventional design requires a relatively low dielectric constant.
  • a dielectric constant low enough generally ⁇ 5
  • to extend the conventional multichip interconnect module structure to superconductors would require a multilayer structure of superconductor/dielectric/superconductor, in which the bottom layer superconductor was patterned. Further, the interconnect layers would need to be epitaxial to one an other.
  • TlBa 2 Cu 3 0 7 as a Possible Basis For Superconducting Electron- ic Devices, Solid State Communications, Vol. 71, No. 7, pages 569-572, 1989.
  • a superconducting ground plane arrangement provides for wide bandwidth transmission of electrical signals.
  • a conductor is patterned from an epitaxial superconducting film on a substrate, with a ground plane which is formed coplanar with the conductor, and patterned from the same epitaxial superconducting film.
  • the coplanar ground plane is further provided with electrical interconnections between various portions of the coplanar ground plane to assure maintenance of a true ground potential.
  • Metallization contacts having good mechanical adhesion and electrical properties may be formed utilizing this tech- nique.
  • a passivation coating has been developed which provides protection for the superconducting film from environmental contact, and provides a suitable dielectric material upon which further structure may be constructed.
  • a polyimide material preferably Proba ide 412TM, has proved particularly useful for these purposes.
  • a detailed disclosure of this coating is described in copending application entitled Passivation Coating for Superconducting Film Device Serial No. 07/697,660, filed on the same day as this application. Both of these applications are incorporated herein by reference.
  • a hybrid multichip interconnect module successfully utilizes superconducting conductors. In this way, multiple interconnections may be made between a plurality of integrated circuit chips.
  • two single layer epitaxial superconducting films are hybridized to create a multichip module having x-direction and y-direction interconnects.
  • a coplanar wave guide structure is used in which the conductors alternate with coplanar ground plane strips.
  • Metallized interconnections between portions of the ground plane may be formed over the conductors.
  • contact to the integrated circuit chip may be made through interconnect vias. Acceptable signal propagation speed is achieved through use of the coplanar ground plane arrangement.
  • a plurality of trilayer films arranged in a microstrip arrangement are hybridized.
  • Each trilayer film consists of a stacked arrangement of a superconductor, a dielectric and another superconductor disposed upon a substrate.
  • the superconductor furthest from the substrate is patterned to provide a plurality of conductors.
  • Acceptable propagation speed is achieved through use of a microstrip geometry.
  • the effective dielectric constant is lowered by removing dielectric from between the superconducting elements.
  • a principal object of this invention is to provide a superconducting multichip interconnect module.
  • Fig. 1 is a plan view of a coplanar hybrid high temperature superconductor multichip interconnect module.
  • Fig. 2 is a cross-sectional view of Fig. 1 along A-A « .
  • Fig. 3 is a cross-sectional view of Fig. 1 along B-B*.
  • Fig. 4 is a plan view of a trilayer hybrid high temperature superconductor multichip interconnect module.
  • Fig. 5 is a cross-sectional view of Fig. 4 along A-A 1 .
  • Fig. 6 is a cross-sectional view of Fig. 4 along B-B 1 .
  • Figs. 1-3 show one embodiment of a coplanar hybrid high temperature superconductor multichip interconnect module.
  • Fig. 1 shows a plan view of the electrical conductors which would be formed above a substrate (not shown) .
  • Conductors 20 alternate with ground plane strips 22 to form a coplanar ground plane transmission arrangement.
  • the ground plane lines 22 are preferably interconnected by conductive ground plane interconnects 24.
  • Contact portions 26 provide mechanical and electrical contact between the interconnects 24 and the ground plane lines 22.
  • the details of the interconnect structure and the preferred method of manufacturing them is provided in co-pending application entitled Fabrication Process For Low Loss Metallizations On Superconducting Thin Film Devices Serial No. 07/697,960, incorporated herein by reference.
  • the conductors 20 and ground plane strips 22 are preferably formed of the same epitaxial high temperature superconductor formed on a substrate. It is currently possible to form epitaxial films from high temperature superconducting materials, such as the YBCO compounds as well as thallium superconductors. These films are desirable as they have critical temperatures T c which are higher than the boiling point of liquid nitrogen, thereby reducing the difficulty and expense of cooling the device to superconducting temperatures.
  • the conductors 20 and ground plane lines 22 may be patterned with any conventional technique, such as lithography techniques utilizing a photo mask followed by an etching step.
  • the structure of this invention is consistent with patterning of any size line width for the conductors 20 and ground plane lines 22.
  • the structure of this invention may be utilized to provide acceptable interconnects with higher packing density.
  • the hybrid multichip interconnect module is arranged with the x-direction and y-direction conductors orthoganol.
  • the conductors 20 and ground plane lines 22 associated with substrate 30 are preferably orthoganol to the conductor 20 and ground plane lines 22 (not shown) associated with substrate 32.
  • Fig. 2 is a cross-section of Fig. 1 on line A-A 1 the conductor 20 associated with the upper substrate 32 is shown having a portion removed.
  • Interconnections between the x-conductors and the y-conductors is preferably accomplished by an indium bump technique. In this technique, indium bumps 34 are placed on the conductors 20 for each of the x-conductors and y- conductors to be interconnected.
  • the two portions of the modules are aligned and compressed, matching the arrays of bumps on each circuit. Connection may be made from a chip 40 via a solder ball 42 through a die via 44 to connect with a y-conductor 20. The conductor 20 may then optionally connect to an x-conductor by the above described indium bump technique.
  • the substrate dielectric material is optionally removed between the conductors and ground plane lines 22.
  • a trench structure is used, being formed by any known technique such as trench etching or ion milling. Removal of the dielectric reduces the effective dielectric constant.
  • a passivation layer 46 is disposed over the surface of the substrate, conductors 20 and ground plane lines 22.
  • the dielectric constant with the trenches and with a passivation layer 46 comprised of a polyimide is less than 9, and is preferably on the order of 6.
  • a detailed description of the preferred passivation coating may be found in copending application entitled Passivation Coating for Superconducting Thin Film Device, filed on the same date as this application, and assigned to the common ass.ignee of this application, incorporated by reference.
  • Formation of the vias 44 may be performed by any technique compatible with the pitch size of the structure. Typically, a wet etch process will limit the pitch to the thickness of the substrate, which may be on the order of 50 to 100 microns. Dry etch processes are useful for smaller pitch structures. Reactive ion etching techniques are particularly useful as etching may be done at angles other than normal. Similarly, laser drilling techniques may be utilized to form die vias.
  • a trilayer hybrid high temperature superconducting multichip interconnect module structure is shown in Figs. 4-6.
  • a microstrip structure comprising two conductors separated by a dielectric is utilized for electrical signal transmission.
  • An x-direction structure 52 disposed on a substrate 54 is hybridized with a y- direction unit 56 disposed upon a substrate 58.
  • the x-direction unit 52 is arranged orthoganolly to the y-direction unit 56.
  • the x-direction unit 52 and the y-direction unit 56 are similar.
  • a trilayer structure is disposed on the substrate 54, having a superconductor ground plane 60, dielectric material 62 and patterned conductors 50.
  • the conductors 50 may be adjacent one another, without the need for intervening ground plane lines as is the case described above for the coplanar ground plane arrangement.
  • the conductors 50 are preferably parallel to one another, with separations in conductors adjacent the location where interconnects 70 are made.
  • a passivation coating 72 such as a polyimide coating, is disposed over the conductors 50 and dielectric layers 62, to provide environmental protection .
  • Die vias 74 may be made utilizing the techniques described above in connection with the coplanar arrangement.

Landscapes

  • Superconductor Devices And Manufacturing Methods Thereof (AREA)

Abstract

Un module d'interconnexion multipuce utilise des conducteurs supraconducteurs permettant une vitesse accrue et une dissipation de puissance réduite. Dans un mode de réalisation, des unités conductrices ayant un sens x et un sens y comprennent chacune un substrat (30, 32) présentant des conducteurs supraconducteurs alternés (20) ainsi que des lignes de plan de masse (22). Lesdites lignes de plan de masse (22) sont connectées par des interconnexions (24) analogues à des ponts, et les unités conductrices ayant un sens x et un sens y sont connectées électriquement de manière sélective. Dans un autre mode de réalisation, un agencement multipuce supraconducteur utilise au moins deux structures présentant un substrat (30, 32), un plan de masse (20), un isolant (46) et une structure empilée de conducteurs supraconducteurs (22). Des interconnexions électriques sélectives sont réalisées entre les structures.
EP19920913021 1991-05-08 1992-05-08 Multichip interconnect module including superconductive materials Withdrawn EP0586558A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US69793991A 1991-05-08 1991-05-08
US697939 1991-05-08

Publications (2)

Publication Number Publication Date
EP0586558A1 true EP0586558A1 (fr) 1994-03-16
EP0586558A4 EP0586558A4 (en) 1994-07-13

Family

ID=24803209

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19920913021 Withdrawn EP0586558A4 (en) 1991-05-08 1992-05-08 Multichip interconnect module including superconductive materials

Country Status (2)

Country Link
EP (1) EP0586558A4 (fr)
WO (1) WO1992020108A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR950704819A (ko) * 1992-12-15 1995-11-20 미리암 디. 메코나헤이 전기적 상호 접속 구조체(electrical interconnect structures)
JP7077402B2 (ja) * 2017-10-05 2022-05-30 グーグル エルエルシー フリップチップ形状の低フットプリント共振器

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5990906A (ja) * 1982-11-16 1984-05-25 Hitachi Cable Ltd 絶縁超電導線
KR880013253A (ko) * 1987-04-17 1988-11-30 미다 가쓰시게 반도체 장치
CA1329952C (fr) * 1987-04-27 1994-05-31 Yoshihiko Imanaka Substrat pour circuit supraconducteur multicouche et procede de fabrication connexe
EP0290271B1 (fr) * 1987-05-08 1995-03-15 Fujitsu Limited Carte à circuit supraconducteur et procédé de sa fabrication
JPS63314850A (ja) * 1987-06-18 1988-12-22 Fujitsu Ltd 半導体装置
JPH01135097A (ja) * 1987-11-20 1989-05-26 Mitsubishi Electric Corp 多層配線基板の製造方法とその装置
JP2551114B2 (ja) * 1988-08-10 1996-11-06 富士通株式会社 超伝導回路基板の製造方法

Also Published As

Publication number Publication date
EP0586558A4 (en) 1994-07-13
WO1992020108A1 (fr) 1992-11-12

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