EP0597926A1 - Procede de verification de circuits integres avec au moins un circuit logique et circuit integre testable - Google Patents

Procede de verification de circuits integres avec au moins un circuit logique et circuit integre testable

Info

Publication number
EP0597926A1
EP0597926A1 EP92916321A EP92916321A EP0597926A1 EP 0597926 A1 EP0597926 A1 EP 0597926A1 EP 92916321 A EP92916321 A EP 92916321A EP 92916321 A EP92916321 A EP 92916321A EP 0597926 A1 EP0597926 A1 EP 0597926A1
Authority
EP
European Patent Office
Prior art keywords
flops
flip
test
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP92916321A
Other languages
German (de)
English (en)
Inventor
Claus-Peter Zepp
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP0597926A1 publication Critical patent/EP0597926A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318555—Control logic
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
    • G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
    • G01R31/318552—Clock circuits details
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/30—Marginal testing, e.g. by varying supply voltage
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/805—Real-time

Definitions

  • the invention relates to a method for testing integrated circuits according to the preamble of patent claim 1 and to a testable integrated circuit according to the preamble of patent claim 8.
  • Boundary scan is used for assemblies with logic circuits.
  • the logic circuits which can be tested with this method have test stages (boundary scan cells) at their signal inputs and their signal outputs, each of which contain a changeover switch and at least one memory stage.
  • the input test stages and the output test stages can be switched as a shift register chain. All shift register chains can also be connected in series by several logic circuits arranged on one module.
  • the boundary scan method is in the
  • test multiplexers which are connected to the signal lines also enables real-time testing of the logic circuits, but they require a great deal of effort due to additional connection points and complicated wiring.
  • the object of the invention is to provide a method for real-time testing of logic circuits which only requires a small amount of additional circuitry.
  • the logic circuits suitable for carrying out the method must be specified.
  • the method according to the invention enables real-time testing.
  • the additional circuitry corresponds approximately to that of the boundary scan method. Only a few additional connection points are required. Pure gate circuits can already be tested in several test cycles by double pulses of the system test signal. If the logic circuit contains clocked memory elements, the number of system test impulses per test cycle can be easily increased. It is also possible to test assemblies which have a plurality of integrated circuits (ICs, ASICs) connected in a chain.
  • ICs, ASICs integrated circuits
  • test combination is written serially into the input and output flip-flops.
  • the test combinations are written in series via a single connection point of the module. It is necessary to check the function with all relevant sequences of test combinations, one-zero and zero-one transitions having to be applied alternately at the inputs of the actual logic circuit.
  • a further combination can be dynamically tested and the output combinations can be transferred in parallel to the test device. If several logic circuits are connected in a chain, then only two output combinations can be tested in each case if all output combinations are to be checked with defined test combinations. Likewise, only two test combinations can be applied to the inputs of the downstream logic circuit and their output combinations be checked. A test cycle then comprises two test combinations and two system test pulses. In the case of logic circuits which, in addition to gate circuits, also contain flip-flops, the number of system test pulses per test cycle can of course be increased.
  • the input-side and output-side memory clock cycles can also be separated, as a result of which it is then also possible to work with the corresponding test programs.
  • the input and output trigger stages of the test stages can be triggered either by a test clock signal or a system clock signal.
  • flip-flops with two clock inputs in order to avoid additional running times by means of clock switches.
  • change-over switches multiplexers
  • Edge-triggered flip-flops are preferably used.
  • FIG. 5 shows a time diagram with test clock signals and system test signals.
  • FIG. 1 shows a logic circuit LSI of an integrated circuit IC1, in the input lines of which the series circuit of an input multiplexer EMI and an input flip-flop EK1; EM2 and EK2; EM3 and EK3 is switched on.
  • the inputs (connection points) E1 to E3 of the integrated circuit IC1 can be connected to the inputs ELI to EL3 of a logic network LN1 via the multiplexers.
  • the logic circuit fulfills its actual function.
  • the multiplexers EMI to EM3 - controlled by a signal S / P - also enable interconnection of the input flip-flops EK1 to EK3 to form a shift register (serial mode), as shown in FIG. 1, for test purposes.
  • the outputs ALI to AL3 of the logic network LN1 are connected to output trigger circuits AK1 to AK3 via output multiplexers AMI to AM3.
  • the output flip-flops can also be connected in series via the output multiplexers, so that they also form a shift register which is connected to the output of the last flip-flop EK3 of the input-side shift register. In this serial mode, test combinations can be written into the shift registers serially.
  • the input flip-flops and the output flip-flops are each supplied with individual pulses TI or SI of two different clock signals, a test clock signal TT and a system Clock signal ST (Fig. 5).
  • a test clock signal TT and a system Clock signal ST (Fig. 5).
  • flip-flops with only one clock input can also be selected, it then being necessary to switch between the two clock signals.
  • Another logic circuit LSO can be connected upstream of the logic circuit LSI and a further logic circuit LS2 can be connected downstream.
  • the inputs E1 to E3 of the first logic circuit LSI are connected in FIG. 1 to the outputs of a test device TE and the outputs AI to A3 of the last logic circuit are connected to the inputs of the test device.
  • the output flip-flops of the upstream test device or logic circuit are labeled API to AP3. In the case of a logic circuit, they can in turn be connected in a chain to form a shift register by means of multiplexers; as a rule, this is not necessary for a test facility.
  • the inputs of the test device TE or the downstream logic circuit LS2 are connected to the outputs AI to A3 of the logic circuit via input multiplexers EM21 to EM23.
  • the information of the output flip-flops AK1 to AK3 of the logic circuit LSI can be taken over in parallel via the multiplexers EM21 to EM23 in flip-flops EP1 to EP3, which serve as input test stages in the test device.
  • Often several logic circuits LSO, LSI, LS2, ... will be connected in a chain. These can be arranged in an integrated circuit or can also belong to several circuits. For logic circuits connected in a chain to a multi-level network, serial writing of the test combinations is absolutely necessary.
  • the multiplexers EM21 to EM23 are not absolutely necessary in the test facility; however, they permit the serial writing of the binary output combination output by the output flip-flops AK1 to AK3 and the logic states stored in the input flip-flops EK1 to EK3.
  • the number of input test stages EP must of course be increased if more output combinations are to be checked in one test section and the output combination of a logic circuit is not checked in each of several test sections. With only one logic circuit, as shown in FIG. 1, the test combination can of course also be adopted in parallel via the inputs E1 to E3. For a better understanding of the function of the test method, however, the restriction to a logic circuit should first be retained.
  • the signals are fed via inputs of the modules EB1 to EB3 for testing purposes during operation and.
  • the input flip-flops of the logic circuit are combined to a boundary register BR11, the output flip-flops to a boundary register BR12 and the output and input test stages to an output test register AR1 or input test register ER1.
  • Test combinations applied in parallel to the inputs EB1 to EB3 of the module BG allow the input lines and the solder joints to be checked; Test combinations inscribed serially in the output tipping stages enable the solder joints and the output lines or the connecting lines between the components to be checked.
  • the dynamic test can, of course, be carried out both on assemblies and on individual integrated circuits which are fitted into corresponding adapters Test facility can be used.
  • the static test of the logic circuit LSI can be carried out as in the previous boundary-scan method by writing all relevant test combinations in the input flip-flops EK1 to EK3 and the output combination ATI generated by the logic circuit LSI (or the logic network LN1) in the Output flip-flops AK1 to AK3 are taken over and read from these flip-flops in order to be checked in the test device TE.
  • test combinations TK1, TK2 are written into the input flip-flops EK1 to EK3 and the output test stages API to AP3 - ie a test double combination - with clock pulses TI (FIG. 5) of the test clock signal TT.
  • test combination TKO was previously written into the output flip-flops AK1 to AK3 in series.
  • test combination TK1 also had to be written into the input flip-flops serially if the same test clock pulses are supplied to both groups of flip-flops EK1 to EK3 and AK1 to AK3.
  • the multiplexers are switched from the serial mode to the operating mode, as shown in Fig. 2, and instead of clock pulses TI of the test clock signal TT, system test pulses SI of the system clock signal ST (Fig. 5) the flip-flops and optionally also supplied to the logic network LN1.
  • the system clock signal can be generated by a clock generator of the system to be tested and can be supplied by it via the test device. It can also be done by an adjustable generator the test facility. Control devices (counter devices) are provided in the test device, which make it possible to call up any number of clock pulses TI and system test pulses SI within a test cycle, the clock pulses TI for serial writing or reading and system test pulses for dy ⁇ Named testing includes.
  • the output flip-flops API to AP3 to an output test register AR1 the input flip-flops EP1 to EP3 to an input test register ER1 and the input and output flip-flops of the logic circuit are combined into boundary registers in FIG. 2.
  • the new test combination TK2 is taken over from the output test stages API to AP3 into the input trigger stages EK1 to EK3 of the logic circuit LSI.
  • the output combination ATI already present as a function of the first test combination TK1 at the outputs of the logic network LN1 is taken over into the output tilting stages AK1 to AK3.
  • the test combination TKO is simultaneously written in parallel in the input test stages EP1 to EP3 as the test device for checking the connecting lines.
  • the test and output combinations shown in Fig. 2 apply to this phase.
  • the dynamic function of the logic circuit LSI is checked by determining whether the output combination AT2 of the logic circuit corresponding to the new test combination TK2 is already being adopted in the output flip-flops AK1 to AK3 or whether due to excessively long runtimes Errors occur.
  • a parallel transfer is time-saving, but only possible with one logic circuit to be tested (or with the last output combination if several logic circuits are connected in a chain). This requires a third system test pulse. A further test register is required in the test device, even if the previous output combination TK1 is also to be checked.
  • test combination at the input of the logic network LN1 does not change with the second system test pulse, even if the input states of the input flip-flops remain unchanged.
  • a first system test pulse would therefore be sufficient to clock the input flip-flops EK1 to EK3. Since the suppression of the second (and a further) system test pulse would increase the circuit complexity, it is still fed to the input flip-flops. Accordingly, only the second test pulse for the output flip-flops is required for dynamic testing.
  • the creation of a third test combination with the second system test pulse can also be expedient for the test.
  • FIG. 3 shows an assembly BG, in which several logic circuits LSI, LS2 of integrated circuits IC1 and IC2, 'are connected in a chain.
  • the input flip-flops and output flip-flops are combined to form the boundary registers BR11 to BR22 shown.
  • the test combinations are written by the test device TE serially via the input EB1 into the input and output flip-flops of the logic circuits LSI and LS2.
  • the input flip-flops of the boundary register BR12 of the second logic circuit LS2 and the test register PR1 of the test device TE contain the result of the static check on the logic circuits.
  • the output flip-flops (registers BR12, BR22) contain the output combinations of the dynamic test. This method enables a test with defined test combinations that are not dependent on an upstream circuit.
  • the reading and checking of the output combinations can be done in several sections. New ones are already being produced during the serial reading and checking of the starting combinations
  • the static check of the logic circuit can also be carried out in the conventional boundary scan test.
  • test cycle comprising three system test pulses, in which the first (static) output combination of the first logic circuit LSI is first stored in the boundary register BR12, then in the boundary register BR21 of the next one Logic circuit LS2 is adopted and finally overwritten by the first "dynamic" output combination AT2.
  • the test device must then of course have a corresponding number of input test registers PR1, PR2, ..., the contents of which are checked in parallel or in a staggered manner during the writing of new test combinations in an evaluation circuit AW. If the test device also has several output test registers AR1, AR2, ..., of which the output test registers AR1 and AR2 are shown in FIG.
  • test can be carried out with several successive test combinations, which shortens the test time.
  • several output combinations of the upstream logic circuits - here the LSI logic circuit - are then overwritten in each test cycle; a "test over everything" is carried out, which must be supplemented by test cycles with two system test pulses to localize the fault if an error occurs.
  • logic circuits can also be implemented in an integrated module, which can be connected in a chain. Likewise, an assembly (or an ASIC) will often have more than two integrated circuits.
  • the connecting lines can also branch from outputs of one logic circuit to several. For serial writing or reading out of test information, all input flip-flops and output flip-flops are again connected in series as shift registers and switched to the operating mode for dynamic testing.
  • the logic circuits can also have memory elements which are clocked during operation by the system clock signal. Their function can also be checked by increasing the number of system test pulses SI until the change in the output combination caused by the memory element occurs. A logic circuit can be checked completely by following any test combination with all other test combinations. However, it is sufficient to check the actually occurring consequences of the input combinations.
  • the creation of the test program will usually be computer-aided.
  • the test program also controls the serial reading and reading as well as the evaluation.
  • FIG. 4 shows a circuit variant in which the multiplexers are replaced by the use of special flip-flops with two clock inputs TE1 and T2.
  • a data input DE1 or DE2 is assigned to each clock input.
  • the data and the clock inputs are logically combined in each case via an OR gate.
  • the logic output signal of the previous flip-flop EK2 is automatically adopted in the following flip-flop.
  • the pulses SI of the system clock signal or the system test signal result in a parallel data transfer into the input flip-flops.
  • the same arrangement can also be used for the output flip flops.

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

Dans le cadre de la vérification en temps réel, deux combinaisons de test TK1 et TK2 sont enregistrées dans les flip-flops d'entrée (EK1 à EK2) du circuit logique à vérifier (LS1) et les flip-flops de sortie (AP1 à AP2) du système de test placé en amont (TE) ou d'un circuit logique (LSO) placé en amont. La deuxième combinaison de test TK2 est transférée avec la première impulsion de test du système dans les flip-flops d'entrée (EK1 à EK3) et la combinaison de sortie (AT2) associée est transférée avec la deuxième impulsion de test dans les flip-flops de sortie (AK1 à AK2). Pour finir, cette combinaison de sortie est transférée dans le système de test (TE) et y est vérifiée. Un circuit intégré adapté à l'application de ce procédé comporte des flip-flops avec deux entrées d'impulsion.
EP92916321A 1991-08-08 1992-08-03 Procede de verification de circuits integres avec au moins un circuit logique et circuit integre testable Withdrawn EP0597926A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE4126333 1991-08-08
DE4126333 1991-08-08
PCT/DE1992/000638 WO1993003434A1 (fr) 1991-08-08 1992-08-03 Procede de verification de circuits integres avec au moins un circuit logique et circuit integre testable

Publications (1)

Publication Number Publication Date
EP0597926A1 true EP0597926A1 (fr) 1994-05-25

Family

ID=6437963

Family Applications (1)

Application Number Title Priority Date Filing Date
EP92916321A Withdrawn EP0597926A1 (fr) 1991-08-08 1992-08-03 Procede de verification de circuits integres avec au moins un circuit logique et circuit integre testable

Country Status (4)

Country Link
US (1) US5513187A (fr)
EP (1) EP0597926A1 (fr)
JP (1) JPH06509643A (fr)
WO (1) WO1993003434A1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE69606129T3 (de) * 1995-10-13 2015-03-05 Jtag Technologies B.V. Verfahren und Tester zur Beaufschlagung eines elektronischen Bausteins mit einem Triggerimpuls
US5867036A (en) * 1996-05-29 1999-02-02 Lsi Logic Corporation Domino scan architecture and domino scan flip-flop for the testing of domino and hybrid CMOS circuits
US5978944A (en) * 1997-11-26 1999-11-02 Intel Corporation Method and apparatus for scan testing dynamic circuits
JP3966453B2 (ja) * 1999-05-26 2007-08-29 株式会社ルネサステクノロジ 半導体集積回路
US11231462B1 (en) * 2019-06-28 2022-01-25 Synopsys, Inc. Augmenting an integrated circuit (IC) design simulation model to improve performance during verification

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DD284981B5 (de) * 1989-06-13 1996-11-28 Zentr Mikroelekt Dresden Gmbh Anordnung zum Test digitaler Schaltungen mit konfigurierbaren in den Test einbezogenen Takterzeugungsschaltungen
US5173906A (en) * 1990-08-31 1992-12-22 Dreibelbis Jeffrey H Built-in self test for integrated circuits
JP2535670B2 (ja) * 1991-01-28 1996-09-18 株式会社東芝 双方向入出力端子用バウンダリスキャンセル

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9303434A1 *

Also Published As

Publication number Publication date
US5513187A (en) 1996-04-30
JPH06509643A (ja) 1994-10-27
WO1993003434A1 (fr) 1993-02-18

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