EP0624862A2 - Circuit de commande pour dispositif d'affichage - Google Patents

Circuit de commande pour dispositif d'affichage Download PDF

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Publication number
EP0624862A2
EP0624862A2 EP94303106A EP94303106A EP0624862A2 EP 0624862 A2 EP0624862 A2 EP 0624862A2 EP 94303106 A EP94303106 A EP 94303106A EP 94303106 A EP94303106 A EP 94303106A EP 0624862 A2 EP0624862 A2 EP 0624862A2
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EP
European Patent Office
Prior art keywords
gray
scale voltage
bits
oscillating
signals
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Granted
Application number
EP94303106A
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German (de)
English (en)
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EP0624862B1 (fr
EP0624862A3 (fr
Inventor
Hisao Okada
Yuji Yamamoto
Mitsuyoshi Seo
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Sharp Corp
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Sharp Corp
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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3685—Details of drivers for data electrodes
    • G09G3/3688—Details of drivers for data electrodes suitable for active matrices only
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2310/00—Command of the display device
    • G09G2310/02—Addressing, scanning or driving the display screen or processing steps related thereto
    • G09G2310/0264—Details of driving circuits
    • G09G2310/027—Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2011—Display of intermediate tones by amplitude modulation
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2014—Display of intermediate tones by modulation of the duration of a single pulse during which the logic level remains constant
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals

Definitions

  • the present invention relates to a driving circuit for a display apparatus. More particularly, the present invention relates to a driving circuit for an active matrix type liquid crystal display apparatus which displays an image with multiple gray scales in accordance with digital video signals.
  • An active matrix type liquid crystal display apparatus includes a display panel and a driving circuit for driving the display panel.
  • the display panel includes a pair of glass substrates and a liquid crystal layer formed between the pair of glass substrates. On one of the pair of glass substrates, a plurality of gate lines and a plurality of data lines are formed.
  • the driving circuit is disposed for every pixel in the display panel, and the driving circuit applies a driving voltage to the liquid crystal of the display panel.
  • the driving circuit includes a gate driver for individually selecting one of a plurality of switching elements connected to the gate lines and the data lines, and a data driver for supplying a video signal corresponding to an image to pixel electrodes via the selected switching element.
  • Figure 11 shows a configuration of a part of a data driver in a prior art driving circuit.
  • the circuit 110 shown in Figure 11 outputs a video signal to one of a plurality of data lines.
  • the data driver requires circuits 110 the number of which is equal to the number of data lines provided in a display panel.
  • video data consists of three bits (Do, D 1 , D 2 ).
  • the video data may have eight values of 0 to 7, and a signal voltage supplied to each pixel is one of eight levels V O -V 7 .
  • the circuit 110 includes a sampling flip-flop M SMP , a holding flip-flop M H , a decoder DEC, and analog switches ASW O -ASW 7 .
  • a corresponding one of external source voltages V O -V 7 of respective eight levels which are different from each other is supplied.
  • control signals SO-S 7 are supplied from the decoder DEC, respectively. Each of the control signals SO-S 7 is used for switching the ON/OFF state of the analog switch.
  • the sampling flip-flop M SMP gets video data (Do, D 1 , D 2 ), and holds the video data therein.
  • an output pulse signal OE is applied to the holding flip-flop M H .
  • the holding flip-flop M H gets the video data (Do, D 1 , D 2 ) from the sampling flip-flop M SMP , and transfers the video data to the decoder DEC.
  • the decoder DEC decodes the video data (Do, D 1 , D 2 ), and produces a control signal for turning on one of the analog switches ASW O -ASW 7 in accordance with the respective values (0-7) of the video data (Do, D 1 , D 2 ).
  • one of the external source voltages V O -V 7 is output to a data line On.
  • the decoder DEC outputs a control signal S 3 which turns on the analog switch ASW 3 .
  • the analog switch ASW 3 becomes into the ON-state, and V 3 of the external source voltages V O -V 7 is output to the data line On.
  • the prior art data driver requires a large number of gray-scale voltages as the number of bits of video data increases. This causes the circuit configuration to be complicated and the circuit size to be increased. Moreover, interconnections between voltage source circuits and analog switches are also complicated.
  • Figure 12 shows a configuration for a part of a driving circuit disclosed in Japanese Laid-Open Patent Publication No. 6-27900.
  • the circuit 120 shown in Figure 12 outputs a video signal to one of a plurality of data lines. Accordingly, the data driver requires circuits 120 the number of which is equal to the number of data lines provided in a display panel. It is herein assumed that video data consists of 6 bits (Do, D 1 , D 2 , D 3 , D 4 , D 5 ).
  • the video data may have 64 values of 0-63, and a signal voltage applied to each pixel is one of nine gray-scale voltages Vo, V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V 64 , and a plurality of interpolated voltages which are produced from the gray-scale voltages V o , V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V 64 .
  • the circuit 120 includes a sampling flip-flop M SMP , a holding flip-flop M H , a selection control circuit SCOL, and analog switches ASW 0 -ASW 8 .
  • control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 are su p- plied from the selection control circuit SCOL, respectively.
  • Each of the control signals are used to switch the ON/OFF state of the analog signal.
  • clock signals t 1 , t 2 , t 3 , and t 4 are supplied. As is shown in Figure 13, the clock signals t 1 , t 2 , t 3 , and t 4 have duty ratios which are different from each other.
  • the selection control circuit SCOL receives 6-bit video data d 5 , d 4 , d 3 , d 2 , d 1 , and do, and outputs one of control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 in accordance with the value of the received video data.
  • the relationship between the input and the output of the selection control circuit SCOL is determined by using a logical table.
  • Table 1 shows a logical table for the selection control circuit SCOL.
  • the 1st to 6th columns of Table 1 indicate values of bits d 5 , d 4 , d 3 , d 2 , d 1 , and do of the video data, respectively.
  • the 7th to 15th columns of Table 1 indicate values of control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 4 ⁇ , S 56 , and S 64 , respectively.
  • Each blank in the 7th to 15th columns in Table 1 means that the value of the control signal is 0.
  • t i indicates that the value of the control signal is 1 when the value of the clock signal t i is 1, and the value of the control signal is 0 when the value of the clock signal t i is 0.
  • t i indicates that the value of the control signal is 0 when the value of the clock signal t i is 1, and the value of the control signal is 1 when the value of the clock signal t i is 0.
  • i 1, 2, 3, and 4.
  • the following equations are logical equations which define the relationships among the video data d 5 , d 4 , d 3 , d 2 , d 1 , and do, the clock signals t 1 , t 2 , t 3 , and t 4 , and the control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 4 ⁇ , S 56 , and S 64 shown in Table 1.
  • control signals S 24 , S 32 , S 40 , and S 48 are defined.
  • control signals S 56 and S64 are defined as follows.
  • ⁇ i ⁇ indicates a value when the binary data (d 5 , d 4 , d 3 , d 2 , d 1 , do) is represented in the decimal notation.
  • t i indicates a signal which is inverted from the signal t.
  • the selection control circuit SCOL is constructed by the logical circuits shown in Figures 14 and 15.
  • the logical circuit shown in Figure 14 produces 64 kinds of gray-scale selection data ⁇ 0 ⁇ - ⁇ 63 ⁇ in accordance with the value of 6-bit video data (d 5 , d 4 , d 3 , d 2 , d 1 , do).
  • the logical circuit shown in Figure 15 produces control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S64, based on the gray-scale selection data ⁇ 0 ⁇ - ⁇ 63 ⁇ and the clock signals t 1 , t 2 , t 3 , and t 4 .
  • the logical circuit shown in Figure 14 outputs the gray-scale selection data ⁇ 1 ⁇ .
  • the logical circuit shown in Figure 15 receives the gray-scale selection data ⁇ 1 ⁇ and alternately outputs the control signal So and the control signal S 8 at a duty ratio of the clock signal t 1 .
  • the gray-scale voltage V o and the gray-scale voltage V 8 are alternately output via the analog switch ASW o and the analog switch ASW s at the duty ratio of the clock signal t 1 to the data line On.
  • the actual data driver requires the selection control circuits SCOL the number of which is equal to the number of data lines.
  • the circuit scale of the selection control circuit SCOL largely affects the chip size of the integrated circuit on which the data driver is installed. If the circuit scale of the selection control circuit SCOL becomes large, the cost for the integrated circuit is increased. Moreover, if the number of bits of video data increases in order to realize an image with a larger number of gray scales, the circuit scale of the data driver is further increased. This also increases the size and the production cost of the integrated circuit.
  • the driving circuit of this invention is used for driving a display apparatus including pixels and data lines for applying voltages to the pixels and which displays an image with multiple gray scales in accordance with video data consisting of a plurality of bits.
  • the driving circuit includes: oscillating voltage specifying means for specifying one of a plurality of oscillating signals having respective duty ratios which are different from each other in accordance with video data consisting of bits selected from the plurality of bits, and for outputting the specified oscillating signal T and an oscillating signal T which is obtained by inverting the specified oscillating signal T; gray-scale voltage specifying means for producing gray-scale voltage specifying signals which specify a first gray-scale voltage and a second gray-scale voltage among a plurality of gray-scale voltages supplied from gray-scale voltage supply means, in accordance with video data consisting of bits other than the selected bits of the plurality of bits; and output means for outputting the first gray-scale voltage and the second gray-scale voltage specified by the gray-scale voltage specifying signals to the data lines, in accordance
  • the first gray-scale voltage and the second gray-scale voltage are adjacent ones of the plurality of gray-scale voltages.
  • the plurality of oscillating signals include oscillating signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7, respectively.
  • a driving circuit for driving a display apparatus including pixels and data lines for applying voltages to the pixels and which displays an image with multiple gray scales in accordance with video data consisting of a plurality of bits.
  • the driving circuit includes: control signal generating means for generating a plurality of control signals in accordance with video data consisting of a plurality of bits; and a plurality of switching means, each of the plurality of switching means being supplied with a corresponding one of the plurality of control signals and a corresponding one of a plurality of gray-scale voltages generated by gray-scale voltage generating means, the gray-scale voltage supplied to the switching means being output to the data lines via the switching means in accordance with the control signal, wherein the control signal generating means includes: oscillating voltage specifying means for specifying one of a plurality of oscillating signals having respective duty ratios which are different from each other in accordance with video data consisting of bits selected from the plurality of bits, and for outputting the specified oscillating signal T and an oscil
  • the first gray-scale voltage and the second gray-scale voltage are adjacent ones of the plurality of gray-scale voltages.
  • the plurality of oscillating signals include oscillating signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7, respectively.
  • the switching means is an analog switch.
  • a pair of gray-scale voltages are selected (specified) among a plurality of gray-scale voltages, and one of a plurality of oscillating signals is specified.
  • the driving circuit outputs a voltage signal which oscillates between the specified pair of gray-scale voltages at the oscillating frequency of the specified oscillating signal. Therefore, a plurality of interpolated gray scales can be realized between a plurality of applied gray-scale voltages.
  • the driving circuit of the invention by using the gray-scale voltage specifying means and the oscillating signal specifying means, it is possible to always realize an image display with multiple gray scales in both cases where the driving circuit directly outputs one of the plurality of gray-scale voltages and where the driving circuit alternately outputs the specified pair of gray-scale voltages.
  • the invention described herein makes possible the advantage of providing a driving circuit for a display apparatus, which has a simplified and small construction, and which can display an image with multiple gray scales in accordance with multi-bit video data.
  • a matrix type liquid crystal display apparatus is used as an example of a display apparatus. It is appreciated that the present invention is applicable to other types of display apparatus.
  • FIG 1 shows a construction of a matrix type liquid crystal display apparatus.
  • the liquid crystal display apparatus shown in Figure 1 includes a display section 100 for displaying a video image, and a driving circuit 101 for driving the display section 100.
  • the driving circuit 101 includes a data driver 102 which provides video signals to the display section 100 and a scanning driver 103 which provides scanning signals to the display section 100.
  • the data driver may be called “a source driver” or "a column driver”.
  • the scanning driver may be called “a gate driver” or "a row driver”.
  • the display section 100 includes an M x N array of pixels 104 (M pixels in each column and N pixels in each row; where M and N are positive integers), and also includes switching elements 105 respectively connected to the pixels 104.
  • TFTs thin film transistors
  • the data line may be called "a source line” or "a column line”.
  • the scanning line may be called "a gate line” or "a row line”.
  • the scanning driver 103 sequentially outputs a voltage which is kept at a high level during a specific time period from its output terminals G(j) to the corresponding scanning lines 107.
  • the specific time period is referred to as one horizontal period jH (where j is an integer of 1 to M).
  • the total length of time obtained by adding up all the horizontal periods jH (i.e., 1 H + 2H + 3H + ... + MH), a blanking period and a vertical synchronizing period is referred to as one vertical period.
  • the switching element 105 connected to the output terminal G(j) is in the ON-state.
  • the pixel 104 connected to the switching element 105 is charged in accordance with the voltage which is output from the output terminal S(j) of the data driver 102 to the corresponding data line 106.
  • the voltage of the thus charged pixel 104 remains unchanged for about one vertical period until it is charged again by the subsequent voltage to be supplied from the data driver 102.
  • Figure 2 shows the relationship among digital video data DA, sampling pulses T smpi , and an output pulse signal OE, during the jth horizontal period jH determined by a horizontal synchronizing signal H s y n .
  • sampling pulses T smp1 , T smp2 , ..., T smpi , ..., and T smpN are sequentially applied to the data driver 102
  • digital video data DA 1 , DA 2 ..., DA ..., and DA N are fed into the data driver 102 accordingly.
  • the jth output pulse OE j determined by the output pulse signal OE is then applied to the data driver 102.
  • the data driver 102 On receiving the jth output pulse OE j , the data driver 102 outputs voltages from its output terminals S(i) to the corresponding data lines 106.
  • Figure 3 shows the relationship among the horizontal synchronizing signal H s y n , the digital video data DA, the output pulse signal OE, and the timing of outputs of the data driver 102 and scanning driver 103, during one vertical period determined by a vertical synchronizing signal V s y n .
  • a SOURCE(j) indicates a level range of voltages output from the data driver 102, with such timing as shown in Figure 2 and in accordance with the digital video data applied during the horizontal period jH.
  • the SOURCE(j) is shown as a hatched rectangular area to indicate a level range of voltages output from all the N output terminals S(1) to S(N) of the data driver 102.
  • the voltage which is outputfrom the jth outputterminal G(j) of the scanning driver 103 to the jth scanning line 107 is changed to and kept at a high level, thereby turning on all the N switching elements 105 connected to the jth scanning line 107.
  • the N pixels 104 respectively connected to these N switching elements 105 are charged in accordance with the voltage applied to the corresponding data lines 106 from the data driver 102.
  • the above-described process is repeated M times, i.e., for the 1st to Mth scanning lines 107, so that an image corresponding to one vertical period is displayed.
  • the produced image serves as a complete display image on the display screen thereof.
  • the time interval between the jth output pulse OE j and the (j+1)th output pulse OE j+1 in the output pulse signal OE is defined as "one output period".
  • one output period is equal to a period represented by SOURCE(j) shown in Figure 3.
  • SOURCE(j) shown in Figure 3.
  • one output period is equal to one horizontal period. According to the present invention, however, one output period is not necessarily required to be equal to one horizontal period.
  • Figure 5 shows an exemplary waveform for a voltage signal output from the data driver 102 to the data lines 106 in one output period.
  • the voltage level of the voltage signal output to the data lines 106 is constant during one output period.
  • the voltage signal output to the data lines 106 includes an oscillating component which oscillates during one output period.
  • the voltage signal is a pulse- like signal, and a ratio of a high-level period to a low-level period, i.e., a duty ratio n:m is selected as described below.
  • Figure 6 shows a configuration of a part of the data driver 102 in the driving circuit 101.
  • the circuit 60 shown in Figure 6 outputs a video signal from an nth output terminal S(n) to one data line 106.
  • the data driver 102 includes circuits 60 the number of which is equal to the number of the data lines 106 provided in the display section 100.
  • the video data consists of 6 bits (Do, D 1 , D 2 , D 3 , D 4 , D 5 ).
  • the video data may have 64 kinds of values of 0 - 63, and a signal voltage applied to each pixel is one of nine gray-scale voltages Vo, V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V64, and interpolated voltages which are produced from any pair of the gray-scale voltages chosen from V o , V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V 64
  • the circuit 60 includes a sampling flip-flop M SMP which performs the sampling operation, a holding flip-flop M H which performs the holding operation, a selection control circuit SCOL, and analog switches ASW o -ASW 8 .
  • a corresponding one of nine gray-scale voltages V o , V 8 , V 16 , V 24 , V 32 , V 40 , V 48 , V 56 , and V 64 is supplied.
  • the gray-scale voltages V 0 -V 64 have respective levels which are different from each other.
  • the selection control circuit SCOL is provided with seven oscillating signals t 1 - t 7 .
  • the oscillating signals t 1 -t 7 have respective duty ratios which are different from each other.
  • sampling flip-flop M SMP and the holding flip-flop M H for example, D-type flip-flops can be used. It is appreciated that such sampling and holding flip-flops can be realized by using other types of circuit elements.
  • the sampling flip-flop M SMP gets video data (Do, D 1 , D 2 , D 3 , D 4 , D 5 ), and holds the video data therein.
  • an output pulse signal OE is applied to the holding flip-flop M H .
  • the video data held in the sampling flip-flop M SMP is fed into the holding flip-flop M H and output to the selection control circuit SCOL.
  • the selection control circuit SCOL receives the video data, and produces a plurality of control signals in accordance with the value of the video data.
  • the control signals are used for switching the ON/OFF states of the respective analog switches ASW 0 -ASW 8 .
  • the video data input to the selection control circuit SCOL is represented by do, d 1 , d 2 , d 3 , d 4 , and d 5
  • the control signals output from the selection control circuit SCOL are represented by So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S64.
  • Table 2 is a logical table for the lower three bits d 2 ,d 1 , and do of the 6-bit video data.
  • the 1 st to 3rd columns of Table 2 indicate the values of video data bits d 2 , d 1 , and do, respectively.
  • the 4th to 11th columns of Table 2 indicate which oscillating signal is specified from the oscillating signals to-t 7 .
  • the oscillating signals to-t 7 are clock signals having duty ratios of 8:0, 7:1, 6:2, 5:3, 4:4, 3:5, 2:6, and 1:7, respectively.
  • an oscillating signal has a duty ratio of k:0 or 0:k (k is a natural number)
  • the oscillating signal is defined as always being at a fixed level.
  • the oscillating signals t 5 , t 8 , and t 7 are the signals obtained by inverting the oscillating signals t 3 , t 2 , and t 1 .
  • Equation (6) can alternatively be represented as the following equation.
  • Table 3 is a logical table representing the relationships among the upper three bits d 5 , d 4 , and d 3 of the 6- bit video data, and the control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 ,_S 56 , and S 64 .
  • a variable T denotes a signal T which is defined by Equations (6) and (7).
  • a variable T denotes an inverted signal T obtained by inverting the signal T.
  • "T" denotes an inverted signal of the signal T.
  • logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10 are obtained.
  • the selection control circuit SCOL is constructed, for example, by the logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10.
  • the logical circuit 70 shown in Figure 7 selectively outputs oscillating signal specifying signals (0)-(7) for specifying one of a plurality of oscillating signals to-t 7 , in accordance with the lower 3 bits d 2 , d 1 , and do of the video data. More specifically, the video data d 2 , d 1 , and do and the inverted signals which are respectively obtained by inverting the video data d 2 , d 1 , and do by inverter circuits INV 0 and INV 2 are input into AND circuits AG 0 -AG 7 in such combinations that constitute 0-7 in binary notation. The oscillating signal specifying signals (0)-(7) are thus obtained as the outputs of the AND circuits AGo- AG 7 .
  • the logical circuit 80 shown in Figure 8 specifies one of the plurality of oscillating signals to-t 7 in accordance with the oscillating signal specifying signals, and produces the specified oscillating signal T and the inverted oscillating signal T which is obtained by inverting the specified oscillating signal T by an inverter circuit INV 3 . More specifically, the oscillating signal specifying signals (1)-(7) and the oscillating signals t 1 -t 7 are input into AND circuits BG 1 -BG 7 , respectively, as is shown in Figure 8. The oscillating signal specifying signal (0) and the outputs of the AND circuits BG 1 -BG 7 are supplied to an OR circuit CG. The oscillating signal T and the inverted oscillating signal T are obtained as the output of the OR circuit CG.
  • the logical circuit 90 shown in Figure 9 selectively outputs gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] for specifying a pair of gray-scale voltages from among a plurality of gray-scale voltages, in accordance with the upper three bits d 5 , d 4 , and d 3 of the video data. More specifically, the video data d 5 , d 4 , and d 3 and the inverted signals which are respectively obtained by inverting the video data d 5 , d 4 , and d 3 by inverter circuits INV 4 -INV 6 are input to AND circuits DG 0 -DG 7 in such combinations which constitute 0-7 in the binary notation. As the outputs of the AND circuits DG 0 -DG 7 , the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and (56] are obtained.
  • the logical circuit 95 shown in Figure 10 selectively outputs the control signals S 0 -S 64 , in accordance with the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56], the oscillating signal T, and the inverted oscillating signal T. More specifically, the gray-scale voltage specifying signals [0], [8], [16],
  • [24], [32], [40], [48], and [56], and the oscillating signal T are input into AND circuits EG o , EG 2 , EG 4 , EG 6 , EG s , EG 1o , EG 12 , and EG 14 , respectively.
  • the gray-scale voltage specifying signals [0], [8], [16], [24], [32], [40], [48], and [56] and the inverted oscillating signal T are input into AND circuits EG 1 , EG 3 , EG s , EG 7 , EGg, EG 11 , EG 13 , and EG 15 , respectively.
  • the outputs of the AND circuits EG 1 and EG 2 are coupled to the inputs of an OR circuit FG 1 , respectively.
  • the outputs of the AND circuits EG 3 and EG 4 are coupled to the inputs of an OR circuit FG 2 , respectively.
  • the outputs of the AND circuits EG 5 and EG 6 are coupled to an OR circuit FG 3 , respectively.
  • the outputs of the AND circuits EG 7 and EG 8 are coupled to the inputs of an OR circuit FG 4 , respectively.
  • the outputs of the AND circuits EG 9 and EG 10 are coupled to the inputs of an OR circuit FG s , respectively.
  • the outputs of the AND circuits EG 11 and EG 12 are coupled to the inputs of an OR circuit FG 6 , respectively.
  • the outputs of the AND circuits EG 13 and EG 14 are coupled to the inputs of an OR circuit FG 7 , respectively.
  • the control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 and S 64 are obtained.
  • the control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 are supplied to the corresponding analog switches ASW 0 -ASW 8 .
  • Each of the control signals So, S 8 , S 16 , S 24 , S 32 , S 40 , S 48 , S 56 , and S 64 has either a high-level value or a low-level value. For example, if the control signal is at a high level, the corresponding analog switch is controlled to be in the ON-state. If the control signal is at a low level, the corresponding analog switch is controlled to be in the OFF-state.
  • the relationship between the level of the control signal and the ON/OFF state of the analog signal can be set in a reverse manner.
  • a waveform of an oscillating voltage is specified in accordance with video data consisting of at least one bit selected from the plurality of bits. Then, in accordance with video data consisting of bits other than the above selected bit(s), a pair of gray-scale voltages are specified from a plurality of gray-scale voltages. As a result, a voltage signal of an appropriate level can be output for every value of video data.
  • the oscillating voltage is used for realizing a plurality of interpolated gray-scale voltages between the specified pair of gray-scale voltages which are specified from among the plurality of gray-scale voltages.
  • the duty ratio n:m of the oscillating signal or the control signal is interpreted to be k:0 or 0:k (k is a natural number).
  • the specified pair of gray-scale voltages among the plurality of gray-scale voltages may be alternately output.
  • the selection control circuit SCOL according to the invention constructed of the logical circuits 70, 80, 90, and 95 shown in Figures 7 through 10 has a simplified construction as compared with the conventional selection control circuit SCOL shown in Figure 12 which is constructed of the logical circuits shown in Figures 14 and 15.
  • a driving circuit having a more simplified construction.
  • the actual data driver requires selection control circuits SCOL the number of which is equal to the number of data lines.
  • the circuit scale of the selection control circuits SCOL largely affects the chip size of an integrated circuit (LSI) on which a data driver is installed.
  • LSI integrated circuit
  • the circuit scale of the selection control circuits SCOL largely affects the chip size of an integrated circuit (LSI) on which a data driver is installed.
  • the invention it is possible to significantly reduce the size of the integrated circuit including the selection control circuits SCOL.
  • the production cost of the integrated circuit can be reduced.
  • the circuit scale of the data driver is of great use. Accordingly, it is possible to make further progress in the size and cost reduction of the integrated circuit.
  • the invention it is possible to obtain one or more interpolated voltages from voltages supplied from given voltage sources, whereby the number of voltage sources can be greatly decreased as compared with a conventional driving circuit which requires a large number of voltage sources. If the voltage sources are provided from the outside of the driving circuit, the number of input terminals of the driving circuit can be reduced. If the driving circuit is constructed as an LSI, the number of input terminals of the LSI can be reduced. According to the invention, it is possible to realize a driving LSI for displaying an image with multiple gray scales which could not be realized by the prior art example because of the increase in the number of terminals.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP19940303106 1993-05-14 1994-04-28 Circuit de commande pour dispositif d'affichage Expired - Lifetime EP0624862B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP11346593 1993-05-14
JP11346593 1993-05-14
JP113465/93 1993-05-14

Publications (3)

Publication Number Publication Date
EP0624862A2 true EP0624862A2 (fr) 1994-11-17
EP0624862A3 EP0624862A3 (fr) 1995-05-17
EP0624862B1 EP0624862B1 (fr) 1999-06-16

Family

ID=14612937

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19940303106 Expired - Lifetime EP0624862B1 (fr) 1993-05-14 1994-04-28 Circuit de commande pour dispositif d'affichage

Country Status (4)

Country Link
EP (1) EP0624862B1 (fr)
KR (1) KR0127102B1 (fr)
CN (1) CN1065059C (fr)
DE (1) DE69419070T2 (fr)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0655726A1 (fr) * 1993-11-26 1995-05-31 Sharp Kabushiki Kaisha Circuit de sélection de niveau de gris pour un circuit de commande d'affichage
US5673061A (en) * 1993-05-14 1997-09-30 Sharp Kabushiki Kaisha Driving circuit for display apparatus
US5923312A (en) * 1994-10-14 1999-07-13 Sharp Kabushiki Kaisha Driving circuit used in display apparatus and liquid crystal display apparatus using such driving circuit
US6067064A (en) * 1995-12-21 2000-05-23 Hitachi, Ltd. Liquid crystal driving circuit and liquid crystal display system using the same

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN100558206C (zh) * 1997-02-17 2009-11-04 精工爱普生株式会社 显示装置
EP1830344B1 (fr) * 1997-02-17 2012-07-04 Seiko Epson Corporation Structure d'un circuit de commande d'élément d'image pour un dispositif d'affichage luminescent
KR100593670B1 (ko) * 1999-08-25 2006-06-28 삼성전자주식회사 박막트랜지스터 액정표시장치의 소스드라이버의 계조전압을 선택하기 위한 디코딩회로
KR100555303B1 (ko) * 2002-12-11 2006-03-03 엘지.필립스 엘시디 주식회사 감마 전압 생성 장치 및 방법
JP4516280B2 (ja) * 2003-03-10 2010-08-04 ルネサスエレクトロニクス株式会社 表示装置の駆動回路
US8810606B2 (en) 2004-11-12 2014-08-19 Samsung Display Co., Ltd. Display device and driving method thereof
KR101197043B1 (ko) * 2004-11-12 2012-11-06 삼성디스플레이 주식회사 표시 장치 및 그 구동 방법

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2642204B2 (ja) * 1989-12-14 1997-08-20 シャープ株式会社 液晶表示装置の駆動回路
DE69226723T2 (de) * 1991-05-21 1999-04-15 Sharp K.K., Osaka Verfahren und Einrichtung zum Steuern einer Anzeigeeinrichtung
JPH05100635A (ja) * 1991-10-07 1993-04-23 Nec Corp アクテイブマトリクス型液晶デイスプレイの駆動用集積回路と駆動方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5673061A (en) * 1993-05-14 1997-09-30 Sharp Kabushiki Kaisha Driving circuit for display apparatus
EP0655726A1 (fr) * 1993-11-26 1995-05-31 Sharp Kabushiki Kaisha Circuit de sélection de niveau de gris pour un circuit de commande d'affichage
US5923312A (en) * 1994-10-14 1999-07-13 Sharp Kabushiki Kaisha Driving circuit used in display apparatus and liquid crystal display apparatus using such driving circuit
US6067064A (en) * 1995-12-21 2000-05-23 Hitachi, Ltd. Liquid crystal driving circuit and liquid crystal display system using the same

Also Published As

Publication number Publication date
CN1065059C (zh) 2001-04-25
KR0127102B1 (ko) 1997-12-29
CN1099177A (zh) 1995-02-22
DE69419070T2 (de) 1999-11-18
DE69419070D1 (de) 1999-07-22
EP0624862B1 (fr) 1999-06-16
EP0624862A3 (fr) 1995-05-17

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