Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W95/00—Packaging processes not covered by the other groups of this subclass
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W44/00—Electrical arrangements for controlling or matching impedance
  • H10W44/20—Electrical arrangements for controlling or matching impedance at high-frequency [HF] or radio frequency [RF]

Definitions

• the invention re. es to an improved chip carrier package and method of making the same such that the carrier is suitable for high radio frequency and microwave applications while maintaining low loss, low permittivity and low cost.
• the present invention finds particular utility in those applications requiring frequencies above 900 MHz.
• Ceramic packages with leads are produced cost ⁇ _.-ectively by thick or thin film metallization of a ceramic layer which is then cofired with a cover piece of ceramic green sheet to form the frame with leads.
• the ceramics have relatively high permittivity and the metal leads formed from firing powdered metal with glass frits have relatively high losses at high frequencies.
• Chip devices or dies designed for high speed or high frequency applications are usually built on gallium arsenide (GaAs) substrates typically only about 100 micrometers thick. To realize planned performance at or above 900 MHz, the mounting surface must be a conductive ground plane. GaAs dies are typically mounted to the floor of a costly metal housing with gold-tin or gold-silicon solder.
• GaAs gallium arsenide
• the above-discussed and other problems and deficiencies of the prior art are overcome or alleviated by the novel chip carrier package and method of manufacture thereof of the present invention.
• the present invention is intended for, and effective in overcoming deficiencies of, prior art chip carriers with respect to high frequency and microwave applications.
• the method of constructing the chip carrier package of this invention is extremely cost effective and so, is economically desirable.
• the chip carrier is constructed by providing a metallic base plate appropriately dimensioned and shaped to accept and interconnect with a first layer frame of dielectric material having a low permittivity.
• the base plate will have a raised central portion which can be of any desired shape; the first frame layer of dielectric material then being shaped to fit over the raised portion in a cooperating manner.
• a lead frame having been previously manufactured, and having an outer perimeter and finger-like leads extending inwardly therefrom, is placed upon the first frame layer of dielectric material so that the inner ends of the leads overlay the dielectric material.
• a line connecting the inner ends of the leads would define a space having a shape, preferably square or rectangular, similar to the shape of the raised portion of the base plate.
• a second frame layer of dielectric material is placed so as to sandwich the ends of the leads between the first and second frame layers of dielectric material.
• the second frame layer of dielectric material is shaped substantially similarly to the first frame layer and defines a void having the same shape as the space defined by the inner ends of the leads but having slightly larger dimensions, preferably square or rectangular.
• first dielectric frame layer, lead frame and second dielectric frame layer are properly assembled, the entire structure is clamped and then heated to a temperature sufficient to soften the dielectric and thereby embed the leads in the dielectric material. This step is followed by a speedy cooling step to prevent the dielectric material from deforming in the areas not contacted by leads.
• the chip carrier can subsequently be cut free from the lead frame by any of a number of conventional methods, such as punching. Leads are then available for desired bending and/or mounting. It will be appreciated that other types of mounting arrangements for carriers, for example, plated through hole pins, etc. and many different configurations of chip carriers can be produced using the method of the invention.
• the resultant electronic chip carrier package comprises an array of metal leads bonded between two layers of a sheet polymer composite (e.g., filled fluoropolymer dielectric) that have been precut to form frames in such a way that the metal leads extend from outside to inside of the single frame shape formed by a pressure and heat bonding step.
• a sheet polymer composite e.g., filled fluoropolymer dielectric
• the polymer composite frame serves the dual purpose of holding the leads in a desired configuration for later assembly and testing steps both inside and outside of its area, and of providing a microwave quality, low insertion loss, low permittivity and electrical insulation function between leads and ground planes.
• This dual purpose is provided in a uniquely cost-effective way that makes it of particular value for packaging high frequency (e.g., greater than 900 MHz) electronic components intended for growing consumer and commercial applications market.
• FIGURE 1 is an exploded, perspective view of the chip carrier of the invention
• FIGURE 2 is a top plan view of the assembled chip carrier with the lead frame still attached;
• FIGURE 2a is a cross-section of FIGURE 2 taken along section line a-a.
• FIGURE 2b is a cross-section of FIGURE 2 taken along section line b-b
• FIGURE 3 is a perspective view of the completed chip carrier package of the invention
• FIGURE 4 is a top plan view of another embodiment of the invention showing five RF leads with widened sections outside of the package and 3 DC leads;
• FIGURE 5 is a top plan view of another embodiment featuring a small space between the metallic base and the first dielectric layer;
• FIGURE 5a is a cross-sectional view of FIGURE 5 taken along section lines a-a;
• FIGURE 6 is a top plan view of a further embodiment.
• FIGURE 6a is a sectional view of FIGURE 6 taken along section lines a-a; .
• FIGURE 6b is an enlarged side view of FIGURE 6 taken along section lines a-a.
• FIGURE 7 is a perspective view of a dual in-line type of chip carrier package made by the invention.
• FIGURE 7a is a side view of FIGURE 7.
• FIGURE 7b is an end view of FIGURE 7.
• FIGURE 7c is a top plan view of FIGURE 7.
• FIGURE 8 is a perspective view of another embodiment of the invention where the entire carrier is enclosed in covering material.
• FIGURE 8a is a side view of FIGURE 8.
• FIGURE 8b is an end view of FIGURE 8.
• FIGURE 8c is a top plan view of FIGURE 8.
• a base plate 10 which can be metallic or made of a conductive polymer such as a PTFE material partially plated with a conductive resin such as silver-epoxy resin composite.
• the metal used is copper but can be any conductive metal.
• the base metal is coined to have a raised plateau area 30 of about 0.025 inch (0.64 mm) in thickness and a border region 20 of about 0.013 inch (0.33 mm) in thickness.
• the shape of the plateau area 30 is, as mentioned above, complimentary to the shape of the first dielectric frame layer 40.
• the raised plateau 30 of the base metal is in the shape of a square or rectangle when viewed from the top.
• the preferred dielectric material comprises a filled fluoropolymeric material.
• the fluoropolymeric matrix comprises polytetrafluoroethylene (PTFE) with glass microfiber filler.
• the fluoropolymer matrix may also contain a suitable inorganic filler material such as ceramic powder (Ti0 2 , Si0 2 or alumina). Materials of this type are commonly available from Rogers Corporation of Rogers, Connecticut, under the trademark RT/Duroid with a more preferred material comprising glass microfiber reinforced PTFE sold under the trademark RT/Duroid 5870.
• the most preferred material however, is a variant of RT/Duroid 5870 called Ultralam GH where cladding is not applied to the dielectric material by the manufacturer of the material.
• Ultralam GH is due to the better bonding properties of the unclad material. This particular material was chosen because of its known desirable electrical properties such as low permittivity, low loss, microwave compatibility, high temperature capability and ease of fabrication.
• the thickness of the dielectric material used, in order to meet space constraints and design impedance values is as little .as 250 ⁇ m for each frame layer. The thickness of the dielectric material can, however, be as large as 5 mm (5000 ⁇ m).
• the dielectric material, first layer is cut into a frame 40, by a programmed router or a punch and die set, the latter being preferred, to be of a complimentary shape to the plateau 30 on the base material.
• the dielectric material is square or rectangularly shaped on its outer perimeter 50 and is punched out in like shape to form its inner perimeter 60.
• the inner perimeter 60 is dimensioned to receive the plateau 30 of the base 10.
• the first PTFE frame layer 40 has outer perimetrical dimensions of 190 x 230 mils (4.826 x 5.842 mm), inner perimetrical dimensions of 110 x 150 mils (2.794 x 3.810 mm) and a thickness of 20 mils (508 ⁇ m).
• a lead is then provided having an outer perimetrical frame portion 80, usually in the ⁇ of a square or rectangle.
• a predetermined ; ⁇ imber of leads 100 extend inwardly and terminate where the inner ends 110 thereof define a predetermined shape 120.
• the shape defined by the inner ends 110 of the leads 100 will be substantially similar to the shape of the plateau 30 on the base metal 10 and the shape of the inner perimeter 60 of the first frame layer of dielec' .c material. More specifically, the shape defined by the inner ends 110 of the leads 100 has the same dimensions as the inner perimeter 60 of the first dielectric frame layer.
• the lead material can be any conductive material depending upon the desired application with respect to parameters such as impedance, etc. Most preferred by the present inventors is .005 inch (127 ⁇ m) thick copper, beryllium-copper alloy, iron-nickel-cobalt alloy or iron-nickel alloy (alloy 42). In the embodiment of FIGURE 1 the leads themselves, individually, are 15 x 5 mils (381 x 127 ⁇ m) with spacing between each lead being as small as 10 mils (254 ⁇ m). However, the desirable thickness range is from 100 to 250 ⁇ m.
• This thickness range is sufficient to allow the leads to retain their shape in handling and so that they can be formed for matched impedance connection to the board on which the package will be mounted.
• the length of the leads extending outside of the carrier is also important to the operation of the chip carrier. A minimum distance of .030 inch from the edge of the dielectric material 50 and 140 from which the lead emerges to its termination point 90 after bending is required. Therefore, one must take into account the thickness of the base plate and the thickness of the first dielectric frame layer 40 along with the type of mounting to be used when determining the length of lead to be used.
• a second frame layer 130 of dielectric material is placed upon the leads.
• the dimensions of the second frame layer 130 are 190 x 230 mils (4.826 x 5.842 mm) outside dimension and 140 x 180 mils (3.556 x 4.572 mm) inside dimension. It will be appreciated that the outside dimension of the second dielectric frame layer is identical to the first frame layer but the inside dimensions differ. A brief review of FIGURE 2 will reveal that this allows for the inner ends 110 of the leads to be exposed for later connection to a chip by beam lead welds or wire bonds. In most cases, the width of the exposed leads are .015 inch, however, the acceptable range is up to .030 inch.
• a direct bonding process was chosen as the method of assembly since this process fuses the dielectric in the sheet composites to each other and to the metal used in the package. Fusing the dielectric creates a sufficiently strong bond for reliable use of the product. Moreover, the use of direct bonding eliminates the compromises attendant the use of adhesives. Adhesives raise costs of production to unacceptable levels and they can compromise the thermal and electrical properties of the package. To accomplish the direct bonding, a clamp and a rapid heating/rapid cooling process are used.
• the purpose of having the temperature change rapidly is to ensure good adhesion between the surfaces and uniform embedding of the leads in the dielectric layers, without producing a lateral flow of material thus distorting the frame and widening the wall. It was determined by the inventors hereof that a 150 psi (1 MPa) pressure, applied by a frictionless clamping force, a rapid rise in temperature to about 388° C, holding the temperature at that level for a period of about 10 to 25 minutes and then rapid cooling was sufficient to embed and seal the leads in the dielectric material yet avoid deformation of the package. This operation is most preferably executed in an aluminum fixture (not shown) designed to maintain each of the component parts in register.
• the final chip carrier package is shown gene;, 'y at 132 in FIGURE 3.
• the above described method of producing the high RF and microwave chip carrier 132 provides a very cost effective and novel product where conductor losses and dielectric losses are both minimal, permittivity is low and conductor dielectric geometry can be designed for matched impedance without resorting to very small lead widths and thicknesses.
• the metal base plate 10 can be replaced by the dielectric material which is partially covered (in the area under the die which is the plateau region 30), with a conductive resin, preferably silver-epoxy resin composition. This can be done in the present invention or in prior art packages and can greatly reduce the cost of providing an adequate ground plane for the Gallium arsenide (GaAs) die. It is also within the ambit of this disclosure to produce multi-layer packages and multi-die packages.
• FIGURE 4 is a variation of the preferred embodiment.
• FIGURE 4 shows five Rf leads 100' and three DC leads 100" ; other than this difference from the embodiment in FIGURE 1 the device is the same.
• a base plate, first dielectric layer, lead frame and second dielectric layer are all used to form the embodiment of FIGURE 4.
• the difference is that the leads are shaped differently for impedance matching.
• FIGURE 5 depicts an alternative embodiment of the present invention, generally used in connection with direct broadcast satellites, where the raised plateau portion 30 of base metal 10 is smaller than the inner perimetrical dimension 60 of the first dielectric frame layer 40, whereby a gap 67 is formed between the two components in the region where they would normally engage.
• the gap formed is .005 inch wide and functions to provide flow space for the solder alloy (typically gold-tin eutectic), used to attach the die to the raised plateau, so it does not short circuit the leads.
• solder alloy typically gold-tin eutectic
• FIGURE 6 depicts a further embodiment of the invention which is a replacement for a multichip type of chip carrier wherein the overall construction is elongated. Visible in the figure are base plate 10, first dielectric frame layer 40, leads 100 and second dielectric frame layer 130. It should be noted that in this embodiment, no raised plateau region (designated as 30 in other figures) has been provided. This benefits the particular utility of this carrier by allowing layers under the chips; that is, the package is used for a small circuit board already populated with several chips.
• FIGURE 7 is a replacement for a conventional Dual-in-line package (DIP) which has been made by the method disclosed and claimed herein. Visible on the edge of FIGURE 7 are base plate 10, first dielectric frame layer 40 and second dielectric frame layer 130; leads are also depicted as 100. The embodiment in this figure is additionally covered with a metal or dielectric cover layer 170. The chief benefit of such a layer is to protect the package contents from contamination or handling damage.
• FIGURES 7a, 7b and 7c are similarly numbered and show the different plan views of FIGURE 7.
• FIGURE 8 depicts yet another embodiment of this invention with the primary difference being that the entire carrier has been placed inside of a separate cover for even greater weather resistance.
• FIGURE 8 a mounting plate 180 is shown in place of base plate 10. Mounting plate 180 laterally extends beyond the chip carrier frame to allow the carrier to be attached to a board with fasteners. ⁇ The embodiment also includes a top cover 190. This ⁇ bodiment is generally used for high power applications.
• FI RES 8a, 8b anc c show the various plan views of FIGURE 8.

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• 1994
  • 1994-10-31 JP JP7515074A patent/JPH08506454A/ja active Pending
  • 1994-10-31 EP EP95901084A patent/EP0681741A4/de not_active Withdrawn
  • 1994-10-31 WO PCT/US1994/012460 patent/WO1995015007A1/en not_active Ceased

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