EP0721188A1 - Elimination de charge résiduelle pour un dispositif de mémoire - Google Patents

Elimination de charge résiduelle pour un dispositif de mémoire Download PDF

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Publication number
EP0721188A1
EP0721188A1 EP95309478A EP95309478A EP0721188A1 EP 0721188 A1 EP0721188 A1 EP 0721188A1 EP 95309478 A EP95309478 A EP 95309478A EP 95309478 A EP95309478 A EP 95309478A EP 0721188 A1 EP0721188 A1 EP 0721188A1
Authority
EP
European Patent Office
Prior art keywords
select gates
node
switching element
conductive
select
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP95309478A
Other languages
German (de)
English (en)
Other versions
EP0721188B1 (fr
Inventor
Andrew Ferris
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Ltd
Original Assignee
SGS Thomson Microelectronics Ltd
SGS Thomson Microelectronics Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Thomson Microelectronics Ltd, SGS Thomson Microelectronics Inc filed Critical SGS Thomson Microelectronics Ltd
Publication of EP0721188A1 publication Critical patent/EP0721188A1/fr
Application granted granted Critical
Publication of EP0721188B1 publication Critical patent/EP0721188B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Definitions

  • addressing decoding circuitry may be made of two small decoders, one decoding the first set Y A ; one decoding the second set Y B .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)
EP95309478A 1994-12-29 1995-12-27 Elimination de charge résiduelle pour un dispositif de mémoire Expired - Lifetime EP0721188B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9426337 1994-12-29
GBGB9426337.3A GB9426337D0 (en) 1994-12-29 1994-12-29 Residual charge elimination for a memory device

Publications (2)

Publication Number Publication Date
EP0721188A1 true EP0721188A1 (fr) 1996-07-10
EP0721188B1 EP0721188B1 (fr) 2002-06-05

Family

ID=10766673

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95309478A Expired - Lifetime EP0721188B1 (fr) 1994-12-29 1995-12-27 Elimination de charge résiduelle pour un dispositif de mémoire

Country Status (4)

Country Link
US (1) US5734608A (fr)
EP (1) EP0721188B1 (fr)
DE (1) DE69526914D1 (fr)
GB (1) GB9426337D0 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US12150231B2 (en) 2022-09-06 2024-11-19 International Business Machines Corporation Stored energy discharge tool for component protection

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257912A2 (fr) * 1986-08-29 1988-03-02 Kabushiki Kaisha Toshiba Dispositif de mémoire statique à semi-conducteurs
EP0572240A2 (fr) * 1992-05-28 1993-12-01 Kabushiki Kaisha Toshiba Dispositif de mémoire non-volatile à semi-conducteur

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4922452A (en) * 1987-11-16 1990-05-01 Analytek, Ltd. 10 Gigasample/sec two-stage analog storage integrated circuit for transient digitizing and imaging oscillography
US5016216A (en) * 1988-10-17 1991-05-14 Waferscale Integration, Inc. Decoder for a floating gate memory
US5491658A (en) * 1991-02-13 1996-02-13 Texas Instruments Incorporated Column decoder for virtual ground memory array
JPH07111084A (ja) * 1993-10-13 1995-04-25 Oki Micro Design Miyazaki:Kk 半導体集積回路装置
US5511032A (en) * 1994-05-17 1996-04-23 Waferscale Integration, Inc. Source pre-charge system in a memory array

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0257912A2 (fr) * 1986-08-29 1988-03-02 Kabushiki Kaisha Toshiba Dispositif de mémoire statique à semi-conducteurs
EP0572240A2 (fr) * 1992-05-28 1993-12-01 Kabushiki Kaisha Toshiba Dispositif de mémoire non-volatile à semi-conducteur

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
"High density memory selection circuit", IBM TECHNICAL DISCLOSURE BULLETIN., vol. 15, no. 7, December 1972 (1972-12-01), NEW YORK US, pages 2042 - 2044, XP002001238 *

Also Published As

Publication number Publication date
US5734608A (en) 1998-03-31
GB9426337D0 (en) 1995-03-01
DE69526914D1 (de) 2002-07-11
EP0721188B1 (fr) 2002-06-05

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