EP0737366A1 - Dispositif a effect de champ - Google Patents

Dispositif a effect de champ

Info

Publication number
EP0737366A1
EP0737366A1 EP95933573A EP95933573A EP0737366A1 EP 0737366 A1 EP0737366 A1 EP 0737366A1 EP 95933573 A EP95933573 A EP 95933573A EP 95933573 A EP95933573 A EP 95933573A EP 0737366 A1 EP0737366 A1 EP 0737366A1
Authority
EP
European Patent Office
Prior art keywords
die
channel
zone
drain
floating gate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP95933573A
Other languages
German (de)
English (en)
Other versions
EP0737366B1 (fr
Inventor
Maarten Jeroen Van Dort
Andrew Jan Walker
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV, Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Priority to EP95933573A priority Critical patent/EP0737366B1/fr
Publication of EP0737366A1 publication Critical patent/EP0737366A1/fr
Application granted granted Critical
Publication of EP0737366B1 publication Critical patent/EP0737366B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/681—Floating-gate IGFETs having only two programming levels
    • H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
    • H10D30/685—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection from the channel
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D30/00—Field-effect transistors [FET]
    • H10D30/60—Insulated-gate field-effect transistors [IGFET]
    • H10D30/68—Floating-gate IGFETs
    • H10D30/6891—Floating-gate IGFETs characterised by the shapes, relative sizes or dispositions of the floating gate electrode

Definitions

  • the invention relates to a semiconductor device with a semiconductor body which is provided at a surface with a memory element comprising a field effect transistor with a source zone and a drain zone and a channel region situated between the source and drain zones, and provided with a control electrode and a floating gate electrode situated between the control electrode and the channel region and separated from the surface by an interposed gate dielectric, while means are present for providing charge on the floating gate electrode at or adjacent the source zone through generation of hot charge carriers.
  • the invention also relates to a non-volatile memory provided with a number of such memory elements arranged in a system of rows and columns. Such memories are generally known, for example, under the acronyms (E)EPROM or Flash EPROM.
  • SI-EPROM source-side injection erasable programmable read-only memory
  • the floating gate electrode is electrically charged with hot electrons which are generated by means of high electric fields at the drain side of the channel and which are injected into the floating gate through the gate oxide.
  • the Fowler-Nordheim tunnelling process is often used near the source zone for erasing.
  • an EPROM element is the speed with which the element can be programmed.
  • Conditions for an efficient charge transport to the floating gate are: an efficient generation of hot electrons in the semiconductor body; the generation of hot electrons at or very close to the boundary between semiconductor body and gate dielectric; the electric field in die gate dielectric must nromote charge transport to the floating gate.
  • hot electrons can be efficiently formed through the channel current in the transistor, given a sufficiently high voltage at the drain zone. It is much more difficult, however, to comply with two other conditions simultaneously therewith.
  • a suitable electric field may be obtained in that a comparatively high voltage is applied to the control electrode, which is usually applied above the floating gate electrode.
  • the invention has for its object inter alia to provide a less intricate, non ⁇ volatile memory cell in which the charge transport of hot charge carriers takes place at the source side of the channel and which can be manufactured in a comparatively simple manner.
  • a semiconductor device of the kind mentioned in the opening paragraph is characterized in that said means comprise a thickened portion of the gate dielectric adjoining the source zone, while the pn junction of the source zone intersects the surface of the semiconductor body below the thickened po ⁇ ion, the source zone and the floating gate electrode, seen at the surface, have edges which coincide at least substantially, and the gate dielectric at the area where the pn junction of the drain zone intersects the surface is thinner than the gate dielectric at the area of the thickened portion.
  • the thickened portion of the gate dielectric may be obtained, for example, through thermal oxidation.
  • a gate oxide then arises which becomes gradually thicker in the direction of the channel towards the source zone between the floating gate and the channel and which has a so-called bird's beak profile.
  • This profile causes in the subjacent portion of the channel an electric field component in lateral direction of sufficient value and width for supplying electrons in the channel with the required energy for transport to the floating gate electrode.
  • This charge transport is in addition favourably affected by the voltage present in situ between the control electrode and the channel which is smaller at the drain side than at the source side.
  • the oxide becomes thicker also at the drain side, unless a mask protecting against oxidation is used.
  • An embodiment which has the advantage that the oxide thickening at the drain side has no or at least substantially no influence on the field distribution in the channel is characterized in that the gate dielectric and the floating gate electrode extend to above the drain zone, while the gate dielectric has a second thickened portion which is situated above the drain zone and, seen at the surface, at a distance from the channel.
  • An embodiment in which a drain zone is obtained in a simple manner which extends to beyond the thickened oxide below the floating gate is characterized in that the drain zone is provided with an extension which extends under the second thickened portion up to the channel region.
  • the cell may be erased in various manners known per se.
  • a preferred embodiment is characterized in that the gate dielectric at the drain side of the channel has a thickness such that information stored on the floating gate electrode can be erased through tunnelling of charge carriers between the floating gate electrode and the drain zone.
  • Fig. 1 is a cross-section of a semiconductor device according to the invention.
  • Figs. 2-4 show a few stages in the manufacture of this device
  • Fig. 5 shows the lateral electric field distribution in the channel for two different gate voltages
  • Fig. 6 is a graph indicating the maximum electric field strength at the source side and at the drain side of the channel in the device of Fig. 1 ;
  • Fig. 7 is a cross-section of a second embodiment of a semiconductor device according to the invention.
  • the semiconductor device of Fig. 1 comprises a semiconductor body 1 , for example made of silicon, with a surface region 3 of a first conductivity type, in this example the p-type, adjoining a surface 2.
  • the surface region is provided with a non-volatile memory element in the form of a field effect transistor with a source zone 4, a drain zone 5, and a channel 6 situated between the source and drain zones.
  • the source zone and the drain zone are formed by n-type surface zones and are provided with a source electrode 7 and a drain electrode 8, respectively.
  • the gate electrode 9 is surrounded on all sides by electrically insulating material, so that non-volatile information in the form of electric charge can be stored on the electrode 9.
  • the device is for this purpose provided with means near the source zone 4 for generating a high electric field in the channel at the source side, in which field the electrons are accelerated.
  • these means comprise a thickened portion 13 of the gate dielectric 10, while the pn junction 25 of the source zone 4 intersects the surface 2 of the semiconductor body 1 below the thickened portion 13.
  • the mutually facing edges of the floating gate electrode and of the source zone 4 coincide at least substantially so that at least the gate electrode 4 extends over the portion of the channel adjoining the source zone below the thickened portion 13.
  • the pn junction 26 of the drain zone 5 intersects the surface 2 in a location in the channel 6 where, as is evident from Fig. 1 , the gate oxide 10 is thinner than at the area of the thickned portion 13, whereby it is avoided that large electric fields are formed also at the drain side of the channel.
  • the floating gate electrode and the control electrode are provided in the form of a stack, so that these electrodes have coinciding edges, at least in longitudinal direction of the channel, and both cover the entire channel 6 between the source zone 4 and drain zone 5.
  • the thickened portion 13 of the gate oxide may be obtained in various ways which are known per se.
  • the thickened portion 13 is formed by an oxide layer which is obtained at least partly through thermal oxidation of silicon material at the area of the source zone 4.
  • the oxide becomes gradually thicker in the direction of the channel towards the source zone 4, which is favourable for the field distribution in the channel.
  • a thickening 14 in the oxide called second thickened portion, may also be formed during this oxidation step.
  • This thickened portion is situated above the drain zone 5 at a distance from the channel 6, and accordingly has no or at least substantially no influence on the field distribution in the channel.
  • the asymmetry between source zone and drain zone is obtained in this embodiment in that the drain zone is provided with an extension 5a which is present under the second thickened portion 14 up to the channel 6.
  • the starting point is a silicon substrate 1 of which at least the surface region 3 is of the p-type with a doping concentration of 10 17 at/cm 3 .
  • the oxide layer 10 with a thickness of approximately 12 nm, forming the gate dielectric of the transistors to be manufactured, is obtained on the surface through oxidation.
  • a first, approximately 0.3 ⁇ m thick layer 15 of polycrystalline silicon (called poly hereinafter for short) is deposited by CVD and n-type doped during the deposition or in a separate doping step after the deposition.
  • the floating gate electrode 9 is manufactured from the first poly layer in a later stage.
  • First an interpoly dielectric 12 is formed on the poly layer 15.
  • This layer in a simple embodiment may be formed by a silicon oxide layer with a thickness of, for example, 25 nm. In alternative embodiments, this layer may comprise other materials, for example oxynitride or a system of various layers such as, for example, oxide-nitride-oxide (ONO).
  • Fig. 2 shows the device after the deposition of the second poly layer 16.
  • the control electrode 11 and the floating gate electrode 9 are formed from the poly layers 15 and 16 by known techniques (Fig. 3), after which phosphorus atoms are provided in the surface zone 17 through ion implantation in a self-aligned manner.
  • a thermal oxidation whereby a thickened portion of approximately 50 nm is formed below the edges of the floating gate electrode 9, extending from the edge of the gate 9 in the shape of a bird's beak to below the floating gate.
  • an oxide layer 18 is formed on the sides of the poly stack 9, 11 so as to act as a spacer or pan of a spacer during the source and drain implantation.
  • the oxide layer 19 is provided on the surface of the semiconductor body to a thickness which may be slightly smaller than the thickness of the layer 18 owing to the difference in oxidation rate between polycrystalline and monocrystalline silicon.
  • Lateral oxygen diffusion also converts silicon material below the floating gate electrode into silicon oxide, so that the oxide 14 extends to below die floating gate electrode at the edges of d e channel and is given a so-called bird's beak profile which is used for obtaining the electric field distribution in die channel.
  • the phosphorus atoms provided in the surface zone 17 diffuse further into the silicon body and form d e n-type zone 5a which extends to below the thin gate oxide 11.
  • a spacer of the desired width can be formed on die sides of die stack 9, 11, for which purpose first an oxide layer is deposited in known manner, from which the spacers are obtained by anisotropic etching-back.
  • the oxide 19 next to d e stack 9, 11 with spacer may be partly or wholly removed, which is favourable for the source and drain implantation.
  • the device is subsequenUy subjected to an implantation whereby the strongly doped n-type zones 4 and 5 are formed through doping with, for example, arsenic.
  • the spacer on the edges of die stack 9, 11 achieves that the edge of die zone 4 (Fig. 1) facing towards d e channel 6 coincides substantially with the edge of die gate electrodes 9 and 11 , so diat part of the channel 6 is situated below the thicker oxide 13 of the bird's beak.
  • the device may further be subjected to usual operations such as the provision of contact windows in ⁇ e oxide layer 14 and the provision of the contacts 7 and 8. Such operations are generally known in the field and are accordingly not described any further here.
  • Fig. 5 shows the field distribution in the channel for two different voltages at the control electrode.
  • the voltage at the drain zone is 5 V in both cases.
  • the distance d in the channel to the source zone is plotted on the horizontal axis, and d e lateral electrical field strength on the vertical axis.
  • Curve 20 shows the situation at a low gate voltage, for example, 3 V.
  • the field strength at the drain side of die channel in this case is much greater than at the source side of the channel. Hot electrons are formed, it is true, at the drain side of the channel owing to the high electric field.
  • the transport of these electrons to the floating gate is counteracted by the electric field in the gate oxide which is very weak, or even has the wrong direction owing to the voltage at the drain zone.
  • Curve 21 shows the field distribution in the channel for a much higher gate voltage at the same drain voltage, for example, a gate voltage of 10 V.
  • a strong electric field is obtained at the source side of the channel and a comparatively weak field at the drain side.
  • the electrons in the channel are now accelerated at the source side.
  • An effective charge transport to the floating gate takes place now, also owing to the high voltage between the source zone and the control electrode, whereby an electric field favouring charge transport is formed in the gate oxide.
  • Fig. 6 shows the (calculated) maximum lateral field strength at the drain side (curve 22) and at the source side (curve 23) of the channel as a function of die (floating) gate voltage for a memory cell as described herein. It is evident from the graph that the electric field strength at the drain side becomes small and that at me source side becomes great for high voltages applied to the control electrode.
  • the Fowler-Nordheim tunnelling effect may be used for erasing, at the said diickness of die diin gate oxide 10, in diat a high positive voltage is applied to d e drain zone and a low voltage to the control electrode. Under these circumstances, electrons are capable of tunnelling from the floating gate electrode dirough die gate oxide 10 to the drain zone 5.
  • the device described above may be manufactured by standard techniques from only two poly layers.
  • Fig. 7 is a cross-section of an alternative embodiment of a semiconductor device according to the invention with two poly layers for the gate electrodes.
  • the floating gate electrode 9 and d e control electrode 11 in this example do not form a stack, as in the previous example, but are defined mutually independendy in the direction of the channel length.
  • the floating gate 9 is provided on die comparatively thin gate oxide 10.
  • the control electrode 11 overlaps the floating gate electrode 9 and extends on either side of the floating gate electrode over the thickened portions 13 and 14 of the gate oxide.
  • the edge of the source zone 4 again substantially coincides widi the edge of die floating gate electrode 11 , so d at again a strong electric field can be generated below die adjoining portion 13 of die gate oxide, in which field hot charge carriers are formed for me purpose of writing.
  • the formation of peaks in the field distribution at die drain side of the channel 6 is prevented by means of the drain extension 5a.
  • the d ickening of the gate dielectric may be obtained in a manner other than by means of an oxidation step, for example, by means of deposition and photolithography.
  • Mechanisms other than the tunnelling effect may be used for erasing, for example, injection of holes into the floating gate electrode. These holes may be formed through avalanche breakdown of the pn junction of the drain zone and compensate for the electron charge on the floating gate.

Landscapes

  • Non-Volatile Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

L'invention concerne une mémoire (E)EPROM dans laquelle l'information est introduite par des électrons chauds générés dans le courant de canal au niveau du côté source du canal plutôt que du côté drain, comme c'est habituellement le cas. Afin de réaliser la répartition du champ électrique nécessaire à cette opération dans le canal (6), l'oxyde de grille (10) est pourvu d'une partie épaissie (13) contiguë à la zone source (4), de façon à induire localement un champ électrique latéral puissant dans le canal à des tensions de grille plus élevées. Un transport efficace de charge d'électrons vers la grille flottante (9) s'effectue à travers ce champ électrique latéral dans le canal et à travers le champ électrique relativement élevé dans l'oxyde de grille. La partie épaissie de l'oxyde de grille peut s'obtenir simplement par oxydation thermique. Afin d'empêcher la création de champs puissants au niveau du côté drain du canal, le drain est, de préférence, pourvu d'une structure LDD (5a) contiguë à l'oxyde de grille mince. De ce fait, l'effet tunnel de Fowler-Nordheim à travers cet oxyde de grille mince peut également s'utiliser pour l'effacement.
EP95933573A 1994-10-28 1995-10-20 Dispositif a effect de champ Expired - Lifetime EP0737366B1 (fr)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP95933573A EP0737366B1 (fr) 1994-10-28 1995-10-20 Dispositif a effect de champ

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
EP94203146 1994-10-28
EP94203146 1994-10-28
EP95933573A EP0737366B1 (fr) 1994-10-28 1995-10-20 Dispositif a effect de champ
PCT/IB1995/000897 WO1996013863A2 (fr) 1994-10-28 1995-10-20 Dispositif a effect de champ

Publications (2)

Publication Number Publication Date
EP0737366A1 true EP0737366A1 (fr) 1996-10-16
EP0737366B1 EP0737366B1 (fr) 2002-04-10

Family

ID=8217325

Family Applications (1)

Application Number Title Priority Date Filing Date
EP95933573A Expired - Lifetime EP0737366B1 (fr) 1994-10-28 1995-10-20 Dispositif a effect de champ

Country Status (7)

Country Link
US (1) US5828099A (fr)
EP (1) EP0737366B1 (fr)
JP (1) JP3762433B2 (fr)
KR (1) KR100350819B1 (fr)
DE (1) DE69526328T2 (fr)
TW (1) TW490082U (fr)
WO (1) WO1996013863A2 (fr)

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US5837584A (en) * 1997-01-15 1998-11-17 Macronix International Co., Ltd. Virtual ground flash cell with asymmetrically placed source and drain and method of fabrication
US6417539B2 (en) * 1998-08-04 2002-07-09 Advanced Micro Devices, Inc. High density memory cell assembly and methods
US6172392B1 (en) * 1999-03-29 2001-01-09 Vantis Corporation Boron doped silicon capacitor plate
US6060742A (en) * 1999-06-16 2000-05-09 Worldwide Semiconductor Manufacturing Corporation ETOX cell having bipolar electron injection for substrate-hot-electron program
US6087695A (en) * 1999-08-20 2000-07-11 Worldwide Semiconductor Mfg Source side injection flash EEPROM memory cell with dielectric pillar and operation
US6521958B1 (en) * 1999-08-26 2003-02-18 Micron Technology, Inc. MOSFET technology for programmable address decode and correction
US6518122B1 (en) * 1999-12-17 2003-02-11 Chartered Semiconductor Manufacturing Ltd. Low voltage programmable and erasable flash EEPROM
US6933554B1 (en) * 2000-07-11 2005-08-23 Advanced Micro Devices, Inc. Recessed tunnel oxide profile for improved reliability in NAND devices
US6674667B2 (en) * 2001-02-13 2004-01-06 Micron Technology, Inc. Programmable fuse and antifuse and method therefor
US20020185673A1 (en) 2001-05-02 2002-12-12 Ching-Hsiang Hsu Structure of a low-voltage channel write/erase flash memory cell and fabricating method thereof
CN1293640C (zh) * 2001-06-11 2007-01-03 力晶半导体股份有限公司 无接触点信道写入/抹除的闪存存储单元结构与制造方法
DE60226571D1 (de) * 2002-02-20 2008-06-26 St Microelectronics Srl Elektrisch programmierbare nichtflüchtige Speicherzelle
EP1349205A1 (fr) * 2002-03-28 2003-10-01 eMemory Technology Inc. Structure de cellule de mémoire FLASH à écriture/effacement depuis le canal à basse tension et son procédé de fabrication
KR100628642B1 (ko) * 2004-12-31 2006-09-26 동부일렉트로닉스 주식회사 고전압 모스 트랜지스터 및 고전압 모스 트랜지스터의형성방법
US7361551B2 (en) * 2006-02-16 2008-04-22 Freescale Semiconductor, Inc. Method for making an integrated circuit having an embedded non-volatile memory
CN103633118B (zh) * 2012-08-24 2016-12-21 上海华虹宏力半导体制造有限公司 浮栅电可擦除型只读存储器及制造方法

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Also Published As

Publication number Publication date
EP0737366B1 (fr) 2002-04-10
DE69526328D1 (de) 2002-05-16
KR100350819B1 (ko) 2003-01-15
WO1996013863A3 (fr) 1996-06-27
WO1996013863A2 (fr) 1996-05-09
JP3762433B2 (ja) 2006-04-05
DE69526328T2 (de) 2002-11-21
TW490082U (en) 2002-06-01
JPH09507616A (ja) 1997-07-29
US5828099A (en) 1998-10-27

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