EP0772818A1 - Appareil et procede pour executer des instructions pop - Google Patents

Appareil et procede pour executer des instructions pop

Info

Publication number
EP0772818A1
EP0772818A1 EP96916800A EP96916800A EP0772818A1 EP 0772818 A1 EP0772818 A1 EP 0772818A1 EP 96916800 A EP96916800 A EP 96916800A EP 96916800 A EP96916800 A EP 96916800A EP 0772818 A1 EP0772818 A1 EP 0772818A1
Authority
EP
European Patent Office
Prior art keywords
stack
stack pointer
memory
pointer value
pop instruction
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96916800A
Other languages
German (de)
English (en)
Inventor
Mario Nemirovsky
Alexander Perez
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Semiconductor Corp
Original Assignee
National Semiconductor Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Semiconductor Corp filed Critical National Semiconductor Corp
Publication of EP0772818A1 publication Critical patent/EP0772818A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/34—Addressing or accessing the instruction operand or the result ; Formation of operand address; Addressing modes
    • G06F9/355—Indexed addressing
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3004—Arrangements for executing specific machine instructions to perform operations on memory

Definitions

  • the present invention relates to a POP instruction used by a microprocessor to transfer the data 5word on the top of the stack to an internal register, and more specifically, to an apparatus and method for computing a POP instruction compatible with an Intel 486TM microprocessor in significantly fewer clock cycles than is currently required by that processor.
  • microprocessors organize the memory in a manner which partitions it into multiple, lQindependent address spaces.
  • independent spaces are assigned to store a program's code, data to be used in executing the program, and a stack.
  • the stack is a segment of memory containing a dynamic, sequential list of data and having the capability to be accessed from one end.
  • the stack is used to store return addresses, parameters passed by a calling routine, and temporary variables assigned by a routine.
  • a POP instruction is used by a microprocessor to transfer the word or doubleword located at the 15current top of the stack to the register location indicated by a destination operand provided when executing the instruction.
  • the register which indicates the current top of the stack (the SP or stack pointer register) is then incremented to point to the new memory address corresponding to the top of the stack.
  • the POP instruction thus has the effect of moving the word at the top of the stack to a register or memory.
  • the POP instruction requires 4 clock cycles in order to transfer the word or doubleword at the top of the stack to a register.
  • the POP instruction is a commonly used instruction (comprising as much as 4% of the executed instructions according to some estimates), the amount of time spent executing this one instruction can become a significant factor in the speed with which a program can be executed.
  • the present invention is directed to an apparatus and method for implementing a POP instruction to transfer data from the top of the stack to an internal register in a more efficient manner than carried out by current microprocessors, particularly the Intel 486TM.
  • a reduction in the number of clock cycles required to 3Cexecute a POP instruction is achieved by a microprocessor architecture which enables the basic operations of the POP instruction to be executed in a single clock cycle.
  • the POP instruction consists of two basic operations: (1) a read operation of the memory using an address formed from the current stack pointer value and stack base address; and (2) incrementing the stack pointer value by either 2 or 4, depending upon the size of the operand.
  • the microprocessor architecture of the 35present invention uses two arithmetic logic units which function as adders to execute both of the POP operations in a single clock cycle. This provides a significant decrease in the time required to execute a POP instruction in an Intel 486TM compatible microprocessor.
  • Fig. 1 is a block diagram of the architecture of a microprocessor which includes apparatus for efficiently computing a POP instruction according to the method of the present invention.
  • Fig. 2 is a detailed diagram showing the portions of the architecture of the microprocessor of Fig. 1 5which are used in executing a POP instruction according to the method of the present invention.
  • Fig. 1 is a block diagram of the architecture of a microprocessor 1 which includes apparatus for efficiently computing a POP instruction according to the method of the present invention.
  • the microprocessor architecture employs a three stage pipeline using microprogrammed control.
  • the three primary stages of the lCpipeline are the decode, execute and writeback stages.
  • the writeback stage is further divided into two substages.
  • the second writeback substage is used for some of the memory accesses.
  • This architecture has the benefit of needing only three stages for register to register operations.
  • the decode stage contains the decode unit 10, but the stage functions as more than just an instruction decoder.
  • This stage also includes the prefetch buffer 12, the instruction cache 14, and the l ⁇ microsequencer 16.
  • Prefetch buffer 12 is 16 bytes wide and is designed as a two tier unit.
  • Prefetch unit 12 acts to keep instruction decoder 10 fully supplied with all the bytes of the instruction it is currently decoding.
  • Prefetch unit 12 interfaces with instruction cache 14, and is designed to fetch ahead of the decode stage. This look ahead mechanism improves the efficiency with which the processor operates.
  • Instruction cache 14 contains 1 K bytes organized as a direct map with a line size of 8 bytes. 2CCache 14 checks on the bus to avoid stale data due to self modifying code. A 1 K byte size cache provides a significant performance improvement, and is particularly effective for executing small groups of application code.
  • Decoder 10 is capable of decoding simple instructions in a single cycle. Prefixes and complex instructions can take more than one cycle to decode. Microsequencer 16 steps through the decoded microcode for the instructions. Most of the microcode is stepped through in a single cycle except for complex instructions, 25which include the ones needed to support the protection mechanism of the 486TM microprocessor.
  • the execute stage not only fetches operands and executes the instructions, but also completes the memory addresses.
  • the 486TM architecture has a segmented address space, with many complex addressing modes being used to access this space.
  • a segmented memory space means that to obtain the physical address that actually goes on the bus, at least one addition must be performed, that of the segment base and the 30offset within that segment. This can be further complicated by the computation of the segment offset, which can have up to three parts; a base, an index, and a displacement.
  • Execution unit 18 is capable of performing the entire address computation in a single cycle. As will be discussed later, this is a result of being able to perform two addition operations in a single clock cycle. Segment limit checking is also done at this point to prevent segment overruns.
  • the linear address thus computed 35 (which is also the physical address in this case) is sent to bus unit 20 for dispatch to the external world. As will be described in greater detail later, this design allows the single cycle execution of frequently used load, store, push and pop instructions.
  • the execute stage also utilizes the architectural register file 22 and protection logic unit 24.
  • Register file 22 resolves the source and destination information for all the operations in the execute stage. It 40 also allows bypassing of results either from the output of the arithmetic and logic unit (ALU), or from a load operation from memory. This helps to reduce pipeline backups due to data dependencies.
  • ALU arithmetic and logic unit
  • the writeback stage includes bus interface unit 20, debug logic unit 26 and register writeback logic.
  • the memory access is initiated and completed.
  • the register file update is also performed.
  • the second writeback substage permits the completion of an independent register operation, out of order, while a memory write access is pending.
  • the memory access is pipelined, which allows a new read/write operation to be initiated every cycle.
  • the microprocessor core is divided into 11 blocks to reduce the complexity of the design. These blocks are the prefetch unit 12, decoder unit 10, microsequencer 16, register file unit 22, 5execution unit 18, protection logic unit 24, exception logic unit 28, debug logic unit 26, bus unit 20, global control unit 30, and instruction cache 14.
  • Prefetch unit 12 consists of two eight byte registers that are filled in from either instruction cache 14 or directly from memory.
  • Decode unit 10 gets an instruction from prefetch unit 12 and generates the entry microcode address for the instruction, register addresses, immediate values, displacement values and segment lQnformation. Decoder 10 also generates information for some of the exceptions.
  • Microsequencer 16 controls the process of stepping through the instruction microcode. It generates the next microcode address and performs the look ups in the micro(code) ROM.
  • the micro-ROM address can come from decoder 10 if a new instruction is started, from the microcode if the present instruction is not finished, or from exception logic unit 28 in the case of exceptions.
  • Register file unit 22 reads the operands, resolves the bypasses, generates constants, and aligns operands for an instruction.
  • the architecture registers and the selectors i.e., the segment lookup registers
  • Register file 22 has dual read and write ports.
  • Registers contained in register file unit 22 can be accessed either as a single byte, a word (2 bytes), or a doubleword (4 bytes). This ability is the basis for the use of dual read and write ports.
  • the dual write ports are used to optimize load instructions and for 2Qsimultaneous completion of instructions.
  • Execution unit 18 has two major functions. One is to perform all the arithmetic and logic operations. For this function, execution unit 18 has an arithmetic and logic unit and a barrel shifter. The second function(s) of execution unit 18 are address computation (linear address generation) and limit checking. The design of this unit allows computation of the address offset, linear address, and limit checking in a single clock 25cycle.
  • Bus unit 20 is the interface of the core to the external world. An important feature of this unit is the ability to support pipelined memory access where a memory access is initiated before the previous one has finished.
  • the external DRAMs which constitute the memory are divided into pages, typically 4 K bytes long. As long as an access is within one page in the DRAM, single cycle reads and writes to memory can 30be sustained. If a page miss occurs, then it takes 3 cycles to complete that access. DRAM, SRAM and ROM accesses can also be supported with wait states and non-pipelined memory accesses.
  • Global control unit 30 is the supervisor of the entire architecture. This unit controls the stepping of the instruction pipeline. Interlocks, control of the exception handling, and process shutdown are also handled by this unit. Exception logic unit 28 prioritizes and resolves all the exceptions and external interrupts. This 3Sncludes the software interrupts, arithmetic exceptions, protected mode exceptions, and other faults and traps. Protection logic unit 24 is responsible for the protection mechanism defined in the Intel 486TM implementation. This unit is required for the implementation of the segmented memory architecture of the 486TM.
  • Debug logic unit 26 includes all the debug registers and implements the instruction and data breakpoints. Debug logic unit 26, along with bus unit 20, also implements the requirements for the external ICE 4C(in circuit emulation) support.
  • Fig. 2 is a detailed diagram showing the portions of the architecture of the microprocessor of figure 1 which are used in executing a POP instruction according to the method of the present invention.
  • register file 22 provides a stack pointer (SP) value as an input to element 52.
  • the stack pointer is a value corresponding to an offset from a base address in the stack to the top-of-stack 45(TOS) in the currently accessed stack segment.
  • the base address of the first memory location in the currently accessed stack is contained in the stack segment base (SS) in register 46.
  • SS stack segment base
  • the address [SS:SP] describes the location of the top of the stack segment whose starting memory location is identified by the contents of the SS base register.
  • Element 52 is shown as a two-input-single-output logic element or switch. It typically takes the form of a data multiplexer, with control logic selecting which of the two inputs to route out of the element as the output.
  • the control logic for selecting the desired output is typically contained in a register file control unit (not shown).
  • the second input to element 52 is provided along path 60. This signal "bypasses" the return loop to register 22, and is used when executing sequential POP instructions. This aspect of the present invention will be lOdiscussed in greater detail later.
  • the output of element 52 is provided as an input to arithmetic logic unit (ALU) 40.
  • ALU 40 is principally used to implement adding operations.
  • the second input to ALU 40 is provided along the data path which includes element 44.
  • Element 44 is a memory unit hich provides a constant whose value is to be used to increment the stack pointer.
  • 15value of the constant used in any particular execution cycle depends upon the size of the data words being accessed. In most situations element 44 will provide a value of +2 for word sized operands and +4 for doubleword sized operands.
  • ALU 40 performs an add operation on its two inputs, with the resulting output serving as the incremented value of the stack pointer (SP).
  • ALU 40 As noted, the output of element 52 is provided as an input to ALU 40. It is also provided as an input to arithmetic logic unit (ALU) 42. In the preferred embodiment of the present invention, ALU 42 is principally used to implement adding operations. A second input to ALU 42 is the stack segment base address provided by register 46.
  • ALU 42 performs an add operation on its two inputs, thereby adding the base value and offset to obtain the address in memory 50 of the data located at the top of the stack. The output of ALU 42 is then used to access memory 50. As indicated by the dotted line in figure 2, memory 50 is typically external to the microprocessor elements shown in the figure. As noted, the output value of ALU 42 corresponds to the address [SS:SP] of the top of the stack, and thus is the location of the data to be written to register 22.
  • a processing unit constructed as is described with reference to figure 2 is capable of executing a POP instruction in a single clock cycle. This is accomplished by the use of ALUs 40 and 42, which perform the steps of: (1) calculating the address in memory of the top of the
  • the apparatus of figure 2 produces the outputs of both ALU 40 and ALU 42.
  • the output of ALU 40 is stored in register 54.
  • This value is the incremented stack pointer which is used to indicate the new location of the data at the top of the stack when executing the next POP instruction.
  • the value stored in register 54 takes each of
  • the value provided along data path 60 is used as the output of element 52 in the situation where
  • control logic recognizes the existence of sequential POP instructions and causes the data along path 60 to be output by element 52.
  • a single clock cycle is all that is necessary for the incremented stack pointer to be passed from register 54 to ALU 40. This permits ALU 40 to be loaded with the (incremented) stack pointer in the clock cycle after the add operation performed by ALU 40, rather than having to wait another clock cycle to have the stack pointer retrieved from register 22.
  • an apparatus and method of executing a POP instruction in a single clock cycle has been described.
  • This apparatus and method can be used to execute a compatible POP instruction for many types of microprocessors, in particular an Intel 486TM microprocessor.
  • the present invention accomplishes this goal by using two ALUs to calculate the memory address of the top of the stack from the stack pointer and stack segment base and increment the stack pointer during the same clock cycle.
  • the lQresult is an apparatus and method for executing a POP instruction in significantly fewer clock cycles than required by microprocessors such as the Intel 486TM. This can speed up the execution of many application programs which frequently utilize POP instructions.

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Mathematical Physics (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

L'invention concerne un appareil et un procédé pour exécuter des instructions POP pour assurer un transfert de données depuis le haut de la pile vers un registre interne avec plus d'efficacité que les microprocesseurs de la technique actuelle. La réduction du nombre de cycles d'impulsions d'horloge nécessaires pour exécuter une instruction POP est assurée par une architecture de microprocesseur permettant l'exécution des instructions POP en un seul cycle d'horloge. L'architecture du microprocesseur selon la présente invention utilise deux unités logiques fonctionnant comme additionneurs pour exécuter les deux opérations POP (une opération de lecture de la mémoire à l'aide d'une valeur du pointeur de pile et de l'adresse de la base de la pile, et une augmentation de la valeur du pointeur de pile) en un seul cycle d'horloge. Cela permet de réaliser des gains de temps lors des exécutions des instructions POP.
EP96916800A 1995-05-26 1996-05-24 Appareil et procede pour executer des instructions pop Withdrawn EP0772818A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US45208095A 1995-05-26 1995-05-26
US452080 1995-05-26
PCT/US1996/008052 WO1996037828A1 (fr) 1995-05-26 1996-05-24 Appareil et procede pour executer des instructions pop

Publications (1)

Publication Number Publication Date
EP0772818A1 true EP0772818A1 (fr) 1997-05-14

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP96916800A Withdrawn EP0772818A1 (fr) 1995-05-26 1996-05-24 Appareil et procede pour executer des instructions pop

Country Status (3)

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EP (1) EP0772818A1 (fr)
KR (1) KR970705077A (fr)
WO (1) WO1996037828A1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6654871B1 (en) * 1999-11-09 2003-11-25 Motorola, Inc. Device and a method for performing stack operations in a processing system

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3461434A (en) * 1967-10-02 1969-08-12 Burroughs Corp Stack mechanism having multiple display registers
US3786432A (en) * 1972-06-20 1974-01-15 Honeywell Inf Systems Push-pop memory stack having reach down mode and improved means for processing double-word items
GB2138182B (en) * 1983-04-14 1986-09-24 Standard Telephones Cables Ltd Digital processor

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9637828A1 *

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Publication number Publication date
WO1996037828A1 (fr) 1996-11-28
KR970705077A (ko) 1997-09-06

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