EP0778558A2 - Spaltensteuerschaltung für eine Flüssigkristallanzeige mit Raster-Tastverhältnis-Steuerung - Google Patents

Spaltensteuerschaltung für eine Flüssigkristallanzeige mit Raster-Tastverhältnis-Steuerung Download PDF

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Publication number
EP0778558A2
EP0778558A2 EP96308500A EP96308500A EP0778558A2 EP 0778558 A2 EP0778558 A2 EP 0778558A2 EP 96308500 A EP96308500 A EP 96308500A EP 96308500 A EP96308500 A EP 96308500A EP 0778558 A2 EP0778558 A2 EP 0778558A2
Authority
EP
European Patent Office
Prior art keywords
lcd
driver
data
levels
pixel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96308500A
Other languages
English (en)
French (fr)
Other versions
EP0778558A3 (de
Inventor
Kai Pui c/o Varitronix Limited Ho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Varintelligent BVI Ltd
Original Assignee
Varintelligent BVI Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Varintelligent BVI Ltd filed Critical Varintelligent BVI Ltd
Publication of EP0778558A2 publication Critical patent/EP0778558A2/de
Publication of EP0778558A3 publication Critical patent/EP0778558A3/de
Withdrawn legal-status Critical Current

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    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2230/00—Details of flat display driving waveforms
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/2007—Display of intermediate tones
    • G09G3/2018—Display of intermediate tones by time modulation using two or more time intervals

Definitions

  • the invention relates to a driver, particularly to an LCD driver with no variable level output for achieving a variable voltage level driving of an LCD.
  • LCDs Certain liquid crystal displays (LCDs) driven by different levels will generally have different responses. For example:
  • a driver for a liquid crystal display comprising fixed preset drive voltage levels and means for varying an ON:OFF ratio over a number of cycles, whereby effectively to present variable driving voltage levels for driving an LCD.
  • the means may comprise a circuit inserted between a controller output of the driver and an input of a column driver of the LCD.
  • the column driver may comprise a serial input column driver.
  • the driver may include a decoder for data, a frame controller for the LCD and a data selector adapted to receive input from the decoder and data controller and having a multi-level routing circuit for outputting to the column driver.
  • the data selector may comprise x different levels and may be adapted to operate over N levels of response, where N is less than x .
  • one complete cycle may last x frames.
  • the value x may be 16.
  • the effective output voltage applied to an LCD pixel may be p/p+q, where p is the number of times the pixel is driven ON and q the number of times the pixel is driven OFF.
  • Voltage waveforms driving multiplexed displays are usually pre-determined multi-level waveforms.
  • the term "voltage level” refers to the effective voltage levels of such complex waveforms, not levels in a multi-level waveform. Sometimes this is also known as the root-mean-square (RMS) voltage as an LCD is believed to respond to RMS value of driving voltage.
  • RMS root-mean-square
  • a driver 1 for a liquid crystal display comprises fixed preset voltage levels 2, and means 3 for varying an ON:OFF ratio over a number of cycles whereby effectively to present variable driving voltage levels 4 for driving an LCD (not shown).
  • Fig. 1 An example of how to drive a 64 (column) X 16 (row) dot matrix display is illustrated in Fig. 1.
  • the arrangement is applicable to any dot-matrix displays of different resolutions.
  • the controller can either be a dedicated LCD controller or it can be a general purpose system designed to control an LCD.
  • the controller accepts commands and displays data from the host system via the interface bus.
  • Typical interface signals are: data bus (DO - D7, 8-bit data bus shown) of appropriate width, enable signal (E) serving to indicate to the controller that it owns the interface bus, read/write (R/W), reset (RES), command or data input (AO).
  • Typical commands are numbers of ways of multiplex, number of segments, frame speed, clear entire display, etc. The controller upon receiving the commands will configure itself accordingly.
  • the minimum amount of SRAM in the example is 64 x 16 bits.
  • the RAM is organised as 16 rows of 64 bit each, corresponding to the display pixels, and "1" will mean ON and " o " will mean OFF.
  • typical output signals of the controller are the output data bus, consisting of a 4-bit bus (DO o - DO3), start of frame signal (FRM), row advance signal (CL1), valid data for display (CL2) and phase of driving voltage (M). This last signal signifies to the row and column drivers to use alternate positive and negative phases of driving waveform to eliminate DC components.
  • a frame is completed when every pixel of a display has been driven once.
  • FRM and CL1 will signify start of first row.
  • the row driver will output ON (select) signal to row 1 and OFF (non-select) signal to other rows.
  • Subsequent CL1 will advance the driving to subsequent rows. For instance, second CL1 will cause row 2 to be driven ON and other rows OFF, etc.
  • CL1 and CL2 will cause the data bits DO o to DO3 to be latched onto the first 4 locations of the data register of the column driver. Subsequent CL2 will cause subsequent DO o to DO3 to be latched to the second 4 locations of the data register.
  • shift registers are used such that earlier latched data are shifted left, say, by 4 bits and the latest data are latched to the last 4 bits.
  • CL2 signals as in this example, all 64 bits of data for one row of display are in the data register in their proper locations.
  • the next CL1 signal will cause this row of data to be latched by the display register to drive the row of selected display.
  • the data register is ready to accept the next row of data, 4 bits at a time, from the controller.
  • Fig. 4 The timing relationship of the signals M, FRM, CL1 and CL2 are illustrated in Fig. 4. Shifting and latching of data by the column driver from the controller is not limited to 4 bits. In fact, it can be from 1 bit to any number of bits. Here 4 bits is used as an example, Fig. 1.
  • Fig 2 there is shown how an LCD controller and drivers not ordinarily used for variable effective voltage level outputs can be used to drive an LCD to produce responses as though variable effective voltage level drives are present.
  • the controller and drivers can only output voltages either to drive a pixel ON or OFF.
  • a driver embodying the invention will cater for cases when the pixel is required to be driven with effective voltage levels between and including ON and OFF. The phenomenon described above is used.
  • the circuit 3 is inserted between the controller output and the column driver input. The circuit receives the data signifying the desired voltage levels to drive the pixel from the controller and transform these data to a series of outputs.
  • the size of RAM is increased to 16 rows of 256 bit per row.
  • every 4 bits of data will signify from OFF to full ON in 16 levels depending on the bit patterns.
  • pattern oooo means full OFF
  • ooo 1 means driving the LCD at 1/16 of the full ON voltage level, and so on.
  • Other coding methods or no coding are also possible.
  • the controller is programmed to expect 16 line of 256 display format. It will output a CL1 signal after outputting every 256 bit of data, and a FRM signal every 16 lines.
  • the LCD display being driven is still 16 lines of 64 bits.
  • Using a monochrome LCD only the contrast ratio is changed when driven by different effective voltages.
  • the driver can drive other properties of an LCD responding to different effective voltage levels.
  • An example of this is colour LCD, namely if an LCD changes colour when driven by different effective voltage levels.
  • the circuit 3 is inserted between the controller and the column driver to effect an effective variable driving voltage level.
  • the circuit 3 (CIRC) will intercept the 4 bit data output by the controller each CL2 strobe. Each such 4-bit data will be interpreted as signifying voltage levels to be applied to the LCD pixel. Assuming no coding is used in the 4 bit data, namely the pixel is driven ON or OFF in accordance with bit patterns being "1" or " o ".
  • the CIRC 3 will sequentially output DO o , DO1, DO2 or DO3 to the column driver at each frame. Initially, during the whole of the first frame, DO o is routed to the column driver 4. This can be achieved by usual circuits such as a 4-to-1 multiplexer or any other signal routing circuits.
  • bits OO, 04, 08 ..., 10, 14... in RAM are fed to the column driver 4 during this frame. This lasts until a new FRM signal is received.
  • DO1 will be output to the column driver 4, namely, bits 01, 05, 09,... 11, 16, 19... in RAM are fed to the column driver 4.
  • DO2 and DO3 will be used in sequence after each FRM signal. Then, the cycle repeats. If the 4 bits (OO, 01, 02, & 03 for the first pixel for instance) for the pixel is oooo, then the pixel will be driven OFF in all 4 frames. If the bits are 1 o 1 o , say, then the pixel will be driven ON in two of the frames and OFF in the other two frames and thus will appear half ON. If the 4 bits are 1111, then the pixel is driven full ON in all 4 frames and will appear full ON. The cycle lasts over 4 frames.
  • the levels can be from 0, 1/4, 1/2, 3/4 and 1.
  • the column driver 4 in the embodiment is a serial input type, namely, accepting 1 bit data each CL2 strobe, instead of 4-bit data as described above.
  • a total of 16 levels can be represented and a decoder 5 can be inserted before the now 16-to-1 signal routing circuit.
  • the decoder 5 will accept the 4 bit input at each CL2 strobe and present 16 outputs to the signal routing circuit. If the 4 bit inputs are oooo, then all 16 outputs can be o 's. If the 4 bit inputs are ooo 1 , then only one of the 16 outputs will be 1 with all others being o. If the 4 bit inputs are oo 1 o, then two of the 16 outputs will be 1's with the others being o , and so on.
  • a 4 bit pattern of all 1's will cause all 16 outputs to be 1's and the pixel is driven ON in every frame.
  • the exact decoder circuit required will depend on the coding on the 4 bit input data.
  • One complete cycle will now last 16 frames. This is illustrated in Fig. 3. It should be noted that, although the example in Fig. 3 uses 4 bit data to implement a 16 to 1 demultiplexor, N bit data can be used to implement a 2 N to 1 demultiplexor, where N is any integer. N is not limited to 4 bits.
  • a driver as hereinbefore described with reference to the accompanying drawings thus provides a way drivers without variable output voltage levels can be used to drive an LCD requiring variable voltage levels.
  • the driver can drive a dot matrix driving arrangement from fixed output voltage levels, thereby achieving a relatively inexpensive, flexible driver.

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  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Liquid Crystal (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
EP96308500A 1995-11-27 1996-11-25 Spaltensteuerschaltung für eine Flüssigkristallanzeige mit Raster-Tastverhältnis-Steuerung Withdrawn EP0778558A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB9524193 1995-11-27
GBGB9524193.1A GB9524193D0 (en) 1995-11-27 1995-11-27 A driver

Publications (2)

Publication Number Publication Date
EP0778558A2 true EP0778558A2 (de) 1997-06-11
EP0778558A3 EP0778558A3 (de) 1998-02-04

Family

ID=10784492

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96308500A Withdrawn EP0778558A3 (de) 1995-11-27 1996-11-25 Spaltensteuerschaltung für eine Flüssigkristallanzeige mit Raster-Tastverhältnis-Steuerung

Country Status (5)

Country Link
EP (1) EP0778558A3 (de)
KR (1) KR970029309A (de)
GB (2) GB9524193D0 (de)
SG (1) SG54392A1 (de)
TW (1) TW337579B (de)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3339492B2 (ja) * 2000-05-10 2002-10-28 日新電機株式会社 イオン源の運転方法およびイオンビーム照射装置

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0193728B1 (de) * 1985-03-08 1992-08-19 Ascii Corporation Anzeigesteuersystem
FR2621728B1 (fr) * 1987-10-09 1990-01-05 Thomson Csf Systeme de visualisation d'images en demi-teintes sur un ecran matriciel
US5196839A (en) * 1988-09-16 1993-03-23 Chips And Technologies, Inc. Gray scales method and circuitry for flat panel graphics display
JPH0720821A (ja) * 1993-06-24 1995-01-24 Internatl Business Mach Corp <Ibm> 多階調薄膜トランジスタ液晶表示装置
JP3275991B2 (ja) * 1994-07-27 2002-04-22 シャープ株式会社 アクティブマトリクス型表示装置及びその駆動方法

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
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Also Published As

Publication number Publication date
TW337579B (en) 1998-08-01
EP0778558A3 (de) 1998-02-04
GB2307584A (en) 1997-05-28
SG54392A1 (en) 1998-11-16
GB9624443D0 (en) 1997-01-15
GB9524193D0 (en) 1996-01-31
KR970029309A (ko) 1997-06-26

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