EP0780888B1 - Méthode de fabrication d'une électrode de porte pour une structure MOS - Google Patents

Méthode de fabrication d'une électrode de porte pour une structure MOS Download PDF

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Publication number
EP0780888B1
EP0780888B1 EP96119052A EP96119052A EP0780888B1 EP 0780888 B1 EP0780888 B1 EP 0780888B1 EP 96119052 A EP96119052 A EP 96119052A EP 96119052 A EP96119052 A EP 96119052A EP 0780888 B1 EP0780888 B1 EP 0780888B1
Authority
EP
European Patent Office
Prior art keywords
layer
spacer
gate electrode
gate
electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP96119052A
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German (de)
English (en)
Other versions
EP0780888A3 (fr
EP0780888A2 (fr
Inventor
Bernhard Dr. Lustig
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP0780888A2 publication Critical patent/EP0780888A2/fr
Publication of EP0780888A3 publication Critical patent/EP0780888A3/fr
Application granted granted Critical
Publication of EP0780888B1 publication Critical patent/EP0780888B1/fr
Anticipated expiration legal-status Critical
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/011—Manufacture or treatment of electrodes ohmically coupled to a semiconductor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D64/00—Electrodes of devices having potential barriers
    • H10D64/01—Manufacture or treatment
    • H10D64/013—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator
    • H10D64/01302—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H10D64/01304—Manufacture or treatment of electrodes having a conductor capacitively coupled to a semiconductor by an insulator the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H10D64/01326—Aspects related to lithography, isolation or planarisation of the conductor
    • H10D64/01328—Aspects related to lithography, isolation or planarisation of the conductor by defining the conductor using a sidewall spacer mask, a transformation under a mask or a plating at a sidewall
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/942—Masking
    • Y10S438/947—Subphotolithographic processing

Definitions

  • Short-channel MOS structures especially short-channel MOSFETs, are required for fast switching.
  • Short-channel MOSFETs have a short gate length. At low operating voltages become small with short-channel MOS transistors Gate delay times achieved.
  • Gate electrodes are usually made by structuring a conductive layer using a photolithographic generated mask formed. Gate electrodes with dimensions below 100 nm as required for short-channel MOS transistors are using optical lithography no longer to be structured. For these structure sizes, Example currently the use of electron beam lithography required.
  • the problem underlying the invention is a further method for producing a gate electrode for a MOS structure specify with the structure sizes in the gate electrode less than the resolution limit of the lithography used can be achieved.
  • the gate electrode formed by structuring an electrode layer.
  • the lateral expansion of the gate electrode is by a spacer determined from the same material as the gate electrode is formed.
  • a hard mask is formed to structure the gate electrode is used.
  • the spacer made of the same material becomes simultaneous with removed. A separate step to remove the Spacers are therefore no longer required. Nevertheless, the gate electrode is im essentially vertical flanks.
  • the spacer is preferred on a flank of a step by depositing a layer with a conformal edge covering and then anisotropically etching the layer.
  • the stage is created in an auxiliary layer that covers the surface the electrode layer covered.
  • the auxiliary layer is continuously produced from one and the same material.
  • the level of the step is set via the etching time when the step is formed. This has the advantage that only one etching process is required to form the hard mask.
  • the auxiliary layer is preferably formed from TEOS-SiO 2 and the electrode layer and the spacer from polysilicon. These materials can be etched with one another with good selectivity in standard processes.
  • a gate dielectric 2 is applied to a substrate 1, for example a monocrystalline silicon wafer or an SOI substrate.
  • the gate dielectric 2 is formed, for example, by thermal oxidation from SiO 2 in a layer thickness of, for example, 3 to 4 nm (see FIG. 1).
  • An electrode layer 3 is applied to the gate dielectric 2.
  • the electrode layer 3 consists, for example, of doped polysilicon and has a thickness of 100 nm, for example.
  • the electrode layer 3 is doped, for example, with a dopant concentration in the range 10 21 cm -3 .
  • An auxiliary layer 4 is applied to the electrode layer 3 in a layer thickness of, for example, 200 nm.
  • the auxiliary layer 4 is formed from SiO 2 , for example, in a TEOS process.
  • a photoresist mask is placed on the surface of the auxiliary layer 4 5 generates the position of an edge of a later to be produced Gate electrode defined.
  • Anisotropic etching for example using CHF 3 -RIE (reactive ion etching), subsequently produces a step in the auxiliary layer 4 with a substantially vertical flank (see FIG. 2).
  • the step has a height of, for example, 150 nm.
  • the surface of the electrode layer 3 therefore remains covered by the step-like structured auxiliary layer 4.
  • the level of the step is controlled via the etching time. Subsequently the photoresist mask 5 is removed.
  • the entire surface is a layer 6 with essentially conform Edge coverage deposited (see Figure 3).
  • the Layer 6 is made, for example, of polysilicon in one Layer thickness of 100 nm, for example, deposited.
  • Anisotropic etching for example with HBr-RIE, makes horizontal ones Parts of layer 6 are removed and it remains the flank of the step-like structured auxiliary layer 4 a spacer 7 (see Figure 4).
  • the spacer 7 forms in supervision a closed curve. If this shape for the gate electrode is undesirable, the spacer 7 using a Lacquer mask to be structured wet-chemically (not shown).
  • the curvature of the spacer 7 can be on its upper Part can be limited by looking at the flank of the step structured auxiliary layer runs higher.
  • the auxiliary layer 4 is then structured using the spacer 7 as an etching mask.
  • a hard mask 8 is created from the auxiliary layer 4.
  • the auxiliary layer 4 consists continuously of, for example, deposited SiO 2 (TEOS), it is structured, for example, in an anisotropic CHF 3 and CF 4 etching process. This has a good selectivity with respect to polysilicon, so that the surface of the electrode layer 3 which was initially exposed on the one side of the spacer 7 when the auxiliary layer 4 is etched is only slightly etched.
  • the electrode layer 3 is anisotropic Structured etching with HBr, for example. This creates one Gate electrode 9. At the same time in this etching process Spacer 7, which is made of the same material as the gate electrode 9 exists, removed (see Figure 6).

Landscapes

  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Drying Of Semiconductors (AREA)
  • Static Random-Access Memory (AREA)
  • Thin Film Transistor (AREA)

Claims (3)

  1. Procédé de fabrication d'une électrode de grille d'une structure MOS,
    dans lequel on dépose sur un substrat (1) semiconducteur qui est muni d'un diélectrique (2) de grille une couche (3) d'électrode,
    dans lequel on dépose sur la couche (3) d'électrode une couche (4) auxiliaire,
    dans lequel on produit dans la couche (4) auxiliaire un épaulement, la surface de la couche (3) d'électrode restant revêtue de la couche (4) auxiliaire structurée à épaulement,
    dans lequel on forme sur l'épaulement un espaceur (7),
    dans lequel on forme à partir de la couche (4) auxiliaire structurée à épaulement, par attaque chimique anisotrope, en utilisant l'espaceur (7) comme masque d'attaque chimique, un masque (8) dur,
    dans lequel on forme l'électrode (9) de grille par attaque chimique anisotrope de la couche (3) d'électrode en utilisant le masque (8) dur comme masque d'attaque chimique,
    caractérisé en ce que l'on forme l'espaceur (7) en le matériau de la couche (3) d'électrode et la couche (4) auxiliaire et le diélectrique de grille en utilisant qu'un seul matériau de couche.
  2. Procédé suivant la revendication 1, dans lequel on forme l'espaceur par dépôt d'une couche (6) à revêtement de bord conforme et attaque chimique anisotrope qui suit.
  3. Procédé suivant la revendication 1 ou 2, dans lequel on forme la couche (4) auxiliaire et le diélectrique (2) de grille en SiO2 et la couche (3) d'électrode et l'espaceur en polysilicium.
EP96119052A 1995-12-21 1996-11-27 Méthode de fabrication d'une électrode de porte pour une structure MOS Expired - Lifetime EP0780888B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE19548056 1995-12-21
DE19548056A DE19548056C1 (de) 1995-12-21 1995-12-21 Verfahren zur Herstellung einer Gateelektrode für eine MOS-Struktur

Publications (3)

Publication Number Publication Date
EP0780888A2 EP0780888A2 (fr) 1997-06-25
EP0780888A3 EP0780888A3 (fr) 1997-07-16
EP0780888B1 true EP0780888B1 (fr) 2002-02-06

Family

ID=7780964

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96119052A Expired - Lifetime EP0780888B1 (fr) 1995-12-21 1996-11-27 Méthode de fabrication d'une électrode de porte pour une structure MOS

Country Status (7)

Country Link
US (1) US5705414A (fr)
EP (1) EP0780888B1 (fr)
JP (1) JP3899152B2 (fr)
KR (1) KR100395667B1 (fr)
AT (1) ATE213094T1 (fr)
DE (2) DE19548056C1 (fr)
TW (2) TW383412B (fr)

Families Citing this family (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5714039A (en) * 1995-10-04 1998-02-03 International Business Machines Corporation Method for making sub-lithographic images by etching the intersection of two spacers
DE19548058C2 (de) * 1995-12-21 1997-11-20 Siemens Ag Verfahren zur Herstellung eines MOS-Transistors
US5893735A (en) * 1996-02-22 1999-04-13 Siemens Aktiengesellschaft Three-dimensional device layout with sub-groundrule features
US5923981A (en) * 1996-12-31 1999-07-13 Intel Corporation Cascading transistor gate and method for fabricating the same
US6159861A (en) * 1997-08-28 2000-12-12 Nec Corporation Method of manufacturing semiconductor device
US6225201B1 (en) * 1998-03-09 2001-05-01 Advanced Micro Devices, Inc. Ultra short transistor channel length dictated by the width of a sidewall spacer
US6069044A (en) * 1998-03-30 2000-05-30 Texas Instruments-Acer Incorporated Process to fabricate ultra-short channel nMOSFETS with self-aligned silicide contact
US6261912B1 (en) * 1999-08-10 2001-07-17 United Microelectronics Corp. Method of fabricating a transistor
US6362057B1 (en) 1999-10-26 2002-03-26 Motorola, Inc. Method for forming a semiconductor device
US6630405B1 (en) 1999-12-20 2003-10-07 Chartered Semiconductor Manufacturing Ltd. Method of gate patterning for sub-0.1 μm technology
US6184116B1 (en) 2000-01-11 2001-02-06 Taiwan Semiconductor Manufacturing Company Method to fabricate the MOS gate
DE10030391C2 (de) * 2000-06-21 2003-10-02 Infineon Technologies Ag Verfahren zur Herstellung einer Anschlussfläche für vertikale sublithographische Halbleiterstrukturen
US6960806B2 (en) * 2001-06-21 2005-11-01 International Business Machines Corporation Double gated vertical transistor with different first and second gate materials
US6967351B2 (en) * 2001-12-04 2005-11-22 International Business Machines Corporation Finfet SRAM cell using low mobility plane for cell stability and method for forming
US6720231B2 (en) * 2002-01-28 2004-04-13 International Business Machines Corporation Fin-type resistors
US6709982B1 (en) * 2002-11-26 2004-03-23 Advanced Micro Devices, Inc. Double spacer FinFET formation
US6762448B1 (en) 2003-04-03 2004-07-13 Advanced Micro Devices, Inc. FinFET device with multiple fin structures
US6716686B1 (en) 2003-07-08 2004-04-06 Advanced Micro Devices, Inc. Method for forming channels in a finfet device
US7498225B1 (en) 2003-12-04 2009-03-03 Advanced Micro Devices, Inc. Systems and methods for forming multiple fin structures using metal-induced-crystallization
US7521371B2 (en) * 2006-08-21 2009-04-21 Micron Technology, Inc. Methods of forming semiconductor constructions having lines
US7670914B2 (en) * 2006-09-28 2010-03-02 Globalfoundries Inc. Methods for fabricating multiple finger transistors
CN101536153B (zh) * 2006-11-06 2011-07-20 Nxp股份有限公司 制造fet栅极的方法
US7772048B2 (en) * 2007-02-23 2010-08-10 Freescale Semiconductor, Inc. Forming semiconductor fins using a sacrificial fin
US11942133B2 (en) * 2021-09-02 2024-03-26 Kepler Computing Inc. Pedestal-based pocket integration process for embedded memory
US12069866B2 (en) 2021-09-02 2024-08-20 Kepler Computing Inc. Pocket integration process for embedded memory
US12525543B1 (en) 2021-10-01 2026-01-13 Kepler Computing Inc. Integration process for fabricating embedded memory

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4358340A (en) * 1980-07-14 1982-11-09 Texas Instruments Incorporated Submicron patterning without using submicron lithographic technique
JP2699179B2 (ja) * 1988-09-20 1998-01-19 株式会社サクラクレパス 筆記用水性インキ組成物
USH986H (en) * 1989-06-09 1991-11-05 International Business Machines Corporation Field effect-transistor with asymmetrical structure
US5202272A (en) * 1991-03-25 1993-04-13 International Business Machines Corporation Field effect transistor formed with deep-submicron gate

Also Published As

Publication number Publication date
TW334567B (en) 1998-06-21
EP0780888A3 (fr) 1997-07-16
EP0780888A2 (fr) 1997-06-25
DE19548056C1 (de) 1997-03-06
TW383412B (en) 2000-03-01
ATE213094T1 (de) 2002-02-15
JPH09181303A (ja) 1997-07-11
KR100395667B1 (ko) 2003-11-17
US5705414A (en) 1998-01-06
JP3899152B2 (ja) 2007-03-28
KR970052527A (ko) 1997-07-29
DE59608704D1 (de) 2002-03-21

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