EP0796547A2 - Couplage de signaux hns dans un reseau de couplage ts's'ts's't - Google Patents

Couplage de signaux hns dans un reseau de couplage ts's'ts's't

Info

Publication number
EP0796547A2
EP0796547A2 EP95920095A EP95920095A EP0796547A2 EP 0796547 A2 EP0796547 A2 EP 0796547A2 EP 95920095 A EP95920095 A EP 95920095A EP 95920095 A EP95920095 A EP 95920095A EP 0796547 A2 EP0796547 A2 EP 0796547A2
Authority
EP
European Patent Office
Prior art keywords
signals
space
time
ssw
centre
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP95920095A
Other languages
German (de)
English (en)
Inventor
Timo Kasurinen
Patric ÖSTERG RD
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Marconi Communications Ltd
Original Assignee
Nokia Telecommunications Oy
Nokia Networks Oy
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nokia Telecommunications Oy, Nokia Networks Oy filed Critical Nokia Telecommunications Oy
Publication of EP0796547A2 publication Critical patent/EP0796547A2/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements
    • H04Q3/64—Distributing or queueing
    • H04Q3/68—Grouping or interlacing selector groups or stages
    • H04Q3/685—Circuit arrangements therefor
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
    • H04Q11/0478—Provisions for broadband connections
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q11/00—Selecting arrangements for multiplex systems
    • H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
    • H04Q11/06—Time-space-time switching
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J2203/00—Aspects of optical multiplex systems other than those covered by H04J14/05 and H04J14/07
    • H04J2203/0001—Provisions for broadband connections in integrated services digital network using frames of the Optical Transport Network [OTN] or using synchronous transfer mode [STM], e.g. SONET, SDH
    • H04J2203/0003—Switching fabrics, e.g. transport network, control network
    • H04J2203/0012—Switching modules and their interconnections

Definitions

  • the invention relates to the use of a TS'S'TS'S'T switching network and especially to a method of switching SDH STM-N signals.
  • Synchronous digital hierarchy comprises an extensive facility for the transmission of time-divided signals in a telecommunications network. Mention can be made of the recommendation ITU-T G.707, which defines the STM-1 signal of the SDH signals, ie, the signal of the Synchronous Transport Module of the first level. Other defined levels are STM-4, STM-16 and STM-64.
  • the STM-1 basic frame is composed of bytes
  • an STM-1 frame it is possible to transmit units of a subsystem, for example, 63 TU-12 signals, in each of which 2,048 kbit/s signals can be transported.
  • the STM-N frames are assembled into logical multiframes.
  • the SDH signals are formed from signals of the subsystems by the interleaving of bytes. Thus each signal can be separated into its own time slot in the main signal.
  • SDH DXC Digital Cross Connect systems have been defined for SDH (ITU-T Draft Resolutions G.sdcx-l...-3).
  • SDH DXC is capable of connecting, in the manner desired, traffic from different SDH levels.
  • Use of cross connect equipment provides the possibility of forming remote-controlled routings, connecting traffi to reserve routes, connecting traffic from one signal to many signals (broadcasting or copying), etc. Ordinarily, connections through a cross connect device are bidirectional.
  • time switches are memory elements and the space switch is composed of switch elements.
  • a double capacity TST structure ie, a time - space - time cross connect structure also fulfils well the requirement of non-blocking properties and implementability.
  • the TST structure is better suited to large cross connect units than is the TxT S structure because in a TST arrangement only the size of the space switch increases quadratically. Depending on how the space switch is implemented, its size may nevertheless pose problems in larger cross connect equipment.
  • the centre switch block of the system is generally marked T&S.
  • the T&S switch block can be, for example, of the form space-time-space, STS, or time x time - space, TxT-S.
  • the entire switching network is then of the form TS'S'TS'S'T.
  • the STS structure of the centre port can advantageously have twice the number of inputs and outputs compared with the number of inputs and outputs of the entire switching network.
  • Each switching element must be capable of switching signals in a byte mode.
  • the problem addressed by the invention is now to indicate, in connection with TS'S'TS'S'T switching network for switching SDH signals, a method by which non-blocking switching can be implemented.
  • the problem presented is solved by means of the method according to the invention in which the signals to be switched can be packed such that new signals can be formed simply and fast via the parts of the switching network th are free.
  • the connections are packed in such a way that at least the same number of free parts is again available.
  • the method according to the invention and a cross connect architecture can be used at all SDH levels, ie, for the cross connection of the defined signals STM- 1...STM-64 and other corresponding signals.
  • STM-1 capacity 16 input and 16 output interfaces of the AU-4 signals
  • the essential point is that the switching connections can be made in a byte mode.
  • the signals of the upper level such as AU-4, TU-3 and TU-2, are "splittable" into as many small parts as there are TU-12 signals.
  • the method according to the invention offers an advantageous way of processing first the AU-4 signals in the ports of the input stages, which signals are routed via the switch stages in such a way that in each given case they are primarily routed via the STS block (space-time-space) of the same centre stage.
  • the switching algorithm does not try to pack, in an optimal manner, signals via the blocks of the other half of the centre stage - ie, the active half because it ha been observed in practice that when using a suitable algorithm, and when seeking a solution for the first time switch, in general only a very few signals do not fit within the framework of the solution. The same holds for the first space switch stage.
  • a corresponding algorithm, which is used in seeking a solution for the time switches can also be used for the first space switch stage.
  • the object is to resolve the situation by columns, ie, time slots, in such a way that not more than one signal that is routed to the same output block goes to the same centre block.
  • the signals that contravene the correct solution are connected to extra blocks.
  • the algorithm can be improved after the fetches for the first solutions in such a way that the arrangement for the signals is repeated in the first TS block.
  • the object is to see to it that the number of signals going to the centremost STS stage, which signals go to an S block of the output side, cannot exceed the number of time slots, which is 63.
  • the number of signals going from the TS block of the input side to the STS block cannot exceed the capacity of the AU-4 signals. If it is desired t enhance the packing capacity in the above-mentioned manner, the STS algorith will have to be solved in the blocks of the centre stage so that the signals can b got out and brought to the final stages in the correct sequence.
  • STM-1 frame must be processed separately. In making the switching connectio the same principles as have been mentioned above can be observed.
  • FIG. 1 shows a simplified view of the markings of the signals of the switching network.
  • FIG. 1 Shown in Figure 1 is a TS'S'TS'ST switching network for AU-4 signals, in which there are 128 inputs and 128 outputs and in which an algorithm in accordance with the invention is used.
  • TSW means a Time S Witch and SSW means a Space SWitch.
  • Each space switch has 8 inputs and 16 outputs, at least one of which is routed to a space stage of the centre block.
  • the structure of the other space switch is 16*16, and its outputs are connected to a time stage 16*16. (Regarding this centremost time switch, the cross connect is symmetrical so that a total of 128 outputs are obtained from the 16 time switches in the output.)
  • the outputs of the space switches of the centre block's output side are routed in each given case to each space switch of the output side. It is to be noted that in the example in Figure 1 the summed capacity of the centre blocks is double that of the capacity of the sidemost blocks.
  • switch blocks 1-8 are active and blocks 9-16 are extra blocks that are used to handle blocking situations as well as for the formation of new signals, which is examined in greater detail in the example given below.
  • This TS'S'TS'ST architecture shown in Figure 1 is a modified reconfigurable Clos structure.
  • modified means that the conventional TST architecture has been extended: a) by placing time and space stages in the middle of the switch and b) by adding 8 blocks to the centremost stage.
  • the first modification (a) enables blocking to be eliminated, or to be more exact, in this manner blocking is theoretically made highly improbable already without the second modification.
  • the second modification is needed primarily to speed up the operation of the TS'S'TS'ST switch, because in especially difficult cases, solution of the TS'S'TS'ST algorithm may require a very long time, in practice 2-30 s with state-of-the-art equipment. In normal cases the extra blocks guarantee that free channels are also available for new bidirectional signals. When the signals have been configured, the TS'S'TS'ST algorithm is solved so that there again remain 8 empty blocks.
  • Figure 2 shows, for purposes of illustration, a simplified example of the markings of the signals to be processed when the switching network has 3 input blocks, in each of which there are 3 input ports. There are thus nine input signals and they have two time slots in use in the example shown in Figure 2. I the figure, two numbers are marked for each input signal, the first of the numbers indicating the desired port number for the input signal and the second indicating the desired time slot of the signal leaving the output port.
  • the signals are arranged in such a way that the SSW-TSW-SSW signals in the output, which come to an STS block of the centre stage, obey the rules: the number of signals coming to the STS block, which go to an STS block of the output side (SSW-TSW), must not exceed the number of the time slots, which is 63.
  • the number of signals going from the TS block of the input side to the STS block cannot exceed the capacity of the AU-4 signal.
  • the plain AU-4 signals in the input ports must be routed first through the switch stages so that fast switching connections of the AU-4 signals are obtained. This means that in each given case it is most advantageous to route them via the same STS block.
  • the signals must be brought to a block of the centre stage such that they can reach the output side's
  • the idea is to organize the signals in such a way that into the same STS block there cannot come more signals that belong to the same group than there are time slots in the block.
  • the idea of the row numbering of the tables below is thus that the signals to be routed to the same STS block of the centre stage have the same row numbers.
  • the signals going out from the TS blocks of the input side are organized first such that the above-mentioned conditions are fulfilled. Broadcasting, ie, copyin of the signals, is not done in the TS blocks of the input side having this TS'S'TS'ST structure, and accordingly broadcasting cannot cause blocking in these blocks. Copying operations are done most advantageously in the centre stage. Due to protections, selection of VC-12 signals could cause blocking, an this can be prevented, for example, by reorganizing the outgoing signals (repeating the arrangement several times) in the TS blocks of the input side if blocking appears to occur.
  • a fan-out to the blocks of the centre stage is effected from the TS blocks of th input port.
  • the outputs of the state switches of the inpu stage are in each given case connected such that the uppermost output of the block is connected to the uppermost block of the centre stage, the second highest output to the second block of the centre stage, etc.
  • Each block of the centre stage receives outputs of the previous state switch such that the uppermost input port of the uppermost block receives the uppermost output of the previous block, the second input port receives the second output of the previous block, etc.
  • the switch blocks SSW-TSW of the output side first in the space switches SSW the signals at any given time are connected to the correct, ie, the desired output port TSW, which signals then arrange the time slots into the correct order to be sent out from the cross connect as the AU-4 signal required at any given time.
  • Table 1 shows, in simplified form, the signals coming to the switching networ According to the explanation in Figure 2, the signal in time slot one of port on (6,1) should be connected to output port 6 of the TS'S'TS'S'T switch and to time slot one in the output port.
  • the incoming signals invol a number of cases in which the signal must be copied to several output ports.
  • the incoming signal in time slot one of port four (fourth row, fir column: 8.2/3,1/1,2) must be copied to the outputs 8/2, 3,1 and 1,2.
  • the organization of the signals of the TS'S'TS'S'T switching arrangement in t input blocks forms the most difficult part of the algorithm according to the invention.
  • the object of this invention is to give a more precise picture of the implementation of the algorithm in the input blocks and, more generally, also i the other blocks.
  • the signals in Table 1 are organized in the first block, ie, the block of the input side, in which the idea is to organize the signals as far as possible in such a wa that one column does not contain two signals going to the same output port.
  • the output of each signal is solved. Thereafter, routes can be sought separately inside each TS block.
  • the problem to be solved is simple.
  • the signals in the time switches must be organized in such a way that the column contains no more than one signal going to the same output port.
  • Table 2 shows the arrangement of the signals after the first time switch.
  • the signals in the space switch can then be switched to the desired port. In this case, selections are made only in the space switch.
  • selections are made only in the space switch.
  • Arranging of the signals must now be continued in the first space switch of the input side according to the same principle as in the time switch, ie, such that one column does not contain two signals going to the same port.
  • a solution must be obtained separately for a situation such that to a given centre block there does not go more than one signal that goes to the same final block. If this cannot be accomplished completely, the unsolved signals are moved to the extra blocks.
  • Each block of the centre stage receives outputs of the space switch in such a way that the highest row (input ports 1 , 4, 7) receives the highest output of the previous block, the second row (input ports 2, 5, 8) receives the second output of the previous block, etc.
  • the situation in the input ports of the centre blocks is made like that shown in Table 4, ie, the situation after fan-out.
  • Signal 6/1 (row 1 , column 1) is moved one row down because it is about to go to the centremost block (of which the output ports are 4-6) of the sidemost switches of the output side.
  • Signal 8,2/3,1/1,2 (row 2, column 1) is first divided in two: first signal 8,2 is copied one row down on the same basis as signal 6/1 was above (the output por of signal 8,2 is in the third output block).
  • a signal is also copied one row up, ie, 3,1/1,2 should come from the output ports that are located in the first output block (output ports 1-3). The same principle is applied to the other signals.
  • the initial situation of the space switching connections made here is not presented separately.
  • Table 7 shows the situation after the last space switches.
  • Table 8 finally shows the situation after the last time switches, ie, the output signals of the entire switching network in the example selected here.
  • Tables 1-8 is greatly simplified for purposes of illustration.
  • the switchings of the signals would have to be illustrated with tables having, in a corresponding fashion, 128 rows and 63 columns, ie, 8,064 signal cells.
  • An illustrative representation of the real-life situation furthermore will grow significantly in size if, additionally, it is desired to show the switching situations of the "extra" blocks of the centre stages by means of corresponding tables.
  • the method and cross connect architecture presented do not limit the implementation to the model presented in the example, but instead the invention can be employed at all SDH levels.
  • the switching mode can be used for the cross connect of both STM and other corresponding signals.
  • the modular structure of the exampl is advantageous at the present moment, it does not of course limit the use of th invention with smaller of, especially, with larger modules.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
  • Data Exchanges In Wide-Area Networks (AREA)

Abstract

L'invention concerne un procédé de commutation de signaux MTS-N dans un réseau de commutation TS'S'TS'S'T (temps-espace' espace' temps-espace'espace'temps') dans lequel le nombre de ports d'entrée et de sortie de l'étage central espace-temps-espace (STS) est, par exemple, le double de celui des ports des étages d'entrée ou de sortie, les blocs de ce doublement étant appelés blocs supplémentaires. Dans le procédé selon l'invention, on obtient d'abord une solution de commutation pour les signaux voyageant à travers les commutateurs temporels et spatiaux (TS) du côté d'entrée de telle manière que dans la même tranche temporelle des sorties des commutateurs temporels (T), il n'y ait pas plus d'un signal se dirigeant vers le même port de sortie du réseau de commutation. Ensuite, on obtient une solution pour les sorties des commutateurs spatiaux (S) du côté des entrées de telle manière qu'il n'y ait pas plus d'un signal se dirigeant vers le même bloc central (STS) de l'étage central, qui ne doive être acheminé vers le même bloc de sortie (ST). Enfin, il est simple d'obtenir une solution à travers l'étage central (STS) et le côté des sorties (TS).
EP95920095A 1994-05-25 1995-05-24 Couplage de signaux hns dans un reseau de couplage ts's'ts's't Withdrawn EP0796547A2 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
FI942434A FI97600C (fi) 1994-05-25 1994-05-25 SDH-signaalien kytkeminen TS'S'TS'S'T-kytkentäverkossa
FI942434 1994-05-25
PCT/FI1995/000287 WO1995032598A2 (fr) 1994-05-25 1995-05-24 Couplage de signaux hns dans un reseau de couplage ts's'ts's't

Publications (1)

Publication Number Publication Date
EP0796547A2 true EP0796547A2 (fr) 1997-09-24

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
EP95920095A Withdrawn EP0796547A2 (fr) 1994-05-25 1995-05-24 Couplage de signaux hns dans un reseau de couplage ts's'ts's't

Country Status (4)

Country Link
EP (1) EP0796547A2 (fr)
AU (1) AU2567695A (fr)
FI (1) FI97600C (fr)
WO (1) WO1995032598A2 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI97842C (fi) * 1995-03-20 1997-02-25 Nokia Telecommunications Oy Digitaalisen ristikytkimen konfigurointi
FI97843C (fi) * 1995-03-20 1997-02-25 Nokia Telecommunications Oy Menetelmä reittivarmistussignaalien kytkemiseksi digitaalisessa ristikytkimessä

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FI95854C (fi) * 1992-04-23 1996-03-25 Nokia Telecommunications Oy Menetelmä sekä digitaalinen ristikytkentäarkkitehtuuri SDH-signaalien ristikytkentää varten
FI90707C (fi) * 1992-04-24 1994-03-10 Nokia Telecommunications Oy Menetelmä ristikytkimen kytkentäreittien muodostamiseksi
GB2269296A (en) * 1992-08-01 1994-02-02 Northern Telecom Ltd Telecommunications switch architecture
US5430716A (en) * 1993-01-15 1995-07-04 At&T Corp. Path hunt for efficient broadcast and multicast connections in multi-stage switching fabrics

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9532598A3 *

Also Published As

Publication number Publication date
WO1995032598A3 (fr) 1995-12-14
WO1995032598A2 (fr) 1995-11-30
FI97600B (fi) 1996-09-30
AU2567695A (en) 1995-12-18
FI942434L (fi) 1995-11-26
FI97600C (fi) 1997-01-10
FI942434A0 (fi) 1994-05-25

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