EP0803859A3 - Système et méthode optimisant les exigences de mémorisation pour un canal de distribution à N voies - Google Patents

Système et méthode optimisant les exigences de mémorisation pour un canal de distribution à N voies Download PDF

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Publication number
EP0803859A3
EP0803859A3 EP96118476A EP96118476A EP0803859A3 EP 0803859 A3 EP0803859 A3 EP 0803859A3 EP 96118476 A EP96118476 A EP 96118476A EP 96118476 A EP96118476 A EP 96118476A EP 0803859 A3 EP0803859 A3 EP 0803859A3
Authority
EP
European Patent Office
Prior art keywords
texels
frame buffer
storage unit
buffer controller
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP96118476A
Other languages
German (de)
English (en)
Other versions
EP0803859A2 (fr
Inventor
John A. Dykstal
Darel N. Emmot
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
HP Inc
Original Assignee
Hewlett Packard Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hewlett Packard Co filed Critical Hewlett Packard Co
Publication of EP0803859A2 publication Critical patent/EP0803859A2/fr
Publication of EP0803859A3 publication Critical patent/EP0803859A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
    • G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
    • G09G5/39—Control of the bit-mapped memory
    • G09G5/393—Arrangements for updating the contents of the bit-mapped memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/121—Frame memory handling using a cache memory
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2360/00—Aspects of the architecture of display systems
    • G09G2360/12—Frame memory handling
    • G09G2360/123—Frame memory handling using interleaving

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Image Generation (AREA)
  • Digital Computer Display Output (AREA)
EP96118476A 1996-04-23 1996-11-18 Système et méthode optimisant les exigences de mémorisation pour un canal de distribution à N voies Withdrawn EP0803859A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US63625096A 1996-04-23 1996-04-23
US636250 1996-04-23

Publications (2)

Publication Number Publication Date
EP0803859A2 EP0803859A2 (fr) 1997-10-29
EP0803859A3 true EP0803859A3 (fr) 1998-03-04

Family

ID=24551094

Family Applications (1)

Application Number Title Priority Date Filing Date
EP96118476A Withdrawn EP0803859A3 (fr) 1996-04-23 1996-11-18 Système et méthode optimisant les exigences de mémorisation pour un canal de distribution à N voies

Country Status (2)

Country Link
EP (1) EP0803859A3 (fr)
JP (1) JPH1083457A (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4617210B2 (ja) * 2005-07-13 2011-01-19 日立ビアメカニクス株式会社 描画装置及びそれを搭載した露光装置
US8207980B2 (en) * 2007-05-01 2012-06-26 Vivante Corporation Coordinate computations for non-power of 2 texture maps
JP5669199B2 (ja) * 2011-02-25 2015-02-12 Ｎｅｃソリューションイノベータ株式会社 画像描画装置、画像描画方法、及びプログラム

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197412A2 (fr) * 1985-04-05 1986-10-15 Tektronix, Inc. Mémoire tampon d'image à accès variable
EP0447227A2 (fr) * 1990-03-16 1991-09-18 Hewlett-Packard Company Méthode et appareil pour générer des primitives graphiques texturées dans des systèmes graphiques à calculateur avec tampon de trame
US5230039A (en) * 1991-02-19 1993-07-20 Silicon Graphics, Inc. Texture range controls for improved texture mapping
WO1994011807A1 (fr) * 1992-11-13 1994-05-26 The University Of North Carolina At Chapel Hill Architecture et appareil de generation d'image
WO1995024682A1 (fr) * 1994-03-07 1995-09-14 Silicon Graphics, Inc. Procede d'integration de memoire de textures et de logique d'interpolation
EP0747858A2 (fr) * 1995-06-06 1996-12-11 Hewlett-Packard Company Antémémoire pour données de topographie de texture

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0197412A2 (fr) * 1985-04-05 1986-10-15 Tektronix, Inc. Mémoire tampon d'image à accès variable
EP0447227A2 (fr) * 1990-03-16 1991-09-18 Hewlett-Packard Company Méthode et appareil pour générer des primitives graphiques texturées dans des systèmes graphiques à calculateur avec tampon de trame
US5230039A (en) * 1991-02-19 1993-07-20 Silicon Graphics, Inc. Texture range controls for improved texture mapping
WO1994011807A1 (fr) * 1992-11-13 1994-05-26 The University Of North Carolina At Chapel Hill Architecture et appareil de generation d'image
WO1995024682A1 (fr) * 1994-03-07 1995-09-14 Silicon Graphics, Inc. Procede d'integration de memoire de textures et de logique d'interpolation
EP0747858A2 (fr) * 1995-06-06 1996-12-11 Hewlett-Packard Company Antémémoire pour données de topographie de texture

Also Published As

Publication number Publication date
EP0803859A2 (fr) 1997-10-29
JPH1083457A (ja) 1998-03-31

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