EP0816964B1 - Spannungsregelungsvorrichtung mit geringer interner Verlustleistung - Google Patents

Spannungsregelungsvorrichtung mit geringer interner Verlustleistung Download PDF

Info

Publication number
EP0816964B1
EP0816964B1 EP97201851A EP97201851A EP0816964B1 EP 0816964 B1 EP0816964 B1 EP 0816964B1 EP 97201851 A EP97201851 A EP 97201851A EP 97201851 A EP97201851 A EP 97201851A EP 0816964 B1 EP0816964 B1 EP 0816964B1
Authority
EP
European Patent Office
Prior art keywords
output
transistor
voltage
terminal
transistors
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP97201851A
Other languages
English (en)
French (fr)
Other versions
EP0816964A1 (de
Inventor
Jean-Claude Perraud
Philippe Maugars
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of EP0816964A1 publication Critical patent/EP0816964A1/de
Application granted granted Critical
Publication of EP0816964B1 publication Critical patent/EP0816964B1/de
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • GPHYSICS
    • G05CONTROLLING; REGULATING
    • G05FSYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
    • G05F1/00Automatic systems in which deviations of an electric quantity from one or more predetermined values are detected at the output of the system and fed back to a device within the system to restore the detected quantity to its predetermined value or values, i.e. retroactive systems
    • G05F1/10Regulating voltage or current 
    • G05F1/46Regulating voltage or current  wherein the variable actually regulated by the final control device is DC
    • G05F1/56Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices
    • G05F1/565Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor
    • G05F1/569Regulating voltage or current  wherein the variable actually regulated by the final control device is DC using semiconductor devices in series with the load as final control devices sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor for protection

Definitions

  • a regulator circuit as described above is known from the article "Verminderen van warmtedissipatie" by Mr. W. Birkhoff, published in the Radio Bulletin of September 1977.
  • the regulator circuit described therein includes a module for managing the distribution of the energy which distributes the dissipation so substantially equal in each of the two transistors.
  • Another tension regulation device intended to obtain a better internal distribution of stress thermal and electrical is described in document EP 0 501 418 (A); this device includes two transistors whose entry into conduction is controlled by a management unit arranged between the two transistors and a comparison module.
  • Such circuits regulators pose a problem when one wishes to realize as an integrated circuit.
  • the object of the present invention is to remedy this disadvantage by proposing a regulating device in which the power to be dissipated by the regulator circuit is reduced, without this does not limit the value of the output current.
  • a voltage regulation device is characterized in that it is provided with a circuit electric to evacuate outside the regulator circuit part of the power dissipated due to the output current.
  • An embodiment of the invention presents a voltage regulation device as defined in paragraph introductory, characterized in that it comprises a first resistance a first terminal of which is connected to the output terminal of the device and a second terminal at the intermediate node common to the first and second transistors, and in that the management module is provided with means for routing at least part of the output current into said first resistance.
  • An advantageous embodiment of the invention presents a voltage regulation device as described above, characterized in that the management module includes a third transistor mounted as a current mirror with the first transistor, the collector of the third transistor being connected to a terminal of a second resistor whose other terminal is connected to the base of the second transistor, on the one hand, and at the output of the module comparison, on the other hand.
  • the voltage drop across the terminals of the second resistor controls the conduction of the second transistor. At first, it is not conductive and almost all of power dissipation is done in the first resistance external to the regulator circuit. It is only when the output current becomes large enough to saturate the first transistor that the conduction of the second transistor is engaged, allowing the regulator circuit to dissipate internally a surplus of power than the first resistance does can't assume.
  • a variant of the invention presents a device for voltage regulation as described above, characterized in that it includes a fourth transistor mounted as a current mirror with the first transistor, the fourth transistor forming a source of current used for the polarization of the comparison module.
  • This variant allows the regulator circuit to adapt its energy consumption under the conditions in which it operates. Indeed, the currents it consumes are substantially proportional to the current flowing through the first transistor, itself equal to the output current. When this is low, the current consumed by the entire regulator circuit is weak.
  • a preferred embodiment of the invention presents a voltage regulation device as described above, characterized in that the first and second transistors have an area several times larger than that of the third and fourth transistors.
  • the currents consumed by the third and fourth transistors are reduced to a fraction of the output current, which greatly reduces the power consumed by the regulator circuit.
  • a particular embodiment presents a device voltage regulator as described above, characterized in that the first, second, third and fourth transistors are PNP transistors.
  • FIG. 1 presents a functional diagram describing a regulation device tension according to one embodiment of the invention.
  • the output voltage Vout is regulated by the feedback effected by means of the divider bridge (R3, R4) and of the CMP comparator in the comparison module 10.
  • the CMP comparator is built on the basis of differential pairs which are here polarized by a current resulting from reproduction, via an assembly current mirror type, of the current delivered by the fourth transistor T4. T4 being N times smaller than T1, this current is substantially equal to Iout / N.
  • the CMP comparator therefore consumes only little energy when the output current Iout is low.
  • the operation of the management module 20 is as follows: When Iout is low, only the transistor T1 is conductive. The transistor T3, N times smaller than T1, then conducts a current substantially equal to Iout / N. The voltage drop in resistor R2, equal to R2.Iout / N is weak. The base-emitter voltage of the transistor T2 being too large to allow its conduction, T2 remains blocked. The almost all of the output current Iout therefore passes through the resistor R1, which then dissipates a large part of the power outside of the regulator circuit.

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Radar, Positioning & Navigation (AREA)
  • Automation & Control Theory (AREA)
  • Continuous-Control Power Sources That Use Transistors (AREA)
  • Control Of Electrical Variables (AREA)

Claims (7)

  1. Spannungsregelungsvorrichtung mit einer ersten und einer zweiten Versorgungsklemme (VCC, GND) und einer Ausgangsklemme, an der die Vorrichtung über einen variablen Ausgangsstrom (Iout) eine geregelte Ausgangsspannung (Vout) liefert, und die Vorrichtung eine sogenannte Regelungsvorrichtung enthält, bestehend aus:
    einem ersten und einem zweiten, in Serie zwischen der ersten Versorgungsklemme (VCC) und der Ausgangsklemme angeordneten Transistor (T1, T2),
    einem sogenannten Vergleichsmodul (10) mit einem Ausgang und zwei Eingängen, von denen der eine zumindest einen Teil der Ausgangsspannung erhält und der andere eine sogenannte Referenzspannung (Vref) erhält,
    einem Steuermodul (20) zur Verteilung der Verlustleistung der Vorrichtung, das vom Ausgang des Vergleichsmoduls (10) gesteuert wird,
       dadurch gekennzeichnete Vorrichtung, daß sie mit einer elektrischen Schaltung versehen ist, die es über den Ausgangsstrom ermöglicht, einen Teil der Verlustleistung extern zum Regler zu entladen.
  2. Spannungsregelungsvorrichtung nach Anspruch 1, dadurch gekennzeichnet, daß sie einen ersten Widerstand (R1) enthält, von dem eine erste Klemme mit der Ausgangsklemme der Vorrichtung, und eine zweite Klemme mit dem dem ersten und zweiten Transistor (T1, T2) gemeinsamen Zwischenknoten verbunden ist, und dadurch, daß das Steuermodul (20) mit Mitteln versehen ist, um zumindest einen Teil des Ausgangsstroms (Iout) in den besagten ersten Widerstand (R1) zu leiten.
  3. Spannungsregelungsvorrichtung nach einem der beliebigen Ansprüche 1 oder 2, dadurch gekennzeichnet, daß das Steuermodul (20) einen dritten Transistor (T3) aufweist, im Stromspiegel zum ersten Transistor (T1) angeordneten, wobei der Kollektor des dritten Transistors mit einer Klemme eines zweiten Widerstands (R2) verbunden ist, dessen andere Klemme einerseits mit der Basis des zweiten Transistors (T2) und andererseits mit dem Ausgang des Vergleichsmoduls (10) verbunden ist.
  4. Spannungsregelungsvorrichtung nach einem der beliebigen Ansprüche 1 bis 3, dadurch gekennzeichnet, daß sie einen vierten Transistor (T4) aufweist, im Stromspiegel zum ersten Transistor (T1) angeordneten, wobei der vierte Transistor (T4) eine Stromquelle bildet, die der Polarisierung des Vergleichsmoduls (10) dient.
  5. Spannungsregelungsvorrichtung nach Anspruch 4, dadurch gekennzeichnet, daß der erste und zweite Transistor (T1, T2) eine zu der des dritten und vierten Transistors (T3, T4) mehrfach größere Oberfläche aufweisen.
  6. Spannungsregelungsvorrichtung nach einem der beliebigen Ansprüche 4 oder 5, dadurch gekennzeichnet, daß der erste, zweite, dritte und vierte Transistor (T1, T2, T3, T4) PNP-Transistoren sind.
  7. Spannungsregelungsvorrichtung nach einem der beliebigen Ansprüche 1 bis 6, dadurch gekennzeichnet, daß das Vergleichsmodul (10) besteht aus:
    einer zwischen der Ausgangsklemme und einer der Versorgungsklemmen (GND) angeordneten Spannungsteilerbrücke (R3, R4),
    einem Vergleicher (CMP) mit einem Ausgang und einem ersten und zweiten Eingang, wobei der erste Eingang die Referenzspannung (Vref) erhält und der zweite Eingang mit einem Zwischenknoten der Teilerbrücke (R3, R4) verbunden ist,
    einem fünften Transistor (T5), dessen Basis mit dem Ausgang des Vergleichers (CMP), während der Emitter mit der zweiten Versorgungsklemme (GND) und der Kollektor mit der Basis des zweiten Transistors (T2) verbunden ist.
EP97201851A 1996-06-26 1997-06-17 Spannungsregelungsvorrichtung mit geringer interner Verlustleistung Expired - Lifetime EP0816964B1 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR9607940 1996-06-26
FR9607940A FR2750514A1 (fr) 1996-06-26 1996-06-26 Dispositif de regulation de tension a faible dissipation interne d'energie

Publications (2)

Publication Number Publication Date
EP0816964A1 EP0816964A1 (de) 1998-01-07
EP0816964B1 true EP0816964B1 (de) 2000-11-22

Family

ID=9493433

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97201851A Expired - Lifetime EP0816964B1 (de) 1996-06-26 1997-06-17 Spannungsregelungsvorrichtung mit geringer interner Verlustleistung

Country Status (5)

Country Link
US (1) US5929616A (de)
EP (1) EP0816964B1 (de)
JP (1) JPH1063353A (de)
DE (1) DE69703568T2 (de)
FR (1) FR2750514A1 (de)

Families Citing this family (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
SE507740C2 (sv) * 1996-11-08 1998-07-06 Ericsson Telefon Ab L M Förfarande och anordning för avledning av effekt
US6292050B1 (en) 1997-01-29 2001-09-18 Cardiac Pacemakers, Inc. Current and temperature compensated voltage reference having improved power supply rejection
DE19818464A1 (de) * 1998-04-24 1999-10-28 Siemens Ag Referenzspannung-Erzeugungsschaltung
US6188211B1 (en) * 1998-05-13 2001-02-13 Texas Instruments Incorporated Current-efficient low-drop-out voltage regulator with improved load regulation and frequency response
KR100358646B1 (ko) * 2000-01-22 2002-10-31 유종근 Rfid 응용을 위한 일정한 감폭율을 갖는 새로운감폭회로
US6489847B1 (en) * 2000-01-28 2002-12-03 Telefonaktiebolaget Lm Ericsson Low distoration driving amplifier for integrated filters
FR2807847B1 (fr) 2000-04-12 2002-11-22 St Microelectronics Sa Regulateur lineaire a faible surtension en regime transitoire
US6359427B1 (en) * 2000-08-04 2002-03-19 Maxim Integrated Products, Inc. Linear regulators with low dropout and high line regulation
US6381491B1 (en) 2000-08-18 2002-04-30 Cardiac Pacemakers, Inc. Digitally trimmable resistor for bandgap voltage reference
US6441765B1 (en) 2000-08-22 2002-08-27 Marvell International, Ltd. Analog to digital converter with enhanced differential non-linearity
US6396334B1 (en) 2000-08-28 2002-05-28 Marvell International, Ltd. Charge pump for reference voltages in analog to digital converter
US6400214B1 (en) 2000-08-28 2002-06-04 Marvell International, Ltd. Switched capacitor filter for reference voltages in analog to digital converter
US6417725B1 (en) 2000-08-28 2002-07-09 Marvell International, Ltd. High speed reference buffer
US6369554B1 (en) * 2000-09-01 2002-04-09 Marvell International, Ltd. Linear regulator which provides stabilized current flow
FR2820923B1 (fr) * 2001-02-09 2003-06-13 Atmel Nantes Sa Alimentation asservie pour liaison serie, de type maitre esclave
KR100607661B1 (ko) 2002-12-30 2006-08-02 매그나칩 반도체 유한회사 Cmos를 이용한 비접촉식 무선인식카드 데이터송수신단의 전압제한회로
US20050003764A1 (en) * 2003-06-18 2005-01-06 Intel Corporation Current control circuit
WO2006079978A2 (en) * 2005-01-28 2006-08-03 Nxp B.V. Voltage integrator and transformer provided with such an integrator
JP4786445B2 (ja) * 2006-07-13 2011-10-05 フリースケール セミコンダクター インコーポレイテッド シリーズレギュレータ回路
US7928709B2 (en) * 2009-02-04 2011-04-19 Vanguard International Semiconductor Corporation Voltage regulator and AC-DC converter
CN101963820B (zh) * 2009-07-21 2013-11-06 意法半导体研发(上海)有限公司 自适应密勒补偿型电压调节器
US9134743B2 (en) * 2012-04-30 2015-09-15 Infineon Technologies Austria Ag Low-dropout voltage regulator
US9846445B2 (en) * 2016-04-21 2017-12-19 Nxp Usa, Inc. Voltage supply regulator with overshoot protection
US10996700B1 (en) * 2019-12-07 2021-05-04 Pixart Imaging Incorporation Fast response linear regulator with bias current control and overshoot and undershoot suppression

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3996498A (en) * 1975-05-19 1976-12-07 Rca Corporation Current limiting circuit and method
US4338646A (en) * 1981-04-27 1982-07-06 Motorola, Inc. Current limiting circuit
DE3440888A1 (de) * 1984-11-09 1986-05-15 Robert Bosch Gmbh, 7000 Stuttgart Spannungskonstanthalter zur stromversorgung elektronischer steuergeraete
IT1185878B (it) * 1985-08-09 1987-11-18 Sgs Microelettronica Spa Circuito antisaturazione per transistore pnp integrato con caratteristica di intervento definibile secondo una funzione prefissata
US5010292A (en) * 1989-12-12 1991-04-23 North American Philips Corporation Voltage regulator with reduced semiconductor power dissipation
IT1245421B (it) * 1991-02-27 1994-09-20 Sgs Thomson Microelectronics Regolatore di tensione a bassa caduta
DE69227244T2 (de) * 1992-07-28 1999-03-04 Stmicroelectronics S.R.L., Agrate Brianza, Mailand/Milano Sättigungssteuerung eines integrierten bipolaren Transistors
US5550462A (en) * 1993-06-29 1996-08-27 Sharp Kabushiki Kaisha Regulated power supply circuit and an emitter follower output current limiting circuit
GB9417267D0 (en) * 1994-08-26 1994-10-19 Inmos Ltd Current generator circuit
FR2724069B1 (fr) * 1994-08-31 1997-01-03 Sgs Thomson Microelectronics Detecteur de temperature sur circuit integre
US5570060A (en) * 1995-03-28 1996-10-29 Sgs-Thomson Microelectronics, Inc. Circuit for limiting the current in a power transistor
KR0149577B1 (ko) * 1995-06-12 1998-12-01 김광호 반도체 메모리 장치의 내부 전원전압 발생회로

Also Published As

Publication number Publication date
DE69703568D1 (de) 2000-12-28
FR2750514A1 (fr) 1998-01-02
DE69703568T2 (de) 2001-06-13
US5929616A (en) 1999-07-27
JPH1063353A (ja) 1998-03-06
EP0816964A1 (de) 1998-01-07

Similar Documents

Publication Publication Date Title
EP0816964B1 (de) Spannungsregelungsvorrichtung mit geringer interner Verlustleistung
EP0414319B1 (de) Schaltung für die Lieferung einer Referenzspannung
EP2256578A1 (de) Low-dropout Spannungsregler mit niedrigem Ruhestrom
FR3102581A1 (fr) Régulateur de tension
FR2583236A1 (fr) Dispositif electrique de puissance " intelligent " a circuit integre monolithique
EP1009003A1 (de) Einrichtung zur Steuerung eines Elektromagneten, mit von Haltestrom gespeisten Stromversorgung
FR3102580A1 (fr) Régulateur de tension
EP0700151A1 (de) Leistungsfolgeverstärkerstufe
FR2872355A1 (fr) Circuit integre et procede pour generer un signal d'horloge
FR2829634A1 (fr) Circuit d'interface logique limiteur de courant
EP0649079A1 (de) Geregelter Spannungsquellengenerator der Bandgapbauart
EP0505234B1 (de) Schaltkreis zur Erkennung eines Schalterzustandes, namentlich eines Zündschlüssels in einem Spannungsregler eines Wechselstromgenerators
EP0843412B1 (de) Anwesenheitsdetektor mit einer stabilisierten Stromquelle
FR2686757A1 (fr) Modulateur du courant d'une ligne telephonique.
FR2744860A1 (fr) Amplificateur de puissance a limitation de tension surelevee
EP1010048A1 (de) Spannungsregelungsschaltung zur unterdrückung des latch-up phänomen
FR2620541A1 (fr) Circuit regulateur de tension
EP4517473B1 (de) Spannungsregler
EP0457397B1 (de) Schaltungsanordnung zur Regelung des Leitungsstroms in einem Telefonapparat
FR2488077A1 (fr) Etage de sortie basse impedance pour couplage capacitif ou direct
FR2767933A1 (fr) Circuit adaptateur de tension d'alimentation
EP0973153B1 (de) Magnetische Informationslesevorrichtung
EP0738037A1 (de) Erregerschaltkreis für einen Wechselstromgenerator, insbesondere für Kraftfahrzeuge und Regler mit einem solchen Wechselstromgenerator
EP1248176A1 (de) Stromquelle, die auch bei niedriger Versorgungsspannung verwendet werden kann und die quasi null Stromänderungen in Abhängigkeit der Versorgungspannung arbeitet
FR2712747A1 (fr) Dispositif d'alimentation d'une charge résistive à partir d'une batterie de stockage d'énergie d'un véhicule.

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): DE FR GB IT

17P Request for examination filed

Effective date: 19980707

AKX Designation fees paid

Free format text: DE FR GB IT

RBV Designated contracting states (corrected)

Designated state(s): DE FR GB IT

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

17Q First examination report despatched

Effective date: 20000201

GRAG Despatch of communication of intention to grant

Free format text: ORIGINAL CODE: EPIDOS AGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAH Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOS IGRA

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB IT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT;WARNING: LAPSES OF ITALIAN PATENTS WITH EFFECTIVE DATE BEFORE 2007 MAY HAVE OCCURRED AT ANY TIME BEFORE 2007. THE CORRECT EFFECTIVE DATE MAY BE DIFFERENT FROM THE ONE RECORDED.

Effective date: 20001122

REF Corresponds to:

Ref document number: 69703568

Country of ref document: DE

Date of ref document: 20001228

GBT Gb: translation of ep patent filed (gb section 77(6)(a)/1977)

Effective date: 20010124

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20010625

Year of fee payment: 5

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20010629

Year of fee payment: 5

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20010821

Year of fee payment: 5

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed
REG Reference to a national code

Ref country code: GB

Ref legal event code: IF02

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20020617

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030101

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20020617

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20030228

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST