EP0837503A3 - Métallisation des plans de référence sur un circuit intégré - Google Patents

Métallisation des plans de référence sur un circuit intégré Download PDF

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Publication number
EP0837503A3
EP0837503A3 EP97116499A EP97116499A EP0837503A3 EP 0837503 A3 EP0837503 A3 EP 0837503A3 EP 97116499 A EP97116499 A EP 97116499A EP 97116499 A EP97116499 A EP 97116499A EP 0837503 A3 EP0837503 A3 EP 0837503A3
Authority
EP
European Patent Office
Prior art keywords
integrated circuit
voltage reference
reference planes
reference plane
metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97116499A
Other languages
German (de)
English (en)
Other versions
EP0837503A2 (fr
Inventor
Donald A. Priore
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hewlett Packard Development Co LP
Original Assignee
Digital Equipment Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Digital Equipment Corp filed Critical Digital Equipment Corp
Publication of EP0837503A2 publication Critical patent/EP0837503A2/fr
Publication of EP0837503A3 publication Critical patent/EP0837503A3/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/495—Capacitive arrangements or effects of, or between wiring layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/423—Shielding layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/435—Cross-sectional shapes or dispositions of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Structure Of Printed Boards (AREA)
EP97116499A 1996-10-16 1997-09-22 Métallisation des plans de référence sur un circuit intégré Withdrawn EP0837503A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US73443696A 1996-10-16 1996-10-16
US734436 1996-10-16

Publications (2)

Publication Number Publication Date
EP0837503A2 EP0837503A2 (fr) 1998-04-22
EP0837503A3 true EP0837503A3 (fr) 1998-07-15

Family

ID=24951695

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97116499A Withdrawn EP0837503A3 (fr) 1996-10-16 1997-09-22 Métallisation des plans de référence sur un circuit intégré

Country Status (2)

Country Link
EP (1) EP0837503A3 (fr)
JP (1) JPH10189593A (fr)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6278186B1 (en) * 1998-08-26 2001-08-21 Intersil Corporation Parasitic current barriers
JP3465617B2 (ja) * 1999-02-15 2003-11-10 カシオ計算機株式会社 半導体装置
WO2004102665A1 (fr) * 2003-05-14 2004-11-25 Ericsson Technology Licensing Ab Circuits a haute densite qui comportent des bobines d'induction
JP5252491B2 (ja) * 2008-08-22 2013-07-31 独立行政法人産業技術総合研究所 多層微細配線構造
WO2011033599A1 (fr) * 2009-09-21 2011-03-24 株式会社 東芝 Dispositif a semi-conducteur
CN116504738A (zh) * 2022-01-19 2023-07-28 长鑫存储技术有限公司 金属互连版图结构及半导体结构

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60187038A (ja) * 1984-03-07 1985-09-24 Hitachi Ltd 多層配線構造
EP0163795A2 (fr) * 1983-12-13 1985-12-11 Fairchild Semiconductor Corporation Procédé et moyens pour réduire des pertes de propagation de signaux dans des circuits intégrés à très grande échelle
US4626889A (en) * 1983-12-23 1986-12-02 Hitachi, Ltd. Stacked differentially driven transmission line on integrated circuit
EP0353414A2 (fr) * 1988-05-26 1990-02-07 Kabushiki Kaisha Toshiba Dispositif semi-conducteur comprenant des couches conductrices

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0163795A2 (fr) * 1983-12-13 1985-12-11 Fairchild Semiconductor Corporation Procédé et moyens pour réduire des pertes de propagation de signaux dans des circuits intégrés à très grande échelle
US4626889A (en) * 1983-12-23 1986-12-02 Hitachi, Ltd. Stacked differentially driven transmission line on integrated circuit
JPS60187038A (ja) * 1984-03-07 1985-09-24 Hitachi Ltd 多層配線構造
EP0353414A2 (fr) * 1988-05-26 1990-02-07 Kabushiki Kaisha Toshiba Dispositif semi-conducteur comprenant des couches conductrices

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PATENT ABSTRACTS OF JAPAN vol. 010, no. 027 (E - 378) 4 February 1986 (1986-02-04) *
PRIORE D A: "INDUCTANCE ON SILICON FOR SUB-MICRON CMOS VLSI", PROCEEDINGS OF THE SYMPOSIUM ON VLSI CIRCUITS, KYOTO, MAY 19 - 21, 1993, no. -, 19 May 1993 (1993-05-19), INSTITUTE OF ELECTRICAL AND ELECTRONICS ENGINEERS, pages 17/18, XP000470862 *

Also Published As

Publication number Publication date
JPH10189593A (ja) 1998-07-21
EP0837503A2 (fr) 1998-04-22

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