EP0856795A3 - Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung und Prozessor dafür - Google Patents

Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung und Prozessor dafür Download PDF

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Publication number
EP0856795A3
EP0856795A3 EP98200768A EP98200768A EP0856795A3 EP 0856795 A3 EP0856795 A3 EP 0856795A3 EP 98200768 A EP98200768 A EP 98200768A EP 98200768 A EP98200768 A EP 98200768A EP 0856795 A3 EP0856795 A3 EP 0856795A3
Authority
EP
European Patent Office
Prior art keywords
state
pin
entries
steps
output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98200768A
Other languages
English (en)
French (fr)
Other versions
EP0856795A2 (de
Inventor
Paul Foster
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Avant| Corp
Original Assignee
Genrad Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Genrad Inc filed Critical Genrad Inc
Publication of EP0856795A2 publication Critical patent/EP0856795A2/de
Publication of EP0856795A3 publication Critical patent/EP0856795A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
    • G01R31/28—Testing of electronic circuits, e.g. by signal tracer
    • G01R31/317—Testing of digital circuits
    • G01R31/3181—Functional testing
    • G01R31/3183—Generation of test inputs, e.g. test vectors, patterns or sequences
    • G01R31/318342—Generation of test inputs, e.g. test vectors, patterns or sequences by preliminary fault modelling, e.g. analysis, simulation
    • G01R31/318357—Simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/26—Functional testing
    • G06F11/261—Functional testing by simulating additional hardware, e.g. fault simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Quality & Reliability (AREA)
  • Tests Of Electronic Circuits (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Hardware Redundancy (AREA)
EP98200768A 1991-03-28 1992-03-30 Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung und Prozessor dafür Withdrawn EP0856795A3 (de)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB919106758A GB9106758D0 (en) 1991-03-28 1991-03-28 A system for determining the operations of an integrated circuit and processor for use therein
GB9106758 1991-03-28
EP92302794A EP0507535B1 (de) 1991-03-28 1992-03-30 Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
EP92302794A Division EP0507535B1 (de) 1991-03-28 1992-03-30 Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung

Publications (2)

Publication Number Publication Date
EP0856795A2 EP0856795A2 (de) 1998-08-05
EP0856795A3 true EP0856795A3 (de) 1998-08-19

Family

ID=10692439

Family Applications (2)

Application Number Title Priority Date Filing Date
EP98200768A Withdrawn EP0856795A3 (de) 1991-03-28 1992-03-30 Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung und Prozessor dafür
EP92302794A Expired - Lifetime EP0507535B1 (de) 1991-03-28 1992-03-30 Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP92302794A Expired - Lifetime EP0507535B1 (de) 1991-03-28 1992-03-30 Ein System zur Bestimmung des Funktionierens einer integrierten Schaltung

Country Status (4)

Country Link
US (1) US5440568A (de)
EP (2) EP0856795A3 (de)
DE (1) DE69227060T2 (de)
GB (1) GB9106758D0 (de)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5903475A (en) * 1996-07-18 1999-05-11 Lsi Logic Corporation System simulation for testing integrated circuit models
US5889685A (en) * 1996-08-02 1999-03-30 Cirrus Logic, Inc. Method and apparatus for automatically characterizing short circuit current and power consumption in a digital circuit
US6233723B1 (en) * 1997-08-28 2001-05-15 Vlsi Technology, Inc. Circuit behavioral information analysis apparatus and a method of analyzing behavioral information of a circuit
GB2364798B (en) 1999-12-03 2004-04-28 Sgs Thomson Microelectronics A processing method
US7406405B2 (en) * 2003-02-03 2008-07-29 Cadence Design Systems, Inc. Method and system for design verification using proof-based abstraction
US6944838B2 (en) * 2003-02-03 2005-09-13 Cadence Design Systems, Inc. Method and system for design verification using proof-partitioning
FR3006784B1 (fr) * 2013-06-11 2015-07-03 Inst Nat Rech Inf Automat Procede et dispositif d'elaboration automatique d'un modele de comportement d'un appareil fournissant une interface cryptographique

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888715A (en) * 1984-12-03 1989-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor test system
EP0397532A2 (de) * 1989-05-12 1990-11-14 Genrad, Inc. Simulationssystem

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3633100A (en) * 1970-05-12 1972-01-04 Ibm Testing of nonlinear circuits by comparison with a reference simulation with means to eliminate errors caused by critical race conditions
US4397021A (en) * 1981-06-15 1983-08-02 Westinghouse Electric Corp. Multi-processor automatic test system
US4901259A (en) * 1988-08-15 1990-02-13 Lsi Logic Corporation Asic emulator
US5051938A (en) * 1989-06-23 1991-09-24 Hyduke Stanley M Simulation of selected logic circuit designs
JPH03118488A (ja) * 1989-10-02 1991-05-21 Hitachi Ltd 故障シミュレーション方式
JPH04148882A (ja) * 1990-10-12 1992-05-21 Hitachi Ltd 論理集積回路の故障位置指摘方法

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4888715A (en) * 1984-12-03 1989-12-19 Mitsubishi Denki Kabushiki Kaisha Semiconductor test system
EP0397532A2 (de) * 1989-05-12 1990-11-14 Genrad, Inc. Simulationssystem

Also Published As

Publication number Publication date
US5440568A (en) 1995-08-08
EP0507535B1 (de) 1998-09-23
EP0507535A3 (en) 1993-12-01
DE69227060T2 (de) 1999-05-20
EP0507535A2 (de) 1992-10-07
GB9106758D0 (en) 1991-05-15
DE69227060D1 (de) 1998-10-29
EP0856795A2 (de) 1998-08-05

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