EP0858178A1 - Méthode et dispositif pour le mixage de signaux sonores numériques - Google Patents

Méthode et dispositif pour le mixage de signaux sonores numériques Download PDF

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Publication number
EP0858178A1
EP0858178A1 EP98100793A EP98100793A EP0858178A1 EP 0858178 A1 EP0858178 A1 EP 0858178A1 EP 98100793 A EP98100793 A EP 98100793A EP 98100793 A EP98100793 A EP 98100793A EP 0858178 A1 EP0858178 A1 EP 0858178A1
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EP
European Patent Office
Prior art keywords
bit
inputs
signals
audio signals
signal
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Granted
Application number
EP98100793A
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German (de)
English (en)
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EP0858178B1 (fr
Inventor
Andreas Von Ow
Silvio Gehri
Robert Huber
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Studer Professional Audio GmbH
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Studer Professional Audio AG
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    • HELECTRICITY
    • H04ELECTRIC COMMUNICATION TECHNIQUE
    • H04HBROADCAST COMMUNICATION
    • H04H60/00Arrangements for broadcast applications with a direct linking to broadcast information or broadcast space-time; Broadcast-related systems
    • H04H60/02Arrangements for generating broadcast information; Arrangements for generating broadcast-related information with a direct linking to broadcast information or to broadcast space-time; Arrangements for simultaneous generation of broadcast information and broadcast-related information
    • H04H60/04Studio equipment; Interconnection of studios

Definitions

  • Digital mixing consoles make it possible to use several sound signals arriving at different channels individually or collectively to any outputs.
  • the individual sound signals changed and combined with other sound signals. It means that the possibility should exist to usually add a factor to each signal multiply and add with other signals and possibly also the Delay sound signals.
  • DSP's digital signal processors
  • Known digital mixing consoles therefore have devices in which the inputs are connected in pairs or in groups to digital signal processors (DSP's) which are able to carry out such operations as addition, multiplication and storage of audio signals without problems.
  • DSP's digital signal processors
  • These problems caused by the large amount of data are usually alleviated by assigning only a small number of inputs to a signal processor, which means that for a given number of inputs and outputs, several signal processors are provided which have to be cascaded.
  • TDM buses or systems with shared memories so-called “shared memory” systems
  • shared memory so-called “shared memory” systems
  • a TDM bus is a parallel bus that provides a time window for the data from each input channel, so that the signals in the bus appear in series.
  • DPRAM memory it is also conceivable to use DPRAM memory for this and to connect the processors to one another like a so-called “daisy chain”.
  • all of these solutions are technically complex and expensive.
  • the invention as characterized in the claims therefore solves the Task a method and an apparatus for mixing digital To create audio signals that are much easier and cheaper.
  • the inputs 1 to m each lead to a processing unit 10, 11, 12, 13, which can be constructed either as a digitally operating signal processor DSP or in some other way as a unit for digital signal processing.
  • a processing unit can also be connected to a plurality of inputs, as is indicated for the processing unit 10 with the inputs 1, 2 and 3.
  • a summator 17, 18, 19, 20 is connected upstream of each output 21 to n.
  • Each Processing unit 10, 11, 12, 13 and thus each input 1 to m is connected via connections to several or ideally all outputs 21 to n. This is done for the processing unit 10 here via lines 101, 102, 103, 104 which lead from corresponding outputs on the processing units 10 to 13 to inputs on the summers 17 to 20. In Fig. 1 such inputs and outputs and part of the necessary connections are shown. All connections have been omitted to ensure the clarity of the representation.
  • the outputs, such as output 21 here can also lead to a format converter 24, which in turn can have a plurality of parallel outputs 25. This is particularly the case when audio signals from several channels are supplied in series via one input. These audio signals can then be output in parallel.
  • a further processing element 26 can be inserted into the lines 101, 102, etc., which can weaken or amplify the signal.
  • Such a further processing element 26 is connected together with the other processing elements 10 to 13 via control lines 28 to an operating unit 27 which has those operating elements which are usually present on the user interface of a mixing console.
  • the format converter 24 can also be a digital signal processor (DSP) or another signal processing element.
  • the summers 17 to 20 preferably form a sum bus in a digitally operating audio mixer.
  • Fig. 2 shows an embodiment of a summer 17 to 20.
  • Audio signals from more than four inputs 39, 40, 41, 42 will be processed the structure is supplemented by three further two-bit adders 45, 46, 47.
  • the Outputs 48, 49 of the two-bit adders 32 and 47 open into one additional two-bit adder 50.
  • Fig. 3 shows a special embodiment of a processing element 26 as it is known from FIG. 1.
  • This in turn consists of a totalizer 51 with an output 52 and, for example, three inputs 53, 54, 55.
  • Multipliers 56, 57, 58, each with two inputs 59, are connected upstream of these and 60, 61 and 62, 63 and 64.
  • Input 63 is direct for the unchanged data stream provided.
  • Received inputs 61 and 59 delays the data stream from delay units 65 or 66.
  • Lines 67 indicate first clock signals that control the processes in the bit grid.
  • the data words are in the direction of a Arrow 70 moves.
  • Each data word W is in such an order formats that the least significant bit 68 and last that most significant bit 69 occurs.
  • FIG. 5 shows a representation of data words corresponding to FIG. 4 there is a time delay between data words W11, W12 and W13 corresponding to the time period assigned to one or two or more bits is provided, which causes the data words W11, W12 and W13 to one or two or more bits are shown spatially or temporally offset.
  • the device works as follows: Digitized audio signals arrive via inputs 1 to n and are formatted in processing units 10 to 13 in a manner known per se so that the least significant bit is output first and the most significant bit is output last. This can be achieved by means of a corresponding readout instruction from a buffer store. All audio signals output by the processing units 10 to 13 or possibly also all input audio signals are synchronized with the first clock signal 67, so that each bit in the device is treated synchronously, as is shown in FIGS. 4 and 5. In addition, the data words are read out from the processing units 10 to 13 word-synchronously, as shown in FIG. 4. The individual outputs of the processing units 10 to 13 are controlled via the operating unit 27 and the control lines 28. This specifies for each output of a processing unit whether an audio signal is emitted there and to what extent.
  • Each summer 17 to 20 now receives audio signals from lines 101 to 104, etc., which it has to sum and then output to its output 21 to n. It can also happen that several audio signals arrive in series via an input. Such signals are treated in the same way as a single signal. After the output, however, they can be passed on in parallel, as is indicated for the output 21 and the parallel outputs 25.
  • the summation of the bit-synchronized audio signals in the summers 17 to 20 can be explained with the aid of FIG. 2. Two signals a and b are at the inputs 39 and 40, two further signals b and c at the inputs 41 and 42.
  • the signals a and b are summed in the two-bit adder 30 according to the following formula or instruction: (! A AND! B AND cy) OR (! A AND b AND! Cy) OR (a AND! B AND! Cy) OR (a AND b AND cy)
  • the transfer cy is treated according to the following rule: (a AND b AND! pr) OR (a AND cy AND! pr) OR (b AND cy AND!
  • the data streams thus summed leave the summer via the output 21. Then they can be formatted in the format converter 24, for example, so that the most significant bit in the data word now precedes them. Or the data stream can be divided and output in parallel over a number of lines 25.
  • the value of the input signals can be changed or weighted in the processing units 10 to 13 before the summation. However, this can also be done in a processing element 26. If the processing element 26 is designed as a device according to FIG. 3, a sound signal is fed via the input 63 to the multiplier 58 on the one hand and to the delay unit 65 on the other hand. The output signal from the delay unit 65 is fed to both the multiplier 57 and the further delay unit 66.
  • the signals applied to the multipliers 56, 57 and 58 are each offset by one bit, which is caused by the delay units 65, 66.
  • the multipliers 56, 57, 58 are also each provided with a bit of a multiplier or factor by inputs 60, 62 and 64, with which the signal in input 63 is to be multiplied.
  • a data word arriving via input 63 is multiplied bit by bit in multiplier 58 by the first bit of the factor, in adder 57 by the second bit and in adder 56 by the third bit of the factor. This results in three data words offset from one another by one bit, which are summed in summer 40. In other words, a situation arises as shown in FIG.
  • an audio signal 63 is to be divided into several identical parallel signals 63, 61, 59 and delayed by one bit each with increasing delay. Then the original signal and the delayed signals should each be added with one bit of a factor expressed in a digital value and the resulting signals should then be summed bit by bit to form a changed signal.

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  • Engineering & Computer Science (AREA)
  • Signal Processing (AREA)
  • Stereophonic System (AREA)
EP98100793A 1997-02-06 1998-01-19 Méthode et dispositif pour le mixage de signaux sonores numériques Expired - Lifetime EP0858178B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
CH262/97 1997-02-06
CH26297 1997-02-06

Publications (2)

Publication Number Publication Date
EP0858178A1 true EP0858178A1 (fr) 1998-08-12
EP0858178B1 EP0858178B1 (fr) 2006-06-21

Family

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EP98100793A Expired - Lifetime EP0858178B1 (fr) 1997-02-06 1998-01-19 Méthode et dispositif pour le mixage de signaux sonores numériques

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US (1) US6330338B1 (fr)
EP (1) EP0858178B1 (fr)
DE (1) DE59813605D1 (fr)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7062336B1 (en) * 1999-10-08 2006-06-13 Realtek Semiconductor Corp. Time-division method for playing multi-channel voice signals
DE10210443A1 (de) * 2002-03-09 2003-09-18 Bts Media Solutions Gmbh Verfahren und Vorrichtung zum Verarbeiten von Signalen
US20060023900A1 (en) * 2004-07-28 2006-02-02 Erhart George W Method and apparatus for priority based audio mixing
WO2006089148A2 (fr) * 2005-02-17 2006-08-24 Panasonic Automotive Systems Company Of America Division Of Panasonic Corporation Of North America Procede et appareil pour l'optimisation de la reproduction d'un materiau de source audio dans un systeme audio
US7869609B2 (en) * 2005-08-22 2011-01-11 Freescale Semiconductor, Inc. Bounded signal mixer and method of operation
DE102006030977A1 (de) * 2006-07-03 2008-02-07 Deutsche Thomson-Brandt Gmbh Datenübertragungsverfahren und Gerät zur Durchführung des Verfahrens
JP5246044B2 (ja) * 2009-05-29 2013-07-24 ヤマハ株式会社 音響装置

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2552958A1 (fr) * 1983-10-03 1985-04-05 Moulin Andre Console numerique de traitements de signaux
EP0342530A1 (fr) * 1988-05-11 1989-11-23 Siemens Aktiengesellschaft Österreich Réseau de commutation pour signaux audiofréquence numériques
AT389784B (de) * 1987-09-10 1990-01-25 Siemens Ag Oesterreich Verfahren zur verarbeitung und konzentration von digitalen audiosignalen
EP0462799A2 (fr) * 1990-06-21 1991-12-27 Matsushita Electric Industrial Co., Ltd. Circuit mélangeur digital

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH087941B2 (ja) * 1986-04-10 1996-01-29 ソニー株式会社 デジタル再生機器の同期方法
JPH0782423B2 (ja) * 1987-09-16 1995-09-06 三洋電機株式会社 データ入出力回路
US5524074A (en) * 1992-06-29 1996-06-04 E-Mu Systems, Inc. Digital signal processor for adding harmonic content to digital audio signals
US5592403A (en) * 1993-03-11 1997-01-07 Monolith Technologies Corporation Digital-to-analog converter including integral digital audio filter
JP3443938B2 (ja) * 1994-03-31 2003-09-08 ソニー株式会社 ディジタル信号処理装置
US5621805A (en) * 1994-06-07 1997-04-15 Aztech Systems Ltd. Apparatus for sample rate conversion
US5517433A (en) * 1994-07-07 1996-05-14 Remote Intelligence, Inc. Parallel digital data communications
US5647008A (en) * 1995-02-22 1997-07-08 Aztech Systems Ltd. Method and apparatus for digital mixing of audio signals in multimedia platforms
US5774567A (en) * 1995-04-11 1998-06-30 Apple Computer, Inc. Audio codec with digital level adjustment and flexible channel assignment
GB2301003B (en) * 1995-05-19 2000-03-01 Sony Uk Ltd Audio mixing console
US5703794A (en) * 1995-06-20 1997-12-30 Microsoft Corporation Method and system for mixing audio streams in a computing system
FR2743228B1 (fr) * 1995-12-29 1998-03-20 Sgs Thomson Microelectronics Systeme de melange et de numerisation de signaux analogiques

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2552958A1 (fr) * 1983-10-03 1985-04-05 Moulin Andre Console numerique de traitements de signaux
AT389784B (de) * 1987-09-10 1990-01-25 Siemens Ag Oesterreich Verfahren zur verarbeitung und konzentration von digitalen audiosignalen
EP0342530A1 (fr) * 1988-05-11 1989-11-23 Siemens Aktiengesellschaft Österreich Réseau de commutation pour signaux audiofréquence numériques
EP0462799A2 (fr) * 1990-06-21 1991-12-27 Matsushita Electric Industrial Co., Ltd. Circuit mélangeur digital

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
TERUO FUJINO ET AL: "DIGITAL MIXING CONSOLE MEETS PROFESSIONAL MIXING NEEDS", JEE JOURNAL OF ELECTRONIC ENGINEERING, vol. 28, 1 January 1991 (1991-01-01), pages 38 - 42, XP000230856 *

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DE59813605D1 (de) 2006-08-03
EP0858178B1 (fr) 2006-06-21
US6330338B1 (en) 2001-12-11

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