EP0903062A1 - Pattes de raccordement aux conducteurs d'une plaque de cablage pour circuit imprime a conducteurs - Google Patents

Pattes de raccordement aux conducteurs d'une plaque de cablage pour circuit imprime a conducteurs

Info

Publication number
EP0903062A1
EP0903062A1 EP97927883A EP97927883A EP0903062A1 EP 0903062 A1 EP0903062 A1 EP 0903062A1 EP 97927883 A EP97927883 A EP 97927883A EP 97927883 A EP97927883 A EP 97927883A EP 0903062 A1 EP0903062 A1 EP 0903062A1
Authority
EP
European Patent Office
Prior art keywords
printed wiring
lead
wiring board
lead attach
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP97927883A
Other languages
German (de)
English (en)
Inventor
Graham J. H. Wells
Christopher L. Caron
Paul J. Schwab
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Whitaker LLC
Original Assignee
Whitaker LLC
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Whitaker LLC filed Critical Whitaker LLC
Publication of EP0903062A1 publication Critical patent/EP0903062A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/243—Reinforcing of the conductive pattern characterised by selective plating, e.g. for finish plating of pads
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/117—Pads along the edge of rigid circuit boards, e.g. for pluggable connectors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0237—High frequency adaptations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/09372—Pads and lands
    • H05K2201/09481—Via in pad; Pad over filled via
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09627—Special connections between adjacent vias, not for grounding vias
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/04—Soldering or other types of metallurgic bonding
    • H05K2203/049—Wire bonding
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13—Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377—Protective layers
    • H05K2203/1394—Covering open PTHs, e.g. by dry film resist or by metal disc
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0094—Filling or covering plated through-holes or blind plated vias, e.g. for masking or for mechanical reinforcement
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/24—Reinforcing of the conductive pattern
    • H05K3/241—Reinforcing of the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus
    • H05K3/242—Reinforcing of the conductive pattern characterised by the electroplating method; means therefor, e.g. baths or apparatus characterised by using temporary conductors on the printed circuit for electrically connecting areas which are to be electroplated
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3405—Edge mounted components, e.g. terminals
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3465—Application of solder
    • H05K3/3473—Plating of solder
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/42—Plated through-holes or plated via connections
    • H05K3/429—Plated through-holes specially for multilayer circuits, e.g. having connections to inner circuit layers

Definitions

  • the present invention relates to chip on board devices and more particularly to a printed wiring board substrate having an improved lead attach area.
  • the interest of miniaturization of electronic instrumentation has led to the desirability of mounting integrated circuit die directly onto a printed wiring board substrate.
  • Integrated circuit die contacts are wire bonded to conductive traces on the printed wiring board to create a circuit.
  • the die and wire bonds are covered by an encapsulent, colloquially referred to as "glob top”.
  • the populated printed wiring board assembly is referred to as a "chip on board” device.
  • the chip on board device substrate has a lead attach area comprising a plurality of electrically conductive lead attach fingers around a perimeter of the printed wiring board substrate. Leads of a lead frame are attached to respective lead attach fingers. Attachment of the lead frame to the chip on board device is typically done by means of soldering. Trimming of the lead frame that is attached to the chip on board substrate results in a leaded chip on board device.
  • the leads are then formed according to conventional practice.
  • the leaded device is attached to a larger printed wiring board to create an assembly.
  • the lead attach fingers prefferably be plated with tin-lead.
  • the tin-lead plating provides for a high quality solder joint between the lead frame and the lead attach area and environmentally protects the underlying copper.
  • the conductive traces providing for interconnection between devices and components on the chip on board substrate to be plated with gold.
  • gold wire bonding for interconnection between the conductive traces on the chip on board device and the die.
  • a gold wire bond requires soft, high purity gold plating on the conductive traces of the printed wiring board substrate for an optimum interconnect between the trace and the wire bond.
  • the tin-lead plating and the nickel-gold plating provide corrosion protection for the copper circuitry of the printed wiring board substrate.
  • acid in the gold plating bath degrades the tin-lead plating where the tin-lead is exposed at the edge of the photoresist (18) .
  • Figure 1 of the drawings Degradation of the tin-lead plating creates an area of unprotected copper where the tin-lead has been etched away by the acid in the gold bath.
  • a prior solution comprises a thin abutment line of photoimageable soldermask at a distance distal from the perimeter of the printed wiring substrate.
  • the abutment line is applied to cover the intermetallic abutment.
  • the abutment line of soldermask serves to environmentally protect the intermetallic abutment and to prevent solder from flowing into the nickel-gold plating.
  • the chip on board device includes a lid that covers the top of the device.
  • the lid is attached with epoxy to the chip on board device just inside the perimeter of the chip on board device substrate.
  • the abutment line is therefore, just inside and concentric with the area of lid attachment. It is important that the area of lid attach be clear of the abutment line because stresses placed on the lid could exceed the strength of the adhesion of the abutment line to the substrate. If the lid attach overlapped the abutment line, the abutment line could be pulled off the substrate resulting in a defective part.
  • the abutment line is optimally, therefore, only as thick as is required to cover the intermetallic abutment. Challenges associated with the abutment line of soldermask to environmentally protect the intermetallic abutment include proper registration of the abutment line.
  • a chip on board device in which a printed wiring board substrate has lead attach fingers wherein all of the lead attaches are electrically connected to conductive traces on the printed wiring board substrate through a via.
  • Figure 1 is a cross section of an intermetallic abutment and photoresist covered lead finger according to conventional practice showing the attendant degradation after gold plating.
  • Figures 2 and 3 illustrate conductive layers of copper for a top side and a bottom side of a multilayer chip on board device having an intermetallic abutment between lead attach fingers and conductive traces.
  • Figure 4 illustrates the solder mask layers for the top side of the chip on board device of Figures 2 and 3 showing an abutment line.
  • Figure 5 illustrates a cross section of a lead attach finger according to the teachings of the present invention. Showing full coverage of the lead attach finger by photoresist.
  • Figure 6 and 7 illustrate conductive layers of copper for a top side and a bottom side of a multilayer chip on board printed wiring board having lead attach fingers according to the teachings of the present invention.
  • Figure 8 illustrates a solder mask layers for the top side of the chip on board device of Figures 6 and 7.
  • Figure 9 and 10 illustrate cross sections of a leaded chip on board according to the teachings of the present invention cut along lines 9-9 and 10-10 respectively in Figure 6.
  • Figures 11 and 12 illustrate cross sections of a base grid array chip on board device according to the teachings of the present invention.
  • a chip on board device comprises printed wiring board substrate (1) having multiple layers of a polyimide electrically insulating material.
  • the printed wiring board is similar to that disclosed in U.S. patent applications serial no. 08/621,304 and application serial no. 08/620,765, the teachings of which are specifically incorporated by reference herein.
  • Each layer of polyimide has conductive areas or traces (2) thereon.
  • a preferred printed wiring board polyimide and prepreg is the N 7000-1 series manufactured by New England Laminates Company, Inc., a subsidiary of Park Electro Chemical Corporation. The N 7205-1 laminate and N 7305-1 prepreg is preferred.
  • vias (3) on and through the substrate (l) provide electrical conductivity from a top side (4) of the printed wiring board substrate (1) to intermediate layers and/or to a bottom side (5) of the printed wiring board substrate (1) .
  • a via (3) carries either ground potential, direct current, radio frequency or microwave signal to effect a desired circuit.
  • the via (3) as is conventionally known comprises an annular rim (6) of substrate (1) having an inner cylindrical surface (7) .
  • the inner cylindrical surface (7) is plated with a layer of a conductive material, typically metal and preferably copper. Electrical connection is made to one or more layers of the printed wiring board substrate (1) including, for example ground plane (8) , by contacting a conductive trace (2) to the plated inner cylindrical surface (7) .
  • DC, RF, and microwave signal vias (3) are not electrically connected to a ground plane.
  • the ground plane layers (8) have an insulating ring surrounding all signal and RF vias (3) .
  • the via (3) necessarily creates an evacuated area or plated through hole in the printed wiring board substrate (1) . Due to the aforementioned reliability and manufacturability problems associated with the intermetallic abutment (19) between the lead attach finger (16) and the conductive trace (2) , it is suggested herein to eliminate the intermetallic abutment for all lead attach fingers (16) .
  • first and second lead attach vias (21,22) to interconnect all lead attach fingers (16) to the appropriate conductive trace (2) and/or ground plane (8) .
  • the first lead attach via (21) electrically communicates with an interconnecting trace (23) on one of the intermediate layers of the printed wiring board (1) .
  • the interconnecting trace (23) connects to the first lead attach via (21) and extends for a distance to electrically connect to the second lead attach via (22) .
  • the second lead attach via (22) interconnects the interconnecting trace (23) to the top side conductive layer.
  • the interconnecting trace (23) therefore, creates a physical separation between an end of the tin- lead plated lead attach finger (16) distal from a perimeter of the printed wiring board and an end of the nickel-gold plated conductive trace (2) and/or ground the plane (8) proximal to the perimeter of the printed wiring board.
  • the physical separation advantageously obviates the need for an intermetallic abutment, and hence an abutment line and permits complete masking of the tin-lead plated lead attach fingers (16) prior to the gold plating bath. See Figure 5 of the drawings for example.
  • the physical separation further advantageously provides an area within which normal manufacturing tolerances of the mask alignment do not adversely affect or compromise the intended function of the photoresist mask in the lead attach area.
  • the intermediate ground plane layers carry the same electrical potential as outer conductive layers which also have a ground plane thereon.
  • the intermediate layers of the printed wiring board substrate are ground planes (8) . Therefore, interconnection of all ground planes (8) in the multilayer printed wiring board as well as all lead attach fingers (16) carrying ground potential is appropriately achieved through the lead attach vias (21,22) without any degradation in high frequency performance.
  • each lead attach finger (16) has a first width and is electrically connected to a secondary conductive trace (20) .
  • the first width of the lead attach finger (16) is appropriately sized to register with a width of the leads (24) on the lead frame according to conventional practice.
  • the secondary conductive trace (20) has a second width and is electrically connected to a first lead attach via (21) .
  • the second width of the secondary conductive trace (20) is less than the first width of the lead attach (16) .
  • the second width of the secondary conductive trace (20) provides an advantage during the process step of attaching the lead frame to the printed wiring board substrate (1) .
  • the lead attach finger (16) gets hotter, faster and minimizes the chip on board device's exposure to temperature extremes.
  • the smaller width of the secondary conductive trace (20) also minimizes the volume of solder wicked toward the first lead attach via (21) which concentrates the solder at the end of the lead attach finger (16) .
  • an alternate embodiment comprises a ball grid array (BGA) attachment method.
  • BGA ball grid array
  • a conductive mass or ball (25) is disposed on a bottom side or attachment side of the printed wiring board substrate. Attachment of the chip on board to the larger printed wiring board could be by means of solder reflow. All connections to the chip on board circuit would be made by way of a via (21) and an interconnecting trace (23) .

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)

Abstract

Une plaque de câblage pour circuit imprimé ayant des pattes de raccordement aux conducteurs élimine une jonction métallique (19) classique entre les pattes de raccordement aux conducteurs (16) et les conducteurs placés sur les couches extérieures de la plaque à circuit imprimé (1). Toutes les pattes de raccordement aux conducteurs (16) sont électriquement connectées aux conducteurs (2) à travers des trous d'interconnexion (21, 22). Les trous d'interconnexion (21, 22) ont un tracé d'interconnexion (23) gravé sur une couche intermédiaire de la plaque à circuit imprimé (1).
EP97927883A 1996-05-31 1997-05-29 Pattes de raccordement aux conducteurs d'une plaque de cablage pour circuit imprime a conducteurs Withdrawn EP0903062A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US65610796A 1996-05-31 1996-05-31
US656107 1996-05-31
PCT/US1997/009351 WO1997046063A1 (fr) 1996-05-31 1997-05-29 Pattes de raccordement aux conducteurs d'une plaque de cablage pour circuit imprime a conducteurs

Publications (1)

Publication Number Publication Date
EP0903062A1 true EP0903062A1 (fr) 1999-03-24

Family

ID=24631656

Family Applications (1)

Application Number Title Priority Date Filing Date
EP97927883A Withdrawn EP0903062A1 (fr) 1996-05-31 1997-05-29 Pattes de raccordement aux conducteurs d'une plaque de cablage pour circuit imprime a conducteurs

Country Status (3)

Country Link
EP (1) EP0903062A1 (fr)
JP (1) JP2000515315A (fr)
WO (1) WO1997046063A1 (fr)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP2124436B1 (fr) * 2008-05-23 2012-04-18 Novabase Digital TV Technologies GmbH Appareil de réception télévisée numérique
TWI704852B (zh) 2018-11-28 2020-09-11 先豐通訊股份有限公司 電路板的電鍍方法及其所製成的電路板

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4437141A (en) * 1981-09-14 1984-03-13 Texas Instruments Incorporated High terminal count integrated circuit device package
JPS63175438A (ja) * 1987-01-14 1988-07-19 Sharp Corp プリント基板へのｉｃ実装方法
JP2926956B2 (ja) * 1990-10-09 1999-07-28 富士通株式会社 プリント基板
JP2909223B2 (ja) * 1990-12-28 1999-06-23 イビデン株式会社 プリント配線板の導体パターンメッキ方法
JP2783093B2 (ja) * 1992-10-21 1998-08-06 日本電気株式会社 プリント配線板

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See references of WO9746063A1 *

Also Published As

Publication number Publication date
WO1997046063A1 (fr) 1997-12-04
JP2000515315A (ja) 2000-11-14

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