EP0933708A3 - Integrieter Speicher mit Fehlerkorrekturdaten in einer Betriebsart - Google Patents
Integrieter Speicher mit Fehlerkorrekturdaten in einer Betriebsart Download PDFInfo
- Publication number
- EP0933708A3 EP0933708A3 EP99101470A EP99101470A EP0933708A3 EP 0933708 A3 EP0933708 A3 EP 0933708A3 EP 99101470 A EP99101470 A EP 99101470A EP 99101470 A EP99101470 A EP 99101470A EP 0933708 A3 EP0933708 A3 EP 0933708A3
- Authority
- EP
- European Patent Office
- Prior art keywords
- operating mode
- featuring
- error correcting
- correcting data
- integrated storage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/52—Protection of memory contents; Detection of errors in memory contents
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/38—Response verification devices
- G11C29/42—Response verification devices using error correcting codes [ECC] or parity check
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/88—Masking faults in memories by using spares or by reconfiguring with partially good memories
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1048—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices using arrangements adapted for a specific error detection or correction feature
- G06F11/1052—Bypassing or disabling error detection or correction
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Quality & Reliability (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Abstract
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19804035A DE19804035A1 (de) | 1998-02-02 | 1998-02-02 | Integrierter Speicher |
| DE19804035 | 1998-02-02 |
Publications (3)
| Publication Number | Publication Date |
|---|---|
| EP0933708A2 EP0933708A2 (de) | 1999-08-04 |
| EP0933708A3 true EP0933708A3 (de) | 1999-12-15 |
| EP0933708B1 EP0933708B1 (de) | 2003-08-20 |
Family
ID=7856404
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| EP99101470A Expired - Lifetime EP0933708B1 (de) | 1998-02-02 | 1999-01-27 | Integrierter Speicher mit Fehlerkorrekturdaten in einer Betriebsart |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6216248B1 (de) |
| EP (1) | EP0933708B1 (de) |
| DE (2) | DE19804035A1 (de) |
| TW (1) | TW508581B (de) |
Families Citing this family (14)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7111224B1 (en) * | 2001-02-28 | 2006-09-19 | Xilinx, Inc. | FPGA configuration memory with built-in error correction mechanism |
| US6785782B1 (en) * | 2001-09-10 | 2004-08-31 | Rambus Inc. | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules |
| US6769050B1 (en) * | 2001-09-10 | 2004-07-27 | Rambus Inc. | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules |
| US6636935B1 (en) * | 2001-09-10 | 2003-10-21 | Rambus Inc. | Techniques for increasing bandwidth in port-per-module memory systems having mismatched memory modules |
| DE10145727B4 (de) * | 2001-09-17 | 2013-07-11 | Qimonda Ag | Verfahren und Vorrichtung zum Verringern des Stromverbrauchs einer elektronischen Schaltung |
| US6904540B2 (en) | 2001-10-29 | 2005-06-07 | Hewlett-Packard Development Company, L.P. | Targeted data protection |
| US20060218467A1 (en) * | 2005-03-24 | 2006-09-28 | Sibigtroth James M | Memory having a portion that can be switched between use as data and use as error correction code (ECC) |
| US20080052598A1 (en) * | 2006-08-09 | 2008-02-28 | Aksamit Slavek P | Memory multi-bit error correction and hot replace without mirroring |
| US9373377B2 (en) | 2011-11-15 | 2016-06-21 | Micron Technology, Inc. | Apparatuses, integrated circuits, and methods for testmode security systems |
| KR20160017922A (ko) * | 2014-08-07 | 2016-02-17 | 에스케이하이닉스 주식회사 | 반도체 메모리 장치 |
| JP6527054B2 (ja) | 2015-08-28 | 2019-06-05 | 東芝メモリ株式会社 | メモリシステム |
| KR20170035103A (ko) * | 2015-09-22 | 2017-03-30 | 삼성전자주식회사 | 반도체 메모리 장치 및 이를 포함하는 메모리 시스템 |
| GB2578420B (en) * | 2018-08-08 | 2023-03-29 | Trw Ltd | A sensing apparatus |
| US11340979B2 (en) * | 2019-12-27 | 2022-05-24 | Seagate Technology Llc | Mitigation of solid state memory read failures with a testing procedure |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4528666A (en) * | 1983-01-03 | 1985-07-09 | Texas Instruments Incorporated | Memory system with built in parity |
| EP0184737A2 (de) * | 1984-12-04 | 1986-06-18 | Kabushiki Kaisha Toshiba | Halbleiterspeichergerät mit Fehlererkennung/Korrekturfunktion |
| US5493574A (en) * | 1992-09-24 | 1996-02-20 | Zilog, Inc. | Power efficient RAM disk and a method of emulating a rotating memory disk |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4319356A (en) * | 1979-12-19 | 1982-03-09 | Ncr Corporation | Self-correcting memory system |
| DE4329012A1 (de) * | 1993-08-28 | 1995-03-02 | Sel Alcatel Ag | Verfahren und Vorrichtung zur Fehlerprüfung und zur Fehlerkorrektur in Speicherbausteinen |
| JPH10198608A (ja) * | 1997-01-08 | 1998-07-31 | Mitsubishi Electric Corp | メモリカード |
-
1998
- 1998-02-02 DE DE19804035A patent/DE19804035A1/de not_active Withdrawn
-
1999
- 1999-01-27 DE DE59906620T patent/DE59906620D1/de not_active Expired - Fee Related
- 1999-01-27 EP EP99101470A patent/EP0933708B1/de not_active Expired - Lifetime
- 1999-02-02 TW TW088101493A patent/TW508581B/zh not_active IP Right Cessation
- 1999-02-02 US US09/243,296 patent/US6216248B1/en not_active Expired - Lifetime
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4528666A (en) * | 1983-01-03 | 1985-07-09 | Texas Instruments Incorporated | Memory system with built in parity |
| EP0184737A2 (de) * | 1984-12-04 | 1986-06-18 | Kabushiki Kaisha Toshiba | Halbleiterspeichergerät mit Fehlererkennung/Korrekturfunktion |
| US5493574A (en) * | 1992-09-24 | 1996-02-20 | Zilog, Inc. | Power efficient RAM disk and a method of emulating a rotating memory disk |
Non-Patent Citations (1)
| Title |
|---|
| HIDETO HIDAKA ET AL: "THE CACHE DRAM ARCHITECTURE: A DRAM WITH AN ON-CHIP CACHE MEMORY", IEEE MICRO, vol. 10, no. 2, 1 April 1990 (1990-04-01), pages 14 - 25, XP000116649, ISSN: 0272-1732 * |
Also Published As
| Publication number | Publication date |
|---|---|
| TW508581B (en) | 2002-11-01 |
| DE19804035A1 (de) | 1999-08-05 |
| DE59906620D1 (de) | 2003-09-25 |
| EP0933708B1 (de) | 2003-08-20 |
| US6216248B1 (en) | 2001-04-10 |
| EP0933708A2 (de) | 1999-08-04 |
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