EP0995228A1 - Procede de gravure a double damasquinage - Google Patents

Procede de gravure a double damasquinage

Info

Publication number
EP0995228A1
EP0995228A1 EP98915322A EP98915322A EP0995228A1 EP 0995228 A1 EP0995228 A1 EP 0995228A1 EP 98915322 A EP98915322 A EP 98915322A EP 98915322 A EP98915322 A EP 98915322A EP 0995228 A1 EP0995228 A1 EP 0995228A1
Authority
EP
European Patent Office
Prior art keywords
interconnect
contact
interlevel dielectric
masking layer
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98915322A
Other languages
German (de)
English (en)
Inventor
Basab Bandyopadhyay
Michael J. Gatto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Advanced Micro Devices Inc
Original Assignee
Advanced Micro Devices Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices Inc filed Critical Advanced Micro Devices Inc
Publication of EP0995228A1 publication Critical patent/EP0995228A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/087—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving multiple stacked pre-patterned masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H10W20/084—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures
    • H10W20/088—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts for dual-damascene structures involving partial etching of via holes

Definitions

  • the present invention relates to the field of semiconductor processing and more particularly to a method of forming a second or subsequent interconnect layer and a contact to first or a previously formed interconnect layer.
  • Modern integrated circuits typically include a plurality of interconnect levels. Multiple interconnect levels are needed in high density integrated circuits to alleviate the density of interconnects within a given interconnect level.
  • a multiple interconnect level integrated circuit process includes the initial steps of forming a transistor level, which includes a plurality of transistors within a silicon wafer substrate. The plurality of transistors are isolated from one another by isolation structures also formed within or upon the silicon substrate.
  • typical semiconductor processes include a series of process steps designed to produce multiple interconnect levels. In a typical sequence, an oxide layer is deposited upon the previous interconnect level. The oxide layer is then selectively etched to produce contact tunnels at desired locations within the oxide layer. The contact tunnels terminate on portions of a previous interconnect level.
  • the contact tunnels After the contact tunnels have been formed, it is necessary to fill the contacts with a conductive material such as aluminum to provide a conductive path from the preceding interconnect level to the subsequently formed interconnect level.
  • a conductive material such as aluminum
  • the contact tunnels were typically filled during the same deposition process used to deposit the metal used for the subsequent interconnect level.
  • a single, aluminum sputtering process could be used to fill the contact tunnels and to form the subsequent metal layer.
  • the aspect ratio of typical contact tunnels has increased to the point where aluminum sputtering techniques are now typically inadequate to completely fill the contact tunnel with a aluminum.
  • the filling of the contact tunnel typically required a dedicated processing step such as a CVD or tungsten deposition step to fill the contact tunnels with a conductive material prior to forming the interconnect layer.
  • a metal layer could then be deposited with a sputtering technique and the metal layer patterned with a conventional photolithography process.
  • Processing interconnect layers in this manner undesirably requires separate deposition processes for the deposition of the contacts and the deposition of the interconnect level.
  • the deposition of the contact is typically followed by a planarization process such as a chemical mechanical polish that is frequently required to produce a substantially planar upper surface prior to the deposition of the subsequent interconnect level.
  • planarization process such as a chemical mechanical polish that is frequently required to produce a substantially planar upper surface prior to the deposition of the subsequent interconnect level.
  • the typical technique of forming the subsequent interconnect level by sputter depositing a metal layer, covering the metal layer with a patterned photoresist mask, and etching the metal frequently produces inadequate results in semiconductor processes in which the metal pitch is less than approximately 1 micron because of the difficulty in achieving substantially vertical interconnect sidewalls and in subsequently filling the spaces between adjacent interconnects with an insulating dielectric.
  • damascene processes have been developed to improve the profiles of the metal interconnect.
  • metal is deposited into a trench previously formed within a dielectric layer trench. The trench is typically etched into a dielectric layer. A metal is then blanket deposited over the dielectric layer to fill the trenches.
  • portions of the deposited metal exterior to the trenches can be removed with a chemical mechanical polish or other planarization process.
  • the damascene process is desirable because the sidewalls profile of each interconnect is defined by patterning and etching a dielectric layer such as a CVD oxide rather than through the patterning of the metal itself.
  • the difficulty of achieving substantially vertical interconnect sidewalls through the use of a metal etch process are well known in the field of semiconductor processing.
  • a damascene process results in a substantially planar semiconductor surface upon which a subsequent interconnect level may be readily fabricated.
  • the interconnect level forms a non-planar topography with the dielectric layer upon which it sits.
  • the problems identified above are in large part addressed by a dual damascene process in which the pattern for the contacts and the pattern for the subsequent interconnect level are simultaneously present prior to the deposition of the appropriate conductive material.
  • the subsequent interconnect level is fabricated with a damascene process eliminating the undesirable etch processes of previous semiconductor technologies.
  • preferred embodiments of the present invention contemplate the integration of the process steps required to form the contact tunnels and the interconnect trenches and further contemplates the integration of the metal deposition process. In these embodiments, the reduced processing typically results in a lower cost and higher yield per wafer.
  • the present invention contemplates a semiconductor process in which a semiconductor substrate is provided.
  • the semiconductor substrate includes a first interconnect level.
  • An interlevel dielectric layer is formed on the semiconductor substrate and a contact masking layer is formed on the interlevel dielectric.
  • a pattern of the contact masking layer is aligned over a contact region of the interlevel dielectric.
  • An interconnect masking layer is then formed on the contact masking layer.
  • a pattern of the interconnect masking layer is aligned over an interconnect region of the interlevel dielectric layer. Portions within the contact region of the interlevel dielectric layer are then selectively removed using the contact masking layer as a mask.
  • Portions of the contact masking layer exposed by the pattern of the interconnect masking layer are then removed to expose an upper surface of the interconnect region of the interlevel dielectric layer. Portions of the interconnect region of the interlevel dielectric layer are then selectively removed using the interconnect masking layer as a mask to form an interconnect trench. The interconnect masking layer and any remaining portions of the contact masking layer are then removed. The contact tunnel and the interconnect trench are then filled with a conductive material.
  • the formation of the interlevel dielectric layer is accomplished by decomposing TEOS in a chemical vapor deposition reactor chamber that is maintained at a temperature of less than approximately 650°C at a pressure of less than approximately 2 torrs.
  • the formation of the contact masking layer includes depositing a silicon nitride layer on the interlevel dielectric layer and patterning the silicon nitride layer to remove portions of the silicon nitride layer over the contact region of the interlevel dielectric level.
  • Depositing silicon nitride is preferably accomplished by decomposing silane and NH 3 in a • chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 600°C to 900°C and a pressure of less than approximately 2 torrs.
  • Removing the portions of the contact masking layer exposed by the pattern of the interconnect masking layer and removing the remaining portions of the contact masking layer both comprise, in one embodiment, immersing the semiconductor substrate into an 85% phosphoric acid solution maintained at a temperature of approximately 100°C.
  • the formation of the interconnect masking layer is preferably accomplished by depositing a photoresist layer on the contact masking layer and selectively removing portions of the photoresist layer that are aligned over the interconnect regions of the interlevel dielectric layer.
  • the step of selectively removing portions of the contact region preferably comprises the anisotropic etch of the interlevel dielectric layer in a reactive ion etcher.
  • the formation of the interconnect masking layer precedes the step of selectively removing portions of the contact region.
  • the interconnect masking layer and the contact masking layer are simultaneously present upon the interlevel dielectric layer prior to the formation of the contact tunnels.
  • the selective removal of portions of the interconnect region is ideally accomplished with an anisotropic etch of the interlevel dielectric layer in a reactive ion etcher.
  • the boundaries of the contact tunnel region of the interlevel dielectric layer are suitably displaced between boundaries of the interconnect region of the interlevel dielectric layer.
  • the steps of selectively removing portions of the contact region, removing portions of the contact masking layer, and selectively removing portions of the interconnect region are all accomplished in a single reactive ion etcher using a single pump down cycle.
  • the filling of the contact tunnel and the filling of the interconnect trench are accomplished simultaneously.
  • the filling of the contact tunnel and the interconnect trench include depositing a metal of aluminum, copper, tungsten, titanium, or an alloy thereof.
  • the depositing of the metal into the contact tunnel and the interconnect trench is preferably accomplished in a chemical vapor deposition reactor chamber.
  • the depositing of the metal is preceded by depositing an adhesion layer on sidewalls of the contact tunnel and the interconnect trench.
  • the selective removal of portions of the interconnect region has the effect of vertically translating the contact tunnel within the interlevel dielectric such that the contact tunnel extends to an upper surface of the first interconnect level of the semiconductor substrate.
  • the present invention still further contemplates a semiconductor process in which a semiconductor substrate is provided and an interlevel dielectric level is deposited on an upper surface of the semiconductor substrate.
  • a contact tunnel is then formed within a contact region of the interlevel dielectric layer.
  • a depth of the contact tunnel is less than a thickness of the interlevel dielectric layer.
  • An interconnect trench is then formed within an interconnect region of the interlevel dielectric layer.
  • the forming of the interconnect trench has the effect of vertically translating the contact tunnel within the interlevel dielectric layer such that the contact tunnel extends to an upper surface of the semiconductor substrate. Tliereafter, the contact tunnel and the interconnect trench are filled with a conductive material.
  • the semiconductor substrate includes a silicon substrate and a first interconnect level formed above the silicon substrate.
  • the deposition of the interlevel dielectric layer preferably comprises decomposing TEOS in a C VD reactor chamber maintained at a temperature of less than approximately 650°C and a pressure of less than approximately two torrs.
  • the formation of the contact tunnel includes forming a contact masking layer on the interlevel dielectric layer. The contact masking layer is aligned over a contact region of the interlevel dielectric layer such that an upper surface of the contact region is exposed by the contact masking layer. Thereafter, portions of the contact region of the interlevel dielectric layer are removed with a reactive ion etcher.
  • the formation of the contact masking layer preferably includes the steps of depositing a silicon nitride layer on an upper surface of the interlevel dielectric layer, forming a patterned photoresist mask on an upper surface of the silicon nitride layer, and removing portions of the silicon nitride layer exposed by the photoresist mask with a silicon nitride etch process.
  • the process further includes the step of forming an interconnect masking layer on an upper surface of the contact masking layer after the contact mask has been formed but prior to the formation of the interconnect trench.
  • the etching of the interconnect trench preferably includes the steps of forming an interconnect mask layer above the semiconductor substrate.
  • the interconnect masking layer exposes an upper surface of the interconnect region of the interlevel dielectric layer. Exposed portions of the interconnect region of the interlevel dielectric layer are then anisotropically removed using a reactive ion etcher.
  • the formation of the interconnect masking layer suitably occurs before the etching of the contact tunnel. In this manner the interconnect masking layer is formed on an upper surface of a contact masking layer that is formed on an upper surface of the interlevel dielectric layer.
  • the filling of the contact tunnel and the interconnect trench are accomplished simultaneously in the presently preferred embodiment.
  • the filling of the contact tunnel and the interconnect trench is preferably accomplished by depositing a metal such as aluminum, copper, tungsten, titanium, or alloys thereof.
  • the deposition is ideally accomplished in a chemical vapor deposition reactor chamber.
  • the deposition step is preceded, in one embodiment, by depositing an adhesion layer on sidewalls of the contact tunnel and the interconnect trench.
  • the present invention still further contemplates a semiconductor process in which a semiconductor substrate is provided, an interlevel dielectric layer is deposited on an upper surface of the semiconductor substrate, an interconnect/contact opening is formed in the interlevel dielectric, and the interconnect/contact opening is filled with a conductive material.
  • the interconnect/contact opening includes an interconnect trench formed within an upper region of the upper level dielectric layer and further includes a contact tunnel that communicates an upper surface of the semiconductor substrate with the interconnect trench.
  • the filling of the interconnect/contact opening is accomplished with a single deposition step in a preferred embodiment.
  • a width of the interconnect trench is greater than a width of the contact tunnel such that sidewalls of the contact tunnel are laterally displaced between sidewalls of the interconnect trench.
  • Fig. 1 is a partial cross-sectional view of the semiconductor substrate including a first interconnect level:
  • Fig. 2 is a processing step subsequent to Fig. 1 in which an interlevel dielectric layer has been formed on the semiconductor substrate:
  • Fig. 3 is a processing step subsequent to Fig. 2 in which a contact masking layer has been formed on the interlevel dielectric layer aligned over a contact region of the interlevel dielectric layer,
  • Fig. 4 is processing step subsequent to Fig. 3 in which an interconnect masking layer has been formed on the contract masking layer.
  • Fig. 5 is a processing step subsequent to Fig. 4 in which the interconnect masking layer has been patterned and aligned over an interconnect region of the interlevel dielectric layer;
  • Fig. 6 is processing step subsequent to Fig. 5 in which portions of the interlevel dielectric layer within the contact region have been removed;
  • Fig. 7 is a processing step subsequent to Fig. 6 in which portions of the contact masking layer exposed by the pattern of the interconnect masking layer have been removed to expose an upper surface of the interconnect region of the interlevel dielectric layer;
  • Fig. 8 is a processing step subsequent to Fig. 7 in which portions of the interconnect region of the interlevel dielectric layer are then selectively removed using the interconnect masking layer as a mask to form an interconnect trench:
  • Fig. 9 is a processing step subsequent to Fig. 8 in which the interconnect trench is filled with a conductive material.
  • Fig. 1 through 9 disclose a processing sequence for f ⁇ ning a second interconnect level and connecting the second interconnect level with a first interconnect level according to the present invention.
  • semiconductor substrate 102 is provided.
  • Semiconductor substrate 102 preferably includes a silicon substrate 104 upon which a first interconnect level 108 is formed within upper region 106 of semiconductor substrate 102.
  • a suitable starting material for silicon substrate 104 useful in the fabrication of CMOS integrated circuits includes a p-type epitaxial layer formed over a p+ silicon bulk.
  • a preferred resistivity of the p-type epitaxial layer is in the range of approximately 10 to 15 ⁇ -cm.
  • first interconnect level 108 is a metal or metal alloy interconnect level as are well known in the field of semiconductor processing. It is to be understood, however, that the first interconnect level may comprise a plurality of transistors fabricated within silicon substrate 104. The significance of the present invention does not lie in the composition of the preceding interconnect level but rather in the method of fabricating a subsequent interconnect level and a contact structure to the preceding interconnect level.
  • CMOS integrated circuits such as microprocessors and other complex logic devices.
  • an interlevel dielectric layer 110 is formed on an upper surface 101 of semiconductor substrate 102.
  • Interconnect dielectric layer 110 includes a contact region 112 bounded by first and second contact region boundaries 112a and 1 12b respectively.
  • Interlevel dielectric layer 110 further includes an interconnect region 114 bounded by first and second interconnect region boundaries 114a and 114b.
  • First and second contact region boundaries 112a and 1 12b are laterally displaced between first and second interconnect region boundaries 1 14a and 114b.
  • a preferred method of fabricating interlevel dielectric layer 110 includes the steps of decomposing TEOS in a chemical vapor deposition reactor chamber maintained at a temperature of less than approximately 650°C and a pressure of less than approximately two torrs.
  • a preferred thickness of interlevel dielectric layer 1 10 is equal to a first displacement d, (shown in greater detail and described with respect to Fig. 6) and a second displacement d ; (shown in greater detail and described with respect to Fig. 8) which represent the height of the contact structure and a thickness of the second interconnect level respectively.
  • a thickness of interlevel dielectric layer 110 is in the range of approximately 5000 to 1500 angstroms.
  • an interconnect masking layer 120 is fabricated on an upper surface 111 of interlevel dielectric layer 1 10.
  • Interconnect masking layer 120 includes an interconnect masking material 122 and an interconnect mask opening 124.
  • Interconnect mask opening 124 is bounded by first and second interconnect mask opening sidewalls 124a and 124b respectively.
  • Interconnect masking layer 120 is aligned over contact region 1 12 of interlevel dielectric layer 1 10.
  • first sidewall 124a of interconnect mask opening 124 is laterally aligned with first contact region boundary 1 12a and second interconnect mask opening sidewall 124b is laterally aligned with second contact boundary 112b.
  • a preferred method of forming contact masking layer 120 includes depositing silicon nitride on upper surface 111 of interlevel dielectric layer 110 and thereafter patterning the silicon nitride layer with a conventional photolithography/etch process sequence.
  • the preferred process for depositing sihcon nitride on interlevel dielectric layer 110 includes decomposing silane and NH 3 in a chemical vapor deposition reactor chamber maintained at a temperature in the range of approximately 600°C to 900°C at a pressure of less than approximately two torrs.
  • the removal of portions of the silicon nitride layer is accomplished with an 85% phosphoric acid solution maintained at a temperature of approximately 100°C.
  • a thickness of contact masking layer 120 is in the range of approximately 100 to 500 angstroms. This relatively thin masking layer can be adequately covered by a subsequent photoreist as will be described below.
  • contact masking layer 120 is patterned in the processing sequence shown in Fig. 3. it is noted that the contact etch is not executed at this point in the presently preferred process. Instead, the contact etch will be performed at a subsequent point in the process and, ideally, may be combined with the etch process required to form an interconnect trench that will define the second interconnect level.
  • an interconnect masking layer material 130 is deposited over contact masking layer 120 and interlevel dielectric layer 1 10.
  • Interconnect masking layer material 130 in a presently preferred embodiment, is formed by spin depositing photoresist over contact masking layer 120.
  • the specific compositions of contact masking layer 120 and interconnect masking layer material 130 is not typically critical. It is important, however, that a process exists for selectively removing contact masking layer 120 without selectively removing interconnect masking layer material 130. This restriction requires that contact masking layer 120 and interconnect masking layer material 130 be of dissimilar material. In addition, it must be possible in the present invention to selectively remove portions of interlevel dielectric layer 110 without removing significant portions of contact masking layer 120 or interconnect masking layer material 130.
  • first interconnect level 108 is not shown in each of the figures. The absence of first interconnect level 108 occurs only in those figures in which the presence of first interconnect level 108 in the figure is not required for an understanding of the process being described with respect to the particular figure and may unduly complicate the diagram. It is to be understood, however, that first interconnect level 108 is, nevertheless, included within semiconductor substrate 102 in all of the figures.
  • interconnect masking layer 132 is fabricated from interconnect masking layer material 130.
  • interconnect masking layer material 130 comprises photoresist
  • the formation of interconnect masking layer 132 is accomplished with a photolithographic exposure/develop cycle as is well known in the field of photolithography.
  • Interconnect masking layer 132 includes interconnect mask opening 136 is defined by first and second interconnect mask opening sidewalls 136a and 136b
  • Interconnect masking layer 132 is aligned over interconnect region 114 of interlevel dielectric layer 1 10 h a manner similar to the alignment of contact masking layer 120 to contact region 112.
  • interconnect masking layer 132 the alignment of interconnect masking layer 132 to interconnect region 114 requires that first interconnect mask opening sidewall 136a is laterally aligned over first interconnect region boundary 114a of ⁇ interconnect region 114 and second interconnect mask opening sidewall 136b is laterally aligned over second interconnect region boundary 114b. It will be appreciated that the formation of interconnect masking layer 132 does not substantially alter interlevel dielectric 1 10 or contact masking layer 120. It is appreciated, therefore, that, as shown in Fig. 5, the present invention contemplates the simultaneous presence upon interlevel dielectric level 110 of contact masking layer 120 and an interconnect masking layer 132.
  • an etch process may be initiated to fabricate an opening to first interconnect level 108.
  • an etch process may be initiated to fabricate an opening to first interconnect level 108.
  • dual masking layers over interlevel dielectric layer 110.
  • one embodiment of the present invention contemplates combining the etch process used to fabricate a contact tunnel with the etch process used to fabricate a second interconnect level trench. It is noted that the formation of interconnect masking layer 132 results in the exposure of exposed portions 138 of contact masking layer 120.
  • first displacement d b in a presently preferred embodiment, is less than a thickness t iw of interlevel dielectric layer 110.
  • the thickness t iId of interlevel dielectric layer 110 is approximately equal to first displacement d, and a second displacement d 2 where the second displacement d 2 is approximately equal to a thickness of an interconnect trench used for the formation of a second interconnect level as shown and described below with respect to Fig. 8.
  • a preferred process of forming contact tunnel 140 comprises anisotropically etching interlevel dielectric layer 110 in a reactive ion etcher using a fluorine bearing plasma as is well known in the field of semiconductor processing.
  • the presence of contact masking layer 120 during the formation of contact 140 prevents significant removal of interlevel dielectric layer 110 from regions exterior to contact region 112.
  • exposed portions 138 of contact masking layer 120 are removed so that upper surface 1 15 of interconnect region 114 is exposed.
  • contact masking layer 120 comprises a silicon nitride material
  • the removal of exposed portions 138 of contact masking layer 120 may be accomplished with a heated phosphoric solution as is well known.
  • the process steps shown in Figs. 6 - 8 may be accomplished in a single etch apparatus using a single pump down cycle.
  • a three stage etch process would be executed.
  • contact tunnel 140 would be formed.
  • exposed portions 138 of contact masking layer 120 would be removed while, during the third stage, an interconnect trench 150 (show an described in Fig. 8) would be formed.
  • the removal of exposed portions 138 of contact masking layer 120 could be suitably achieved with a conventional, dry, silicon nitride etch process.
  • Combining the process steps required to form contact tunnel 140. removed exposed portions 138 of contact masking layer 120. and form interconnect trench 150 advantageously reduces the amount of handling to which semiconductor substrate 102 is subjected.
  • interconnect trench 150 is formed by selectively removing portions of interlevel dielectric layer 110 within interconnect region 114.
  • the etch process used to form interconnect trench 150 is substantially similar to the etch process used to form contact tunnel 140.
  • the formation of interconnect 150 comprises an anisotropic oxide etch process.
  • performing an anisotropic etch process on the topography of interlevel dielectric layer 110 shown in Fig. 7 will result in an effective vertical translation of contact tunnel 140 wherein the amount of translation is approximately equal to the second depth d 2 of interconnect trench 150.
  • interconnect/contact opening 152 is fabricated within interlevel dielectric layer 110. Interconnect/contact opening 152 extends from an upper surface 111 of interlevel dielectric layer 110 to an upper surface 101 of semiconductor substrate 102. In an embodiment of semiconductor substrate 102 in which a first interconnect level 108 occupies upper region 106 of semiconductor substrate 102 including upper surface 101 of semiconductor substrate 102. then it will be appreciated that interconnect/contact opening 152 extends to first interconnect level 108.
  • Interconnect/contact opening 152 includes an interconnect trench 150 and a contact tunnel 140.
  • Contact tunnel 140 communicates between first interconnect level 108 within semiconductor substrate 102 and a lower surface 150c of interconnect trench 150.
  • a width of interconnect trench 150 is greater than the width of contact tunnel 140 and sidewalls 140a and 140b of contact tunnel 140 are laterally displaced between sidewalls 150a and 150b of interconnect trench 150.
  • interconnect/contact opening 152 is filled with a conductive material to form a contact/interconnect structure 160.
  • contact structure 160 includes an adhesion layer 160a and an interior layer 160b.
  • adhesion layer 160 may be desired in certain applications to improve the adhesion of contact/interconnect structure 160 to interlevel dielectric layer 1 10.
  • a filling of interconnect/contact opening 152 is initiated by blanket depositing an adhesion material onto the sidewalls of interconnect/contact opening 152.
  • Suitable adhesion materials include titanium (Ti), titanium-tungsten (Ti:W), titanium nitride (Ti:N), or tungsten suicides (WSi x ). Adhesion layers are typically required in those cases where the material used for central portion 160b of contact/interconnect structure 160 adhere poorly to the material of interlevel dielectric layer 1 10.
  • Adhesion layers are typically required, for example, to compensate for the poor adhesion characteristics of tungsten and some tungsten alloys to silicon/oxide dielectric films.
  • a core material 160 is then deposited on adhesion layer 160.
  • the interconnect portion of contact/interconnect structure 160 is defined by interconnect trench 150.
  • a mechanical planarization process such as a chemical mechanical polish is required to remove portions of the deposited film from regions exterior to interconnect trench 150.
  • the use of a damascene process to form an interconnect is desirable because the interconnect sidewalls are defined by an oxide etch process.
  • an upper surface 161 of the interconnect structure is substantially planar with an upper surface 111 of interlevel dielectric 110.
  • the inherently planar topography produced by damascene processes faciUtates subsequent interconnect processing because no additional planarization is typically required.
  • a subsequent interconnect level may be fabricated by essentially repeating the processing sequence shown in Figs. 2 through 9. In this manner, multiple levels of interconnect may be fabricated upon a semiconductor substrate.
  • adhesion layer 160a an alternative embodiment may eliminate the need for a separate adhesion layer.
  • the formation of contact interconnect structure 160 is accomplished with a single deposition step in which a conductive material such as aluminum, copper, tungsten, titanium, or appropriate alloys thereof are deposited into interconnect/contact opening 152 and thereafter planarized as described above.
  • adhesion layer 160a may be suitably eliminated in conjunction with a CVD aluminum process.
  • a CVD aluminum process is desirable because (1) the resistivity of CVD aluminum is typically significantly lower than the resistivity of other CVD metals such as tungsten, (2) CVD aluminum exhibits excellent adhesion to silicon and typical dielectric materials such as CVD oxide, and (3) excellent conformal coverage of the underlying structure can be achieved with CVD alurninum processes.
  • aluminum is chemically vapor deposited by the pyrolisis of triisobutyl aluminum (TIBA) in a reactor chamber maintained at a temperature of approximately 250°C and a pressure less than approximately 1 torr.

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Abstract

La présente invention concerne un procédé de semi-conducteurs incluant un premier niveau d'interconnexion (108) dans un substrat de semi-conducteur (104). Une couche diélectrique interniveau (110) est formée sur le substrat semi-conducteur et une couche masquant les contacts (122) est formée sur le diélectrique interniveau (110). Un motif de couche masquant les contacts (122) est aligné au-dessus d'une région de contacts (112) du diélectrique interniveau (110). Une couche masquant l'interconnexion (130) est alors formée sur la couche masquant les contacts (122). Un motif de la couche masquant l'interconnexion (130) est alors aligné au-dessus d'une région d'interconnexion (136) de la couche diélectrique interniveau (110). Des portions de la région d'interconnexion (136) sont alors enlevées pour former un tunnel de contacts (140). Des portions de la région d'interconnexion (136) sont alors sélectivement enlevées pour former une tranchée d'interconnexion (150). Le tunnel de contacts (140) et la tranchée d'interconnexion (150) sont alors comblées avec un matériau conducteur (160). Dans la réalisation préférée, la couche masquant les contacts (122) comprend une couche de nitrure de silicium. La couche masquant l'interconnexion (130) est de préférence une couche de photorésiste comportant un motif formée sur la couche masquant les contacts (122). La formation de la couche masquant l'interconnexion (130) précède de préférence l'opération d'enlèvement sélectif des portions de la région de contacts (112) de façon que la couche masquant l'interconnexion (130) et la couche masquant les contacts (122) sont simultanément présentes au-dessus de la couche diélectrique interniveau (110), avant la formation des tunnels de contacts (140). Dans une réalisation, le comblement du tunnel de contacts, et le comblement de la tranchée d'interconnexion sont accomplis simultanément. De façon idéale, l'enlèvement sélectif des portions de la région d'interconnexion translate verticalement le tunnel de contacts dans les limites du diélectrique interniveau de façon que le tunnel de contacts aboutit jusqu'à une surface supérieure du premier niveau d'interconnexion.
EP98915322A 1997-06-26 1998-04-07 Procede de gravure a double damasquinage Withdrawn EP0995228A1 (fr)

Applications Claiming Priority (3)

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US883197 1986-07-08
US88319797A 1997-06-26 1997-06-26
PCT/US1998/006828 WO1999000839A1 (fr) 1997-06-26 1998-04-07 Procede de gravure a double damasquinage

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CN102610563A (zh) * 2012-04-06 2012-07-25 上海集成电路研发中心有限公司 制备铜双大马士革结构的方法

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FR2663784B1 (fr) * 1990-06-26 1997-01-31 Commissariat Energie Atomique Procede de realisation d'un etage d'un circuit integre.
US5091339A (en) * 1990-07-23 1992-02-25 Microelectronics And Computer Technology Corporation Trenching techniques for forming vias and channels in multilayer electrical interconnects
JPH053258A (ja) * 1990-09-25 1993-01-08 Kawasaki Steel Corp 層間絶縁膜の形成方法
US5635423A (en) * 1994-10-11 1997-06-03 Advanced Micro Devices, Inc. Simplified dual damascene process for multi-level metallization and interconnection structure

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