EP1002320B1 - Blockdekodierter wortleitungstreiber mit positiver und negativer spannungsbetriebsart unter verwendung von mos-transistoren mit vier anschlüssen - Google Patents

Blockdekodierter wortleitungstreiber mit positiver und negativer spannungsbetriebsart unter verwendung von mos-transistoren mit vier anschlüssen Download PDF

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Publication number
EP1002320B1
EP1002320B1 EP98926353A EP98926353A EP1002320B1 EP 1002320 B1 EP1002320 B1 EP 1002320B1 EP 98926353 A EP98926353 A EP 98926353A EP 98926353 A EP98926353 A EP 98926353A EP 1002320 B1 EP1002320 B1 EP 1002320B1
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European Patent Office
Prior art keywords
coupled
supply voltage
drivers
negative
wordline
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French (fr)
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EP1002320A4 (de
EP1002320A1 (de
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Tzeng-Huei Shiau
Yu-Shen Lin
Ray-Lin Wan
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Macronix International Co Ltd
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Macronix International Co Ltd
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/08—Word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, for word lines
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits

Definitions

  • the present invention relates to wordline drivers used in memory arrays which are capable of driving both positive and negative voltages on the wordlines; and more particularly to floating gate memory devices which apply a negative voltage to wordlines during an erase mode, and a positive voltage to individual wordlines during a read mode and a program mode.
  • nonvolatile semiconductor memory devices based on floating gate memory cells, such as those known as flash EEPROM
  • positive and negative voltages are used to read and write data into the nonvolatile memory array.
  • the writing of data into the nonvolatile memory array for floating gate devices involves processes known as the program and erase modes.
  • the erase mode involves setting an entire array, or at least a sector of an array, to a single state, in which either all of the cells in the array (or sector) have a low threshold or all of the cells in the array (or sector) have a high threshold. Whether the erased state is a high threshold state, in which the floating gate of the cell is charged or a low threshold state in which the floating gate is discharged, depends on the particular implementation of the flash memory.
  • the programming mode involves charging or discharging the floating gate of individually addressed cells in the array to establish the opposite threshold level with respect to the erased state.
  • Wordline drivers must be capable of driving a positive voltage during a normal read mode for the device to selected wordlines in response to decoded addresses. It has proved difficult in the prior art to provide a wordline driver with the simple circuitry that can also apply a negative voltage to selected the wordlines. Prior systems for applying negative voltages to the wordlines have overridden the decoding function which drives the wordline driver, making it impossible to selectively apply negative voltages to individual wordlines. See, for instance, European Patent Application No. 92112727.0 entitled NON-VOLATILE SEMI-CONDUCTOR MEMORY DEVICE HAVING ROW DECODER, invented by Atsumi, et al. (Publication No. 0 525 678 A2); and European Patent Application No.
  • WO 96/23307 discloses a Flash EEPROM array comprising memory cells arranged in blocks.
  • Wordlines are coupled to memory cells in the array.
  • a wordline driver includes a driver circuit and selector circuitry which is coupled to voltage sources. A number of such driver circuits are provided, each coupled to a wordline.
  • the driver circuits drive associated wordlines with a voltage provided by the selector circuitry.
  • the selector circuit supplies a predetermined voltage to all drivers, dependent on the particular operating mode. In the erase mode, V POS and ground is supplied to all driver circuits.
  • the driver circuits then select the appropriate voltage to be applied to the wordlines based on signals received from a decoder. To enable the driver circuits to apply a negative voltage, isolation circuitry is provided to isolate the decoder from those negative voltages.
  • Embodiments of the present invention provide a compact wordline driver and decoder system in which the negative supply voltage used by the wordline drivers during sector or chip level erase operations is decoded separately from the decoding of inputs to the individual wordline drivers.
  • the wordline drivers include triple well transistors which are required for implementation of high negative voltage circuits on an integrated circuit of this nature.
  • the triple well transistors of a plurality of wordline drivers are formed in a shared well, biased independently of the source and drain of the transistors. Accordingly, using the wordline driver of the present invention, an integrated circuit memory is provided with compact array layout and therefore reduced cost.
  • embodiments of the present invention can be characterised as an integrated circuit memory comprising an array of memory cells arranged in a plurality of segments.
  • a set of wordlines is coupled to the memory cells in the array.
  • Wordline driver circuitry is coupled to the set of wordlines.
  • the wordline driver circuitry includes a first supply voltage source, a second supply voltage source, a third supply voltage source, and a set of wordline drivers.
  • the wordline drivers are coupled to the first, second and third supply voltage sources, and selectively drive wordlines in the set of wordlines with a wordline voltage from either the first supply voltage source or the second supply voltage source in response to address signals which identify the respective drivers.
  • the individual drivers are connected to sets including one or more wordlines.
  • the second supply voltage source includes a set of second supply voltage selectors.
  • Each second supply voltage selector in the set is coupled with a subset of the set of drivers.
  • Each subset of drivers is coupled with a respective segment in the array.
  • the second supply voltage selectors select a negative erase supply voltage or an erase inhibit supply voltage during an erase mode in response to address signals identifying the respective segments.
  • the selected negative erase supply voltage or erase inhibit supply voltage is applied to the subsets of the set of drivers which are coupled to the respective segment on a segment by segment basis.
  • the subset of drivers include a shared well for triple well transistors in the respective drivers. This enables erase operations with a compact wordline driver design at a segment level, where a segment is a block or sector of the array that is coupled to more than one wordline driver, such as 16 wordline drivers.
  • the third supply voltage source includes a set of third supply voltage selectors. Each third supply voltage selector in the set is coupled with one or more of the subsets of the set of drivers. The third supply voltage selectors select a negative bias voltage for the shared well of a subset of drivers during an erase mode in response to address signals identifying the respective segments.
  • the wordline circuitry includes logic that causes the drivers to select the second supply voltage source during the erase mode for all wordlines in the set of wordlines.
  • Such logic in one embodiment overrides the address signals identifying the respective drivers during the erase mode, in the logic which supplies the inputs to the drivers.
  • the wordline drivers each comprise an inverter having an input driven in response to address signals identifying the corresponding driver, a first supply terminal coupled to the first supply voltage source, a second supply terminal coupled to the second supply voltage source, a third supply terminal coupled to the third supply voltage source, and an output coupled to one or more wordlines in the set of wordlines.
  • a feedback circuit is included that is coupled between the output and the input of the inverter.
  • the inverter comprises a p-channel MOS transistor in series with a four-terminal triple well n-channel MOS transistor.
  • the n-channel MOS transistors in the inverters in subsets of the plurality of wordline drivers are placed in shared p-wells.
  • the source of each n-channel MOS transistor is coupled to the second supply voltage source, and supports transferring of the high negative voltage to the wordline.
  • the shared p-well of each n-channel MOS transistor is coupled to the third supply voltage source, which acts to maintain the p-well in a reverse-biased state with respect to the source of the n-channel MOS transistor for the subset.
  • the third supply voltage source acts to maintain the shared p-well in a reverse biased state with respect to the sources of all of the n-channel MOS transistors sharing the p-well .
  • the source of the p-channel MOS transistor is coupled to the first supply voltage source, and supports applying positive voltages to the wordline during the read and program modes.
  • the feedback circuit comprises a p-channel MOS transistor having its source coupled to the first supply terminal, its gate coupled to the output of the driver, and its drain coupled to the input of the driver.
  • Another embodiment of the invention comprises a flash memory device comprising an array of floating gate memory cells.
  • Control logic on the device establishes a read mode, a program mode and an erase mode.
  • Wordline driver circuitry as described above is included on the device.
  • the wordline driver circuitry includes segment decoder logic that is coupled to the drivers in the set of drivers.
  • the segment decoder logic causes the inputs of the drivers to be set in response to address signals identifying the drivers during the read mode so that they supply a read supply voltage to addressed wordlines.
  • the decoder logic causes the inputs to the drivers to be supplied independent of the address signals, and the second supply voltage selectors select a negative erase supply voltage or the erase inhibit voltage in response to address signals identifying the respective segments.
  • the negative erase supply voltage has a value in the range of -5 to -10 volts such as about -8 volts, while the erase inhibit supply voltage has a value in the range of +3 volts to -3 volts, and preferably about ground potential.
  • the cells in the array are otherwise biased in this condition to induce Fowler Nordheim tumneling in the floating gate memory cells in the segment being erased.
  • the embodiments of present invention can be characterized as a wordline driver in a set of wordline drivers.
  • the wordline driver according to this aspect comprises a first supply voltage source, a second supply voltage source and a third supply voltage source.
  • the second and third supply voltage sources each include a supply voltage selector which selects a negative voltage or an inhibit supply voltage as a supply voltage in response to a supply select signal.
  • Decode logic responsive to address signals identifying the driver and a mode signal, operates to supply a decode logic output in response to the address signals when the mode signal is in a first state, and without response to the address signals when the mode signal is in a second state.
  • Supply select logic is responsive to address signals identifying a plurality of wordline drivers in the set of wordlines, such as a plurality of wordline drivers corresponding to a segment of the memory to be erased.
  • the supply select logic supplies the supply select signal without response to the address signals when the mode signal is in a first state, and in response to the address signals when the mode signal is in the second state.
  • the driver further includes an inverter having an input coupled to the decode logic output, a first supply terminal coupled to the first supply voltage source, a second supply terminal coupled to the second supply voltage source to receive the second supply voltage, a third supply terminal coupled to the third supply voltage source to receive the third supply voltage, and an output coupled to a wordline.
  • a feedback circuit is coupled between the output and the input of the inverter. In preferred aspects, the inverter and feedback circuit are implemented as discussed above.
  • embodiments of the present invention provide a set of wordline drivers for a memory organized into a plurality of segments and including 4 terminal, triple well n-channel MOS transistors.
  • the wordline drivers in a given segment share the same second supply voltage source which is capable of applying a negative voltage.
  • each segment has its own second supply voltage source.
  • the wordline drivers within one segment experience either a negative voltage on the second supply terminal or an inhibit voltage such as ground on the second supply terminal.
  • a simplified wordline driver and compact overall array architecture are achieved.
  • embodiments of the present invention provide a compact decoded wordline driver which can be used in a flash memory device for providing positive and negative decode modes.
  • This system is small, operates with great efficiency, and eliminates complex circuitry of prior art systems.
  • a flash device which includes a floating gate transistor array 100 having a plurality of sectors capable of independently being erased, which might be implemented as shown in Fig. 2. Coupled to the array is a decoder 101, which has positive and block decoded negative voltage wordline drivers using 4 terminal, triple well mechanical transistors with shared p-wells.
  • a mode control circuit 106 is coupled to the negative voltage generator 108, positive voltage generator 109, and column and virtual ground decoders 105 to provide a read RD, a program PGM, and an erase ERS mode for the Flash device.
  • a negative voltage generator 108 and a positive voltage generator 109 are also coupled with the decoder.
  • Column and virtual ground decoders 105 are coupled to the bitlines in the array as shown, and to the negative voltage generator 108 and positive voltage generator 109. Finally, sense amps 107 and program data-in structures 103 are coupled to the column and virtual ground decoders 105 for use in programming and reading the array.
  • Fig. 2 illustrates one embodiment of a flash memory array which might be used with the system of Fig. 1.
  • Fig. 2 shows two pairs of columns of the array, where each pair of columns includes flash cells in a drain-source-drain configuration.
  • the first pair 120 of columns includes a first drain diffusion line 121, a source diffusion line 122, and a second drain diffusion line 123.
  • Wordlines WL0 through WL63 each overlay the floating gates of a cell in a first one of the pairs of columns and a cell in the second one of the pairs of columns.
  • a first pair 120 of columns includes one column including cell 124, cell 125, cell 126, and cell 127. Not shown are cells coupled to wordlines WL2 through WL61.
  • the second one of the pair 120 of columns includes cell 128, cell 129, cell 130, and cell 131.
  • a second pair 135 of columns is shown. It has a similar architecture to the pair 120 of columns except that it is laid out in a mirror image.
  • the transistor in the first one of the pair of columns such as the cell 125, includes a drain in drain diffusion line 121, and a source in the source diffusion line 122.
  • a floating gate overlays the channel region between the first drain diffusion line 121 and the source diffusion line 122.
  • the wordline WL1 overlays the floating gate of the cell 125 to establish a flash cell.
  • the column pair 120 and column pair 135 share an array virtual ground diffusion 136 (ARVSS).
  • ARVSS array virtual ground diffusion 136
  • the source diffusion line 122 of column pair 120 is coupled to the ground diffusion 136.
  • the source diffusion line 137 of column pair 135 is coupled to the ground diffusion 136.
  • each pair 120 of columns of cells shares a single metal line.
  • a block right select transistor 138 and a block left select transistor 139 are included.
  • the transistor 139 includes a source in the drain diffusion line 121, a drain coupled to a metal contact 140, and a gate coupled to the control signal BLTR1 on line 141.
  • the right select transistor 138 includes a source in the drain diffusion line 123, a drain coupled to the metal contact 140, and a gate coupled to the control signal BLTR0 on line 142.
  • the select circuitry including transistors 138 and 139, provides for selective connection of the first drain diffusion line 121 and a second drain diffusion line 123 to the metal line 143 (MTBL0) through metal contact 140.
  • column pair 135 includes left select transistor 144 and right select transistor 145 which are similarly connected to a metal contact 146.
  • Contact 146 is coupled to the same metal line 143 as is contact 140 which is coupled to column pair 120.
  • the metal line can be shared by more than two columns of cells with additional select circuitry.
  • the array may be repeated horizontally and vertically as required to establish a large scale flash memory array.
  • column pairs 120 and 150 which share a wordline are repeated horizontally to provide a sector of the array.
  • Fig. 2 is one example of the kinds of non-volatile memory architectures with which the present invention may be used.
  • a variety of other architectures are also suited to segmented erase operations, and would benefit from the present invention.
  • Fig. 3 illustrates a preferred embodiment of the wordline driver according to the present invention.
  • the wordline driver includes a first supply voltage source (such as positive voltage generator 109 of Fig. 1) which is connected to the AVX terminal 300.
  • a second supply voltage source is coupled to terminal 301, which supplies a high voltage driver V SS voltage HVDRVSS.
  • the second supply voltage source includes a supply voltage selector 302 which selects a negative voltage NVPP from terminal 303 or an inhibit supply voltage HVDRGND on terminal 304 as output in response to a supply select signal on line 315.
  • the value of NVPP is about -8 volts, and typically falls within the range of -5 to -10 volts.
  • HVDRGND is preferably about ground potential or 0 volts, and typically falls within the range of about -3 volts to +3 volts.
  • a third supply voltage source is coupled to terminal 318, which supplies a high voltage driver voltage HVDRPWI.
  • a positive supply voltage AVW is applied on line 305 to the selector 302.
  • This positive supply voltage AVW (same as AVX during erase mode, about 3 volts) is controlled as discussed below during operation of the selector 302.
  • the voltage HVDRVSS on line 301 is shared among a plurality of driver circuits 306, as indicated by the arrow 317.
  • the voltage HVDRPWI is also shared among a plurality of driver circuits 306, as indicated by the arrow 320.
  • the core driver circuit 306 includes an inverter composed of transistors MP3 and MT0 having their gates coupled to an input at node 307, and their drains coupled to a wordline or a set of wordlines 308.
  • the driver circuit 306 also includes feedback which is provided by p-channel transistor MP0 which has its gate coupled to the output 308, its drain coupled to the input 307, and its source coupled to the supply terminal 300.
  • the n-wells of the p-channel transistors MP0 and MP3 are both coupled to the AVX supply terminal 300.
  • the n-channel transistor MT0 consists of a triple well transistor implemented as shown in Fig. 4. This structure will be described below.
  • the deep n-well is biased at the supply potential V DD which is typically 5 volts +/-10% and serves to isolate the n-channel transistor from the p-type substrate during negative voltage operations. In some embodiments, the supply voltage V DD is lesser or greater as suits a particular implementation.
  • the p-well is biased at the supply potential HVDRPWI, which is set to maintain the p-well in a reversed-biased state with respect to the source 403.
  • the driver circuit 306 also includes a "keeper" transistor MN2 which consists of a n-channel transistor having its source coupled to the input 307 its drain coupled to the supply terminal V DD , and its input coupled to a control signal XDHB on line 309. This control signal XDHB on line 309 is controlled during negative voltage operations as discussed below.
  • an n-channel transistor MN1 is connected in a pass-gate configuration between the input 307 and further decode logic represented by NAND gate 310.
  • the n-channel transistor MN 1 has its gate coupled to the signal XR on line 312 which is supplied by the wordline decoding logic.
  • the source of transistor MN1 is connected to the output of the NAND gate 310.
  • the inputs to the NAND gate include the signals XP, XBL2, and XBL3 derived from address signals. These signals in combination with the decode signal XR on line 312 serve to identify the particular driver circuit 306.
  • Another input to the NAND gate 310 comprises a mode signal ERASEB which is low during the erase mode. Thus, during the erase mode, the signals derived from the address signals are overridden and the input on line 307 of the wordline circuit 306 is driven to a logic 1 value when XR is high.
  • the input on line 307 is driven in response to address signals identifying a particular driver during the read and program modes.
  • the address signals are overridden during the erase mode and the driver circuit 306 receives a logic 1 value for all wordlines in a set of wordlines coupled to this decoding system.
  • the signal XR is high on all drivers, in this example.
  • the supply select signal on line 315 at the input to supply voltage sector 302 is driven by the NAND gate 311.
  • the inputs to the NAND gate 311 include the signals XBL2 and XBL3 derived from the address signals, and the erase mode signal ERASE.
  • the signal ERASE is high enabling the output of the NAND gate 311 to be controlled by the address signals XBL2 and XBL3 which identify a particular segment of the array.
  • These signals XBL2 and XBL3 are the same signals XBL2 and XBL3 which are applied to the input of NAND gate 310 which drives each of the wordline driver circuits 306 in the segment being selected.
  • the NAND gate 310 is simplified to a 3 input NAND gate, removing the control signal ERASEB as input.
  • the signal XR is controlled in response to ERASEB or its equivalent to disconnect the drivers from the gate 310, while XDHB is driven to a level that applies a logic one to node 307 without driving node 307 to a level exceeding AVX during erase mode.
  • the wordline driver operates during the read and program mode to apply a positive voltage from the supply AVX, or ground as a result of the specific wordline circuit 306 being activated by the wordline decoding system.
  • a negative voltage or ground is applied to the wordline through the triple well n-channel transistor MT0.
  • the operation conditions of the wordline driver circuit 306 are shown in Table 1 which follows: Operation Mode XDHB HVDRVSS AVX HVDRPWI READ VDD 0v Vcc 0v Programming VDD 0v 12v 0v Programming Inhibit of Row VDD 0v 12v 0v Erase of blocks VDD ⁇ 0v -8v 3v -8v Erase Inhibit of blocks VDD ⁇ 0v 0v 3v -8v
  • U.S. Patent No. 5,463,586 describes a suitable supply voltage selector for the positive voltage AVX. A wide variety of implementations of such supply voltage selector are suitable for utilization according to the present invention.
  • control signal XDHB is switched from V DD to 0 volts in order to break the connection between the terminal AVX on line 300 and the supply voltage V DD .
  • XDHB is driven to a level that prevents node 307 from exceeding AVX, as mentioned above.
  • wordline driver circuits 306 which have the same XBL2 and XBL3 but have different XP and XR share the same supply voltage selector 302. As a result, the wordline drivers in a segment of the floating gate memory array are switched to the negative voltage together.
  • FIG. 4 A description of the triple well n-channel MOS transistor MT0 is illustrated in Fig. 4.
  • the supply voltage selector 302 in a preferred embodiment is illustrated in Fig. 5, and the modified wordline decoding system according to the present invention is illustrated in Fig. 6.
  • a triple well n-channel transistor such as MT0 is illustrated in Fig. 4.
  • the transistor is composed of a gate terminal 400 over a channel region 401 which is formed between n-type diffusion regions 402 and 403 operating as the drain and source, respectively, of the transistor.
  • the n-type diffusion regions 402 and 403 are implemented in the isolated p-type well 404.
  • the p-type well has a contact at point 405 which is connected to the HVDRPWI value on line 318.
  • the p-type well 404 is shared among a plurality of transistors.
  • the shared p-type well 404 is, in turn, formed in an n-type well 406, which has contact 407 to a positive supply voltage V DD .
  • the n-type well 406 is, in turn, formed in a p-type substrate 408.
  • the structure establishes a p-n junction, schematically represented by the diode symbol 409 between the p-well 404 and the n-well 406. When negative voltages are applied to the p-well 404, this junction is reversed biased, isolating the n-well from the negative voltage.
  • a p-n junction represented by the diode symbol 410 is formed between the p-type substrate and the n-well 406. By biasing the n-well 406 with a positive voltage, this junction 410 is reversed biased, isolating the entire structure from the substrate.
  • Fig. 5 illustrates the supply voltage selector 302 of Fig. 3 in one preferred embodiment. Similar circuitry can be used for selector 319.
  • the supply voltage selector receives a supply input AVW on line 500, and selector signal ENB on line 501, a negative voltage NVPP on line 502, and a ground voltage HVDRGND on line 503.
  • the circuit operates to select between the negative voltage 502 and the ground voltage 503 for supply on an output 504 which corresponds to the signal HVDRVSS on line 301 of Fig. 3.
  • the supply selector includes p-channel MOS transistor MP 1 which has its source and n-well coupled to the supply terminal 500, its gate coupled to line 501, and its drain coupled to node 510.
  • P-channel MOS transistor MP2 has its source and n-well coupled to node 500, its gate connected to the output of an inverter 511 which has its input connected to node 501.
  • the drain of transistor MP2 is connected to node 512.
  • a triple well n-channel MOS transistor MT3 has its gate connected to node 512, its drain connected to node 510, its source and p-well connected to terminal 502 at which the negative voltage is applied.
  • the deep n-well is coupled to the supply terminal V DD .
  • Triple well transistor MT4 has its drain coupled to node 512, its gate coupled to node 510, and its source coupled to node 502. Also, the p-well of transistor MT4 is also coupled to node 502.
  • the deep n-well of transistor MT4 is coupled to the supply terminal V DD .
  • Node 512 is coupled to the source of triple well transistor MT1 which has its gate coupled on line 513 to a ground potential and its drain coupled to the output node 504.
  • the p-well of triple well transistor MT1 is coupled to node 502, while the deep n-well is coupled to the supply terminal V DD .
  • Triple well transistor MT2 has its gate coupled to node 512, its source coupled to the ground terminal 503, its p-well coupled to node 502, and its deep n-well coupled to the positive supply terminal V DD .
  • the drain of transistor MT2 is coupled to the output node 504.
  • node 512 is driven to the negative voltage NVPP via transistor MT4.
  • This negative voltage typically -8 volts, is thus applied to node 504 through transistor MT1 and transistor MT2 is turned off.
  • Transistor MT2 serves to isolate the negative voltage at node 504 from the ground potential on node 503.
  • the node 512 When the input signal ENB on line 501 is driven to the supply voltage V DD , the node 512 is driven to the AVW value (typically 3 volts). The AVW value turns on transistor MT2, and causes transistor MT1 to turn off. This supplies the ground potential at line 503 to the output on node 504, while isolating the node 504 from the voltage at node 512.
  • the AVW value typically 3 volts.
  • Fig. 6 illustrates the wordline decoding system including the supply voltage selector of the present invention.
  • the wordline decoding system of Fig. 6 corresponds to the decoding system for a segment of the array which drives 16 wordlines including wordlines WLLO - WLL7 on the left and wordlines WLRO - WLR7 on the right.
  • Each of the wordlines is driven by a wordline driver circuit 306 as described in Fig. 3.
  • the inputs to the wordline driver circuits 306 include the values AVX, XDHB.
  • each of the drivers 306 receives an input from the decoding system labeled in the system XRL0 - XRL7 on the left, and XRR0 - XRR7 on the right.
  • the input to each of the wordline circuits is supplied at the output of the NAND gate 310, which corresponds to the NAND gate of Fig. 3.
  • the wordline circuits also receive the HVDRVSS signal the output of the wordline selector 302.
  • the XP signal is one of four XP signals (XP10 - XP13) generated in response to the address signals.
  • the XBL2 signal is one of four (XBK20 - XBL23), and the XBL3 signals is one of eight (XBL30 - XBL37).
  • the XBL2 signal and XBL3 signal supplied at the input of NAND gate 311 are the same as those applied to the input of NAND gate 310 for a single segment of the array.
  • an efficient compact wordline driver circuitry supporting a segment erase operation for floating gate memory devices such as flash memory has been provided.
  • the circuit reduces the layout and complexity required for negative voltage decoding, and overall reduces the cost of integrated circuits implementing this feature.

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Claims (17)

  1. Wortleitungstreiberschaltkreis für eine Anordnung (Array) (100) von Speicherzellen (124-131), die in einer Mehrzahl von Segmenten (120, 135, 150, 151) angeordnet sind, wobei ein Satz von Wortleitungen (WLO-63, WLO'-63') mit den Speicherzellen in dem Array verbunden ist und wobei der Wortleitungstreiberschaltkreis mit dem Satz von Wortleitungen verbunden ist, wobei der Wortleitungstreiberschaltkreis aufweist:
    Eine erste Versorgungsspannungsquelle (109), eine zweite Versorgungsspannungsquelle (108), eine dritte Versorgungsspannungsquelle und einen Satz von Wortleitungstreibem (306), der mit den ersten, zweiten und dritten Versorgungsspannungsquellen verbunden ist, wobei die Treiber in dem Satz von Treibern in der Weise betreibbar sind, daß sie wahlweise Wortleitungen in dem Satz von Wortleitungen mit einer Wortleitungsspannung (AVX; HVDRVSS) aus der ersten Versorgungsspannungsquelle oder der zweiten Versorgungsspannungsquelle treibt, und zwar in Reaktion auf Adresssignale, welche die jeweiligen Treiber identifizieren, wobei die Treiber in dem Satz von Treibern im MOS-Transistoren (MTO) mit Dreifach-Wells (mit Dreifach-Gruben) in einem oder mehreren Isolations-Wells (Isolationsgruben) hat, welche mit der dritten Versorgungsspannungsquelle verbunden sind,
    wobei die zweite Versorgungsspannungsquelle einen Satz von Versorgungsspannungsauswählem (302) umfaßt, die mit Teilsätzen einschließlich eines oder mehrerer Treiber des Satzes von Treibern für entsprechende Segmente des Arrays verbunden sind, und wobei
    die dritte Versorgungsspannungsquelle in der Weise betreibbar ist, daß sie eine Vorspannung (HVDRPWI) an dem Isolations-Well für eine Mehrzahl von Teilsätzen anlegt, um jeden Kanal der MOS-Transistoren mit Dreifach-Well von jeder Source zu isolieren,
    dadurch gekennzeichnet, daß
    die Isolafions-Wells geteilte bzw. gemeinsam verwendete Isolations-Wells sind und daß der Satz von Versorgungsspannungsauswählem in Reaktion auf Adressignale, welche die jeweiligen Segmente des Arrays identifizieren, in der Weise betreibbar ist, daß er eine negative Löschversorgungsspannung (NVPP) oder eine Löschverhinderungsversorgungsspannung (HVDRGND) auswählt, die an den jeweiligen Teilsätzen des Satzes von Treibern während eines Löschbetriebs anzulegen sind.
  2. Wortleitungstreiberschaltkreis nach Anspruch 1, wobei die zweite Versorgungsspannungsquelle einen Versorgungsspannungsauswähler aufweist, welcher die negative Spannung oder die verhindernde Versorgungsspannung als die zweite Versorgungsspannung in Reaktion auf das Versorgungsauswahlsignal auswählt, wobei die dritte Versorgungsspannungsquelle einen Versorgungsspannungsauswähler enthält, welcher eine negative Vorspannung, die gleich oder niedriger ist als die zweite Versorgungsspannung, als eine dritte Versorgungsspannung auswählt, wobei der Wortleitungstreiberschaltkreis weiterhin aufweist:
    Eine Decodierlogik, die auf die Adressignale reagiert, welche den Treiber und ein Betriebsartsignal kennzeichnen, um einen Decodierlogikausgangswert in Reaktion auf die Adressignale zu liefern, wenn das Betriebsartsignal sich in einem ersten Zustand befindet, und nicht auf die Adressignale zu reagieren, wenn sich das Betriebsartsignal in einem zweiten Zustand befindet,
    eine Versorgungsauswahllogik, welche auf Adressignale reagiert, die eine Mehrzahl von Wortleitungstreibem in dem Satz von Wortleitungstreibem identifizieren, um das Versorgungsauswahlsignal ohne Reaktion auf die Adressignale zuzuführen, wenn das Betriebsartsignal sich in dem ersten Zustand befindet, und das Versorgungsauswahlsignal in Reaktion auf die Adressignale zuzuführen, wenn das Betriebsartsignal sich in dem zweiten Zustand befindet, wobei die Treiber in dem Satz von Treibern aufweisen:
    Einen Invertierer (MP3, MT0), mit einem Eingang, welcher mit dem Ausgang der Decodierlogik verbunden ist, einem ersten Versorgungsanschluß, der mit der ersten Versorgungsspannungsquelle verbunden ist, einem zweiten Versorgungsanschluß, der mit der zweiten Versorgungsspannungsquelle verbunden ist, um die zweite Versorgungsspannung zu empfangen, einen dritten Versorgungsspannungsanschluß, der mit der dritten Versorgungsspannungsquelle verbunden ist, und einen mit einer Wortleitung verbundenen Ausgang, und
    einen Rückkopplungsschaltkreis (MP0), der zwischen den Ausgang und den Eingang des Invertierers geschaltet ist.
  3. Wortleitungstreiberschaltkreis nach Anspruch 2, wobei der Invertierer einen P-Kanal-MOS-Transistor (MP3) in einem Substrat aufweist, welcher eine Source hat, die mit dem ersten Versorgungsanschluß verbunden ist, ein Gate, welches mit dem Eingang und eine Drain, welche mit dem Ausgang des Treibers verbunden ist,
    einen n-Kanal-MOS-Transistor (MT0) in dem Substrat, welcher eine Source hat, die mit dem zweiten Versorgungsanschluß verbunden ist, ein Gate hat, welches mit dem Eingang und eine Drain hat, welche mit dem Ausgang des Treibers verbunden ist, und einen p-Well hat, der mit dem dritten Versorgungsanschluß verbunden und in einem tiefen Well vom n-Typ eingesetzt ist, der zum Isolieren des p-Wells von dem Substrat vorgespannt ist.
  4. Wordeitungstreiberschaftkreis nach Anspruch 3, wobei der Rückkopplungsschaltkreis aufweist:
    Einen p-Kanal-MOS-Transistor (MP0) in einem Substrat, welcher eine Source hat, die mit dem ersten Versorgungsanschluß verbunden ist, ein Gate hat, welches mit dem Ausgang und eine Drain hat, welche mit dem Eingang des Treibers verbunden ist.
  5. Wortleitungstreiberschaltkreis nach Anspruch 2, wobei die negative Spannung einen Wert in dem Bereich von minus 5 bis minus 10 Volt hat.
  6. Wortleitungstreiberschaltkreis nach Anspruch 2, wobei die negative Spannung einen Wert in dem Bereich von minus 5 bis minus 10 Volt hat und die Verhinderungsspannung einen Wert in dem Bereich von minus 3 bis plus 3 Volt hat.
  7. Integrierter Schaltkreisspeicher, welcher aufweist:
    Ein Array (100) aus Speicherzellen (124-131), die in einer Mehrzahl von Segmenten (120, 135, 150, 151) angeordnet sind,
    einen Satz von Wortleitungen (WLO-63, WLO'-63'), die mit Speicherzellen in dem Array verbunden ist, und
    den Wortleitungstreiberschaltkreis nach Anspruch 1.
  8. Integrierter Schaltkreisspeicher nach Anspruch 7, wobei das Array ein Array aus Speicherzellen mit potentialfreiem Gate (Floating Gate) aufweist, wobei der Integrierte Schaltkreis weiterhin aufweist:
    Eine Steuerlogik (106), die mit dem Array verbunden ist und die so betreibbar ist, daß sie einen Lesebetrieb, einen Programmierbetrieb und einen Löschbetrieb bereitstellt, und wobei
    der Wortleitungstreiberschaltkreis mit der Steuerlogik verbunden ist, wobei die Treiber in dem Satz von Treibern in der Weise betreibbar sind, daß sie wahlweise Wortleitungen in dem Satz von Wortleitungen mit einer Wortleitungsspannung aus der ersten Versorgungsspannungsquelle oder der zweiten Versorgungsspannungsquelle in Reaktion auf Adressignale treiben, welche die jeweiligen Treiber in dem Lesebetrieb und in dem Programmierbetrieb kennzeichnen.
  9. Integrierter Schaltkreisspeicher nach Anspruch 7 oder 8, wobei der Wortleitungstreiberschaltkreis eine Logik enthält, die bewirkt, daß die Treiber in dem Satz von Treibern während des Löschbetriebs für alle Wortleitungen in dem Satz von Wortleitungen die zweite Versorgungsspannungsquelle auswählen.
  10. Integrierter Schaltkreisspeicher nach Anspruch 9, wobei der Wortleitungstreiberschaltkreis eine Logik enthält, welche die Adressignale, welche die entsprechenden Treiber während des Löschbetriebes kennzeichnen, überschreibt.
  11. Integrierter Schaltkreisspeicher nach Anspruch 7 oder 8, wobei die Treiber in dem Satz von Treibern aufweisen:
    Einen Invertierer (MP3, MT0), der einen Ausgang hat, welcher in Reaktion auf Adressignale, welche den Treiber identifizieren, angesteuert wird, wobei ein erster Versorgungsanschluß mit der ersten Versorgungsspannungsquelle verbunden ist, ein zweiter Versorgungsanschluß mit der zweiten Versorgungsspannungsquelle verbunden ist, ein dritter Versorgungsanschluß mit der dritten Versorgungsspannungsquelle verbunden ist, und ein Ausgang mit einer Wortleitung in dem Satz von Wortleitungen verbunden ist, und
    einen Rückkopplungsschaltkreis (MP0), der zwischen den Ausgang und den Eingang des Invertierers geschaltet ist.
  12. Integrierter Schaltkreisspeicher nach Anspruch 11, wobei der Invertierer aufweist:
    Einen p-Kanal-MOS-Transistor (MP3) in einem Substrat und mit einer Source, die mit dem ersten Versorgungsanschluß verbunden ist, einem Gate, welches mit dem Eingang, und einer Drain, die mit dem Ausgang des Treibers verbunden ist,
    einen n-Kanal-MOS-Transistor (MT0) in dem Substrat, mit einer Source, die mit den zweiten Versorgungsanschluß verbunden ist, einem Gate, welches mit dem Eingang und einer Drain, die mit dem Ausgang des Treibers verbunden ist.
  13. Integrierter Schaltkreisspeicher nach Anspruch 12, wobei der Rückkopplungsschaltkreis aufweist:
    Einen p-Kanal MOS-Transistor (MP0) in einem Substrat und mit einer Source, die mit dem ersten Versorgungsanschluß verbunden ist, einem Gate, welches mit dem Ausgang, und einer Drain, welche mit dem Eingang des Treibers verbunden ist.
  14. Integrierter Schaltkreisspeicher nach Anspruch 7 oder 8, wobei die negative Löschversorgungsspannung einen Wert in dem Bereich von minus 5 bis minus 10 Volt hat.
  15. Integrierter Schaltkreisspeicher nach Anspruch 7 oder 8, wobei die negative Löschversorgungsspannung einen Wert in dem Bereich von minus 5 bis minus 10 Volt hat und wobei die Löschverhinderungsversorgungsspannung einen Wert in dem Bereich von minus 3 bis plus 3 Volt hat.
  16. Integrierter Schaltkreisspeicher nach Anspruch 7, wobei der Wortteitungstreiberschaltkreis eine Segmentdecoderlogik enthält, welche mit Treibern in dem Satz von Treibern verbunden sind, wobei die Segmentdecoderlogik einen Lesemodus hat, in welchem Eingaben in die Treiber des Satzes in Reaktion auf die Adressignale zugeführt werden, welche die Treiber identifizieren, und in welchem der Versorgungsspannungsauswähler, welcher mit dem Segment verbunden ist, eine Leseversorgungsspannung auswählt, und einen Segmentlöschbetrieb hat, in welchem Eingaben in die Treiber der Teilsätze des Satzes von Treibern für entsprechende Segmente in Reaktion auf ein Löschbetriebssignal zugeführt werden und die Versorgungsspannungsauswähler, welche mit den entsprechenden Segmenten verbunden sind, die negative Löschversorgungsspannung oder die Löschverhinderungsversorgungsspannung in Reaktion auf Adressignale auswählen, welche die entsprechenden Segmente identifizieren.
  17. Integrierter Schaltkreisspeicher nach Anspruch 8, wobei die Wortleitungstreiberschaltung eine Segmentdecoderlogik enthält, welche mit Treibern in dem Satz von Treibern verbunden ist, wobei die Segmentdecoderlogik bewirkt, daß Eingaben in die Treiber in dem Satz in Reaktion auf die Adressignale zugeführt werden, welche die Treiber identifizieren, so daß die Treiber in dem Lesebetrieb eine Leseversorgungsspannung auswählen, und welche bewirkt, daß Eingaben in die Treiber in den Teilsätzen des Satzes von Treibern für entsprechende Segmente in dem Löschbetrieb unabhängig von den Adressignalen zugeführt werden, und daß die Versorgungsspannungsauswähler, welche mit den entsprechenden Segmenten verbunden sind, die negative Löschversorgungsspannung oder die Löschvefiinderungsversorgungsspannung in Reaktion auf Adressignale auswählen, welche die entsprechenden Segmente in dem Löschbetrieb identifizieren.
EP98926353A 1998-06-04 1998-06-04 Blockdekodierter wortleitungstreiber mit positiver und negativer spannungsbetriebsart unter verwendung von mos-transistoren mit vier anschlüssen Expired - Lifetime EP1002320B1 (de)

Applications Claiming Priority (1)

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PCT/US1998/011675 WO1999063543A1 (en) 1998-06-04 1998-06-04 Block decoded wordline driver with positive and negative voltage modes using four terminal mos transistors

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EP1002320A4 EP1002320A4 (de) 2003-05-07
EP1002320B1 true EP1002320B1 (de) 2006-04-05

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KR20260015993A (ko) * 2021-05-18 2026-02-03 실리콘 스토리지 테크놀로지 인크 P-기판의 깊은 n-웰 내 p-웰에 형성된 비휘발성 메모리 셀 어레이

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US5265052A (en) * 1989-07-20 1993-11-23 Texas Instruments Incorporated Wordline driver circuit for EEPROM memory cell
JP3068291B2 (ja) * 1990-12-12 2000-07-24 新日本製鐵株式会社 半導体記憶装置
JP2835215B2 (ja) * 1991-07-25 1998-12-14 株式会社東芝 不揮発性半導体記憶装置
US5668758A (en) * 1995-01-26 1997-09-16 Macronix Int'l Co., Ltd. Decoded wordline driver with positive and negative voltage modes
WO1998010471A1 (en) * 1996-09-05 1998-03-12 Macronix International Co., Ltd. Triple well floating gate memory and operating method with isolated channel program, preprogram and erase processes

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DE69834120T2 (de) 2006-10-12
EP1002320A4 (de) 2003-05-07
JP2002517879A (ja) 2002-06-18
WO1999063543A1 (en) 1999-12-09
EP1002320A1 (de) 2000-05-24

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