EP1048082A1 - Circuiterie comprenant au moins un condensateur, et production - Google Patents

Circuiterie comprenant au moins un condensateur, et production

Info

Publication number
EP1048082A1
EP1048082A1 EP98951220A EP98951220A EP1048082A1 EP 1048082 A1 EP1048082 A1 EP 1048082A1 EP 98951220 A EP98951220 A EP 98951220A EP 98951220 A EP98951220 A EP 98951220A EP 1048082 A1 EP1048082 A1 EP 1048082A1
Authority
EP
European Patent Office
Prior art keywords
pores
main
substrate
etching step
layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP98951220A
Other languages
German (de)
English (en)
Inventor
Volker Lehmann
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
Original Assignee
Epcos AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Epcos AG filed Critical Epcos AG
Publication of EP1048082A1 publication Critical patent/EP1048082A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/01—Manufacture or treatment
    • H10D1/045—Manufacture or treatment of capacitors having potential barriers, e.g. varactors
    • H10D1/047—Manufacture or treatment of capacitors having potential barriers, e.g. varactors of conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/62—Capacitors having potential barriers
    • H10D1/66—Conductor-insulator-semiconductor capacitors, e.g. MOS capacitors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/61—Electrolytic etching
    • H10P50/613—Electrolytic etching of Group IV materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/60—Capacitors
    • H10D1/68—Capacitors having no potential barriers
    • H10D1/692—Electrodes
    • H10D1/711—Electrodes having non-planar surfaces, e.g. formed by texturisation
    • H10D1/712—Electrodes having non-planar surfaces, e.g. formed by texturisation being rough surfaces, e.g. using hemispherical grains

Definitions

  • Circuit structure with at least one capacitor and method for its production.
  • Capacitors with large specific capacitance are of interest in many technical fields, for example in microelectronics and for audio and video applications.
  • Electrolytic capacitors based on aluminum or tantalum are known as capacitors with large specific capacitance. These electrolytic capacitors have a specific capacitance in the range from 10 to 100 ⁇ F V / mm 3 .
  • a method for producing a semiconductor capacitor in which the surface of a substrate made of single-crystal silicon is provided with grooves by etching which is dependent on the crystal orientation.
  • the etching is carried out with a 50 percent potassium hydroxide / water mixture at 85 ° C. Troughs with a depth of 500 ⁇ m and a width of 5 ⁇ m, which are arranged at intervals of 10 ⁇ m, are formed. The length of the channels depends on their depth. In this way, the surface of the substrate is enlarged up to 100 times. The maximum achievable specific capacitance is thus limited to 2.3 ⁇ F V / mm 3 in a capacitor manufactured in this way.
  • EP 0 528 281 A has proposed a capacitor which is implemented in a substrate made of single-crystal silicon.
  • an electrochemical etching provides a surface of the substrate with hole openings whose depth is greater than its diameter.
  • the surface of the hole openings is covered with ner dielectric layer and a conductive layer.
  • the electrochemical etching achieves hole structures with an aspect ratio in the range of 1: 1000. Therefore, specific capacitances in the range of typically 10 ⁇ F V / mm 3 are achieved in the capacitor.
  • the arrangement of the hole structures is predetermined by a photolithographically determined etching. This limits the distance between the hole structures to about 1 ⁇ m and thus the specific capacity that can be achieved.
  • the invention is based on the problem of specifying a circuit structure with at least one capacitor in which, compared to the prior art, increased specific capacities can be achieved. Furthermore, a method for producing such a circuit structure is to be specified.
  • a substrate which has main pores in a main area.
  • the depth of the main pores is greater than their diameter.
  • the side walls of the main pores have side pores whose diameter is at least a factor 10 smaller than that of the main pores.
  • the surface of the main pores and the side pores is provided with a dielectric layer, the thickness of which is less than half the diameter of the side pores, so that the surface of the dielectric layer reflects the surface of the main pores and side pores.
  • a conductive layer is arranged on the dielectric layer.
  • the substrate and the conductive layer are each provided with contacts. Since in the condensation If the side walls of the main pores are provided with side pores, the surface area effective for the capacitor is increased again by the surface area of the side pores. This enables the specific capacity to be increased by a factor of 10 to 100.
  • the substrate preferably has monocrystalline silicon at least in the region of the main surface.
  • the capacitor can be manufactured using electrochemical etching.
  • the location of the main pores is predetermined by a masked etching.
  • the side pores are created by changing the process parameters. According to one embodiment of the invention, the side pores are generated by increasing the voltage during the electrochemical etching.
  • the surface of the main pores is provided with an increased doping after the formation of the main pores.
  • the side pores are subsequently formed by electrochemical etching. This takes advantage of the fact that the diameter of the pores depends on the dopant concentration of the silicon.
  • the production of the capacitor using electrochemical etching has the advantage that branching of the side pores can occur when the side pores are formed, which in turn causes an increase in the surface area.
  • the diameter of the main pores is preferably between 1 ⁇ m and 10 ⁇ m.
  • the distance between centers of adjacent main pores is between 2 ⁇ m and 20 ⁇ m.
  • the diameter of the side pores is at least a factor 10 smaller and is between 10 nm and 100 nm, preferably between 10 nm and 50 nm.
  • the main pores are arranged essentially perpendicular to the main surface of the substrate and have a depth of between 100 ⁇ m and 600 ⁇ m.
  • the dielectric layer is formed from silicon dioxide, silicon nitride or titanium dioxide or combinations of these layers. Silicon dioxide is one of the best known dielectrics and can therefore be controlled very well. With a dielectric made of titanium dioxide, larger capacities are achieved because of the higher dielectric constants.
  • the dielectric layer is particularly advantageous to implement the dielectric layer as a triple layer made of silicon oxide, silicon nitride and silicon oxide.
  • a triple layer is often referred to in the specialist literature as an ono layer and has a very low defect density. Defect densities well below 1 / cm 2 are achieved.
  • the conductive layer is preferably formed from doped polysilicon, which is introduced into the side pores and the main pores by CVD deposition. In this way it can be ensured that the conductive layer covers the entire surface of the dielectric layer in the main pores and the side pores.
  • FIG. 1 shows a section through a substrate after the formation of main pores.
  • Figure 2 shows the section through the substrate after formation of a highly doped area.
  • FIG. 3 shows the section through the substrate after the formation of side pores in the side walls of the main pores.
  • Figure 4 shows the section through the substrate after formation of a dielectric layer, a conductive layer and contacts.
  • FIG. 5 shows a section through a substrate after the formation of main pores.
  • Figure 6 shows the section through the substrate after the formation of side pores.
  • FIG. 7 shows the section through the substrate after formation of a dielectric layer, a conductive one
  • the surface topology comprises depressions in the main surface 2, which are produced with the aid of a photolithographically produced photoresist mask and anisotropic etching, for example with KOH (not shown).
  • the main surface 12 is brought into contact with an electrolyte for a first etching step.
  • an electrolyte for a first etching step.
  • hydrofluoric acid is used as the electrolyte.
  • the substrate 11 is acted on as a anode with a potential of, for example, 2 V.
  • the substrate 11 is illuminated from the rear.
  • a current density of, for example, 15 mA / cm 2 is set.
  • the main pores 13 is grid-shaped with a distance between adjacent recesses of 1 ⁇ m. After an etching time of 4 hours, the depth of the main pores 13 is 400 ⁇ m and the diameter of the main pores 13 is 2 ⁇ m with a distance from center to center of 4 ⁇ m.
  • n + -doped region 14 is formed along the surface of the main pores 13 and the main surface 12, in which a dopant concentration of 1 to 3 ⁇ 10 18 cm -3 is present.
  • arsenic or phosphorus is introduced by diffusion and tempering at 1000 ° C (see Figure 2).
  • the main surface 12 is then brought into contact with an electrolyte again for a second section.
  • the electrolyte contains hydrofluoric acid, water and ethanol in a ratio of 1: 1: 2 HF: H2 ⁇ : ethanol.
  • a potential between 1 and 5 V is applied to the substrate 11 in such a way that a current density of 100 mA / cm 2 is established.
  • the electrochemical etching is
  • side pores 15 are formed in the side walls and on the bottom of the main pores.
  • the side pores 15 have pore diameters of 10 to 50 nm.
  • the maximum side pore diameters are at least a factor of 10 smaller than the main pores.
  • the depth of the side pores 15 measured from the side wall of the main pores 13 is 0.5 to 5 ⁇ m (see FIG. 3).
  • the surface of the side pores 15, the main pores 13 and the main surface 12 is subsequently provided with a dielectric layer 16 (see FIG. 4).
  • the dielectric layer 16 is a triple layer which comprises a first silicon umoxid für, a silicon nitride layer and a second silicon oxide layer.
  • the first silicon oxide layer and the second silicon oxide layer are formed by thermal oxidation, the silicon nitride layer by CVD deposition.
  • the dielectric layer 16 is formed in a layer thickness of 5 to 10 nm.
  • the conductive layer 17 is deposited in a thickness of up to 5 ⁇ m, so that it completely fills the side pores 15 and the main pores 13. In this way, that part of the conductive layer 17 which fills the main pores 13 represents a low-resistance connection for that part of the conductive layer 17 which fills the side pores 15.
  • the surface of the n + -doped region 14 is exposed to the side of the main pores 13 in the region of the main surface 12.
  • a masked etching is carried out to structure the conductive layer 17 and the dielectric layer 16.
  • a first contact 18 to the conductive layer 17 and a second contact 19 to the n + -doped region 14 are formed by depositing a metal layer and structuring the metal layer.
  • the first contact 18 and the second contact 19 contain aluminum, for example (see FIG. 4).
  • n + -doped region 14 and the conductive layer 17 form capacitor electrodes and the dielectric layer 15 a capacitor dielectric of a capacitor.
  • main pores 23 are formed in a main surface 22 of a substrate 21 by electrochemical etching (see FIG. 5).
  • the substrate 21 has n-doped, monocrystalline silicon. It is doped to have a resistivity of 5 ⁇ cm.
  • the main pores 23 are made by electrochemical etching generated in an acidic, fluoride-containing electrolyte, preferably in 6 wt .-% hydrofluoric acid.
  • the arrangement of the main pores 23 is predetermined by masked etching using a photoresist mask.
  • the main pores 23 are arranged in a grid. The distance between the centers of adjacent main pores 23 is 2 ⁇ m, for example.
  • the electrochemical etching in the first etching step is continued for 240 minutes.
  • the substrate 21 is connected as an anode and a potential of 2 V is applied to the electrolyte.
  • the electrolyte is in communication with the main surface 22.
  • the etching is continued with these parameters until the main pores 23 have a depth of 400 ⁇ m.
  • the current density required for the etching is set to 15 mA / cm 2 by illuminating the back of the substrate 21.
  • a second etching step the potential applied to the substrate 21 is increased to 10 V.
  • the second step is continued until the side pores 24 have a depth of 0.5 to 5 ⁇ m perpendicular to the side wall of the main pore 23.
  • the side pores 24 are partially branched, which further enlarges the surface.
  • the dielectric layer 25 is formed as a triple layer made of silicon oxide, silicon nitride and silicon oxide by thermal oxidation and CVD deposition.
  • the thickness of the dielectric layer is 5 to 10 nm.
  • a conductive layer 26 is deposited which completely fills the side pores 24 and the main pore 23.
  • the conductive layer 26 is preferably deposited by CVD deposition from doped polysilicon in a layer thickness of 5 ⁇ m.
  • the dielectric layer 25 and the conductive layer 26 are structured in such a way that the main surface 22 to the side of the main pores 23 and the side pores 24 is partially exposed.
  • a first contact 27 and a second contact 28 are formed on the surface of the conductive layer 26 and on the exposed main surface 22 by applying and structuring a metal layer, for example made of aluminum.
  • a metal layer for example made of aluminum.
  • the substrate 21 and the conductive layer 26 each form a capacitor electrode and the dielectric layer 25 forms the capacitor dielectric.
  • the main pores 23 and the side pores 24 bring about an increase in surface area from 2000 to 20,000.
  • the capacitor thus has a specific capacitance of 50 to 500 ⁇ FV / mm 3 .
  • the second contact to the substrate can be arranged on the back of the substrate. Furthermore, a large number of capacitors can be produced within a substrate.

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Weting (AREA)
  • Semiconductor Memories (AREA)

Abstract

La présente invention concerne un condensateur réalisé dans un substrat, notamment un substrat de silicone, dont la surface principale présente des pores principales d'une profondeur supérieure à leur diamètre et dont les parois latérales présentent des pores latérales dont le diamètre est inférieur à celui des pores principales d'au moins un facteur 10. La surface des pores principales et des pores latérales est recouverte d'une couche diélectrique et d'une couche conductrice. Les pores principales et les pores latérales permettent un agrandissement de la surface, d'où la possibilité de fabriquer un condensateur d'une capacité spécifique comprise entre 50 et 500 mu F V/mm<3>.
EP98951220A 1997-11-12 1998-08-26 Circuiterie comprenant au moins un condensateur, et production Ceased EP1048082A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19750148 1997-11-12
DE19750148 1997-11-12
PCT/DE1998/002507 WO1999025026A1 (fr) 1997-11-12 1998-08-26 Circuiterie comprenant au moins un condensateur, et production

Publications (1)

Publication Number Publication Date
EP1048082A1 true EP1048082A1 (fr) 2000-11-02

Family

ID=7848515

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98951220A Ceased EP1048082A1 (fr) 1997-11-12 1998-08-26 Circuiterie comprenant au moins un condensateur, et production

Country Status (4)

Country Link
EP (1) EP1048082A1 (fr)
JP (1) JP2001523050A (fr)
KR (1) KR20010031974A (fr)
WO (1) WO1999025026A1 (fr)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10055712B4 (de) * 2000-11-10 2006-07-13 Infineon Technologies Ag Verfahren zur Herstellung von Grabenkondensatoren für hochintegrierte Halbleiterspeicher
DE10055711B4 (de) * 2000-11-10 2008-04-30 Qimonda Ag Verfahren zur Herstellung von Grabenkondensatoren
DE10138981B4 (de) 2001-08-08 2005-09-08 Infineon Technologies Ag Verfahren zur Bildung von Siliziumoxid durch elektrochemische Oxidation eines Halbleiter-Substrats mit Vertiefungen
DE10143283C1 (de) 2001-09-04 2002-12-12 Infineon Technologies Ag Verfahren zur Herstellung eines Grabenkondensators für einen Halbleiterspeicher
DE10143936A1 (de) 2001-09-07 2003-01-09 Infineon Technologies Ag Verfahren zur Bildung eines SOI-Substrats, vertikaler Transistor und Speicherzelle mit vertikalem Transistor
EP1306894A1 (fr) 2001-10-19 2003-05-02 Infineon Technologies AG Méthode de formation d'une couche de dioxyde de silicium sur une surface de Si courbe
DE10153187C1 (de) * 2001-10-27 2003-07-10 Infineon Technologies Ag Herstellungsverfahren zum Herstellen einer räumlichen Struktur in einem Halbleitersubstrat und Halbleitersubstrat mit einer Einrichtung zum Ätzen einer räumlichen Struktur in dem Halbleitersubstrat
DE10217569A1 (de) * 2002-04-19 2003-11-13 Infineon Technologies Ag Vorrichtung auf Basis von partiell oxidiertem porösen Silizium
DE10242877A1 (de) * 2002-09-16 2004-03-25 Infineon Technologies Ag Halbleitersubstrat sowie darin ausgebildete Halbleiterschaltung und zugehörige Herstellungsverfahren
EP2278614B1 (fr) * 2009-07-21 2013-04-03 STMicroelectronics (Crolles 2) SAS Via de connexion électrique comportant des excroissances latérales
JP7027352B2 (ja) * 2019-01-21 2022-03-01 株式会社東芝 コンデンサ
CN113544847A (zh) * 2019-03-13 2021-10-22 松下知识产权经营株式会社 电容器及其制造方法
EP3966875A1 (fr) * 2019-04-05 2022-03-16 Arno Mecklenburg Condensateur intégrable
JPWO2021186893A1 (fr) * 2020-03-17 2021-09-23
TW202243237A (zh) 2021-04-21 2022-11-01 日商松下知識產權經營股份有限公司 電容器
JP7676334B2 (ja) 2022-01-28 2025-05-14 株式会社村田製作所 電子部品、電子回路および電子部品の製造方法
WO2024116968A1 (fr) * 2022-11-29 2024-06-06 パナソニックＩｐマネジメント株式会社 Condensateur
WO2025154391A1 (fr) * 2024-01-17 2025-07-24 パナソニックＩｐマネジメント株式会社 Interposeur

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0296348A1 (fr) * 1987-05-27 1988-12-28 Siemens Aktiengesellschaft Procédé d'attaque pour creuser des trous ou des sillons dans du silicium de type n

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0424623B1 (fr) * 1989-10-26 1995-07-12 International Business Machines Corporation Structures tridimensionnelles à semi-conducteur formées par des couches planares
JPH05160342A (ja) * 1991-12-02 1993-06-25 Canon Inc 半導体装置及びその製造方法
US5508542A (en) * 1994-10-28 1996-04-16 International Business Machines Corporation Porous silicon trench and capacitor structures

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0296348A1 (fr) * 1987-05-27 1988-12-28 Siemens Aktiengesellschaft Procédé d'attaque pour creuser des trous ou des sillons dans du silicium de type n

Also Published As

Publication number Publication date
WO1999025026A1 (fr) 1999-05-20
KR20010031974A (ko) 2001-04-16
JP2001523050A (ja) 2001-11-20

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