EP1080413A4 - Procede et appareil pour programmer un ensemble de registres dans un processeur graphique - Google Patents

Procede et appareil pour programmer un ensemble de registres dans un processeur graphique

Info

Publication number
EP1080413A4
EP1080413A4 EP98921155A EP98921155A EP1080413A4 EP 1080413 A4 EP1080413 A4 EP 1080413A4 EP 98921155 A EP98921155 A EP 98921155A EP 98921155 A EP98921155 A EP 98921155A EP 1080413 A4 EP1080413 A4 EP 1080413A4
Authority
EP
European Patent Office
Prior art keywords
programming
register set
graphics subsystem
subsystem register
graphics
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP98921155A
Other languages
German (de)
English (en)
Other versions
EP1080413A1 (fr
Inventor
Michael K Larson
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
S3 Graphics Co Ltd
Original Assignee
S3 Graphics Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by S3 Graphics Co Ltd filed Critical S3 Graphics Co Ltd
Publication of EP1080413A1 publication Critical patent/EP1080413A1/fr
Publication of EP1080413A4 publication Critical patent/EP1080413A4/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06T—IMAGE DATA PROCESSING OR GENERATION, IN GENERAL
    • G06T1/00—General purpose image data processing
    • G06T1/20—Processor architectures; Processor configuration, e.g. pipelining

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Controls And Circuits For Display Device (AREA)
  • Bus Control (AREA)
EP98921155A 1998-05-12 1998-05-12 Procede et appareil pour programmer un ensemble de registres dans un processeur graphique Withdrawn EP1080413A4 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US1998/009688 WO1999059068A1 (fr) 1998-05-12 1998-05-12 Procede et appareil pour programmer un ensemble de registres dans un processeur graphique

Publications (2)

Publication Number Publication Date
EP1080413A1 EP1080413A1 (fr) 2001-03-07
EP1080413A4 true EP1080413A4 (fr) 2006-02-01

Family

ID=22267044

Family Applications (1)

Application Number Title Priority Date Filing Date
EP98921155A Withdrawn EP1080413A4 (fr) 1998-05-12 1998-05-12 Procede et appareil pour programmer un ensemble de registres dans un processeur graphique

Country Status (4)

Country Link
EP (1) EP1080413A4 (fr)
JP (1) JP4846097B2 (fr)
AU (1) AU7383198A (fr)
WO (1) WO1999059068A1 (fr)

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0447145A2 (fr) * 1990-03-12 1991-09-18 Hewlett-Packard Company Accès direct mémoire planifié par l'usager utilisant des adresses virtuelles
EP0627699A2 (fr) * 1993-06-04 1994-12-07 Sun Microsystems, Inc. Préprocesseur de commande pour accélérateur graphique tridimensionel à haute performance
US5657479A (en) * 1995-12-04 1997-08-12 Silicon Graphics, Inc. Hierarchical display list processing in graphics data retrieval system
US5706478A (en) * 1994-05-23 1998-01-06 Cirrus Logic, Inc. Display list processor for operating in processor and coprocessor modes

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5524265A (en) * 1994-03-08 1996-06-04 Texas Instruments Incorporated Architecture of transfer processor

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0447145A2 (fr) * 1990-03-12 1991-09-18 Hewlett-Packard Company Accès direct mémoire planifié par l'usager utilisant des adresses virtuelles
EP0627699A2 (fr) * 1993-06-04 1994-12-07 Sun Microsystems, Inc. Préprocesseur de commande pour accélérateur graphique tridimensionel à haute performance
US5706478A (en) * 1994-05-23 1998-01-06 Cirrus Logic, Inc. Display list processor for operating in processor and coprocessor modes
US5657479A (en) * 1995-12-04 1997-08-12 Silicon Graphics, Inc. Hierarchical display list processing in graphics data retrieval system

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO9959068A1 *

Also Published As

Publication number Publication date
JP4846097B2 (ja) 2011-12-28
JP2002514817A (ja) 2002-05-21
AU7383198A (en) 1999-11-29
EP1080413A1 (fr) 2001-03-07
WO1999059068A1 (fr) 1999-11-18

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Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20001212

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): GB

RAP1 Party data changed (applicant data changed or rights of an application transferred)

Owner name: S3 GRAPHICS CO., LTD.

A4 Supplementary search report drawn up and despatched

Effective date: 20051221

RIC1 Information provided on ipc code assigned before grant

Ipc: G06F 12/06 20060101ALI20051215BHEP

Ipc: G06T 1/20 20060101AFI20051215BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 20060913