EP1084285B1 - Membrane en silicium perforee produite selon un procede d'attaque electrochimique - Google Patents

Membrane en silicium perforee produite selon un procede d'attaque electrochimique Download PDF

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Publication number
EP1084285B1
EP1084285B1 EP99929077A EP99929077A EP1084285B1 EP 1084285 B1 EP1084285 B1 EP 1084285B1 EP 99929077 A EP99929077 A EP 99929077A EP 99929077 A EP99929077 A EP 99929077A EP 1084285 B1 EP1084285 B1 EP 1084285B1
Authority
EP
European Patent Office
Prior art keywords
substrate
area
main surface
pores
mask layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
EP99929077A
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German (de)
English (en)
Other versions
EP1084285A1 (fr
Inventor
Volker Lehmann
Hans Reisinger
Hermann Wendt
Reinhard Stengl
Gerrit Lange
Stefan Ottow
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
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Infineon Technologies AG
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Publication date
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Publication of EP1084285A1 publication Critical patent/EP1084285A1/fr
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Publication of EP1084285B1 publication Critical patent/EP1084285B1/fr
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25FPROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00Electrolytic etching or polishing
    • C25F3/02Etching
    • C25F3/12Etching of semiconducting materials
    • CCHEMISTRY; METALLURGY
    • C25ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25FPROCESSES FOR THE ELECTROLYTIC REMOVAL OF MATERIALS FROM OBJECTS; APPARATUS THEREFOR
    • C25F3/00Electrolytic etching or polishing
    • C25F3/02Etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P1/00Auxiliary devices
    • H01P1/20Frequency-selective devices, e.g. filters
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T428/00Stock material or miscellaneous articles
    • Y10T428/24Structurally defined web or sheet [e.g., overall dimension, etc.]
    • Y10T428/24273Structurally defined web or sheet [e.g., overall dimension, etc.] including aperture
    • Y10T428/24322Composite web or sheet
    • Y10T428/24331Composite web or sheet including nonapertured component

Definitions

  • Perforated are used for various technical applications Workpieces, especially as inexpensive optical or mechanical Filters with pore diameters in the micrometer or submicron range needed.
  • Such applications include isoporous membranes, backwashable filters, laminators, Catalyst carriers, reagent carriers, electrodes for batteries and fuel cells, nozzle plates, tubular grids or Filters for electromagnetic waves such as light or microwaves.
  • a method for producing a perforated workpiece known, with the pore diameter in this area can be produced.
  • a substrate wafer made of n-doped monocrystalline silicon through electrochemical etching holes formed perpendicular to the first surfaces, so that a structured Layer arises.
  • the electrochemical etching takes place in a fluoride-containing electrolyte in which the substrate is connected as an anode.
  • the process parameters are changed so that the Cross-section of the holes grows and the structured layer detached as a plate from which the workpiece is formed becomes.
  • the invention is based on the problem of a perforated Specify workpiece and a method for its production, which has increased mechanical strength.
  • the workpiece has a substrate made of silicon, in which a first area and a second area are provided. In In the first area, pores cross the substrate from one first main surface to a second main surface. In the first Area the workpiece is perforated. In a second Pores are provided starting from the first Main surface extend into the substrate that However, do not cross the substrate. This is below the Pores present in the second region of solid substrate material, which increases the stability of the perforated workpiece. As a result, the perforated workpiece is smaller Danger of destruction can be installed.
  • the thickness of the substrate is in the direction of the depth of the pores preferably larger in the second area than in the first Area.
  • first areas for use as a catalyst or reagent carrier define different filter ranges.
  • the second area in a ring shape and the first Arrange area within the second area.
  • the solid border in the second area acts as Frame for the perforated workpiece.
  • the perforated workpiece is used electrochemical etching.
  • This will be done in a first main surface of a substrate made of silicon by electrochemical Etching creates pores whose depth is less than is the thickness of the substrate.
  • the mask layer is in the area of the second Main area structured so that the second main area is exposed in the first area.
  • a structured mask layer as an etching mask becomes the substrate then in the area of the exposed second main area etched at least to the bottom of the pores. Then will the mask layer is removed so that those arranged in the first region Pores the substrate from the first major surface to cross the second main area.
  • the mask layer is preferably formed from Si 3 N 4 or SiO 2 .
  • Etching the substrate to form the continuous pores in the first area preferably with KOH.
  • This results in for the second area in the area of the second Main area is an edge area with a surface with a ⁇ 111> orientation.
  • the electrochemical etching is preferably carried out in one fluoride-containing, acidic electrolytes, the substrate being Anode of an electrolysis cell is connected. Since that If the substrate is connected as an anode, minority charge carriers move in the silicon to that with the electrolyte in Contact the first main area. One forms there Space charge zone. Because the field strength in the area of depressions is always larger in a surface than outside it, the minority charge carriers move preferentially such wells, with statistical distribution in each Surface are present. This leads to a Structuring the first main area. The deeper one is initially small unevenness due to the etching, the more minority carriers move because of the enlarged Field strength there and the stronger the etching attack this place. The holes grow in the substrate in the crystallographic ⁇ 100> direction.
  • the diameter of the holes is preferably 2 ⁇ m.
  • a substrate 1 made of n-doped, single-crystal silicon a resistivity of 5 ohm cm is at a first Main surface 2 provided with a surface topology.
  • the surface topology includes those arranged at regular intervals Wells made using photolithographic Process steps produced by an alkaline etching become.
  • the surface topology can be light-induced, electrochemical etching are formed.
  • the first main surface 2 of the substrate 1 is covered with a fluoride-containing acidic electrolytes brought into contact.
  • the Electrolyte has a hydrofluoric acid concentration of 2 to 10 percent by weight, preferably 5 percent by weight.
  • the electrolyte an oxidizing agent, for example hydrogen superoxide, added to the development of hydrogen bubbles on the first main surface 2 of the substrate 1 suppress.
  • the substrate 1 is connected as an anode.
  • a voltage of 1.5 to 5 volts, preferably 3 volts, is applied between the substrate 1 and the electrolyte.
  • the substrate 1 is illuminated from a second main surface 3, which lies opposite the first main surface 2, so that a current density of 10 mA per cm 2 is set.
  • pores 4 are generated during the electrochemical etching and run perpendicular to the first main surface 2 (see FIG. 1). After an etching time of 4.5 hours, the pores 4 reach a depth of 300 ⁇ m, measured from the first main surface 2 in the direction of the pore depth, and a diameter of 2 ⁇ m. The distance between adjacent pores 4 is 4 ⁇ m.
  • a mask layer 5 made of silicon nitride is formed by CVD deposition formed in a thickness of 100 nm.
  • the mask layer 5 covers both the first main surface 2 and the second The main surface 3 and the surface of the pores 4.
  • the mask layer 5 is structured in the area of the second main surface 3 with the aid of a photolithographically generated mask (not shown) and a plasma etching using CF 4 , O 2 (see FIG. 2). This defines first areas 6 and second areas 7.
  • the second main surface 3 is exposed in the first regions 6. In the second regions 7, the second main surface 3 is still covered by the mask layer 5.
  • the first main surface 2 and the surface of the pores 4 are also completely covered by the mask layer 5.
  • etching with KOH at a concentration of 50 percent by weight is then the substrate 1 at least until etched to the bottom of the pores 4.
  • the substrate 1 is etched measured to a depth from the second main surface 3 of 350 ⁇ m with a substrate thickness of 625 ⁇ m. This will in the first areas 6 in the area of the bottom of the pores 4 the surface of the mask layer 5 is exposed (see figure 3).
  • the etching attack takes place along preferred crystallographic directions, so that on the edge of the second regions 7 form edge regions 71 which form a surface with ⁇ 111> orientation.
  • first areas 6 has continuous pores 4 (see Figure 4).
  • the first Area 6 is adjacent to the second areas 7, in which the pores do not cross the substrate 1.
  • the second Areas 7 give the perforated workpiece stability.
  • the first areas 6 have 6 different shapes (see supervision in Figure 5).
  • the first areas 6 can large area, for example rectangular or square, with a variety of pores, elongated with a series of pores or be square with only one pore.
  • the first area 6 is due to the etching with KOH for exposure the bottoms of the pores 4 in the first area 6 of the Edge area 71 of one of the second areas 7 surround.
  • the geometrical The shape of the second regions 7 corresponds to that Stability requirements selected. It corresponds in particular Webs, a grid, individual windows, one Scoring frame or identification features.
  • the mask layer 5 can be formed from SiO 2 by thermal oxidation.

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  • Chemical & Material Sciences (AREA)
  • Engineering & Computer Science (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Metallurgy (AREA)
  • Organic Chemistry (AREA)
  • Weting (AREA)
  • Micromachines (AREA)

Claims (9)

  1. Pièce perforée
    dans laquelle il est prévu un substrat (1) en silicium qui a une première partie (6) et une deuxième partie (7),
    dans laquelle il est prévu dans la première partie (6) des pores (4) qui traversent le substrat (1) d'une première surface (2) principale à une deuxième surface (3) principale,
    dans laquelle il est prévu dans la deuxième partie (7) des pores qui s'étendent à partir de la première surface (3) principale dans le substrat (1), mais qui ne traversent pas le substrat (1) de part en part.
  2. Pièce suivant la revendication 1, dans laquelle la deuxième partie (7) a, dans la zone de la deuxième surface (3) principale, une zone (71) marginale ayant une surface à orientation <111>.
  3. Pièce perforée suivant la revendication 1 ou 2,
    dans laquelle la profondeur des pores (4) dans la première partie (6) et dans la deuxième partie (7) est sensiblement la même,
    dans laquelle le substrat (1) est plus épais suivant la direction de la profondeur des pores dans la deuxième partie (7) que dans la première partie (6).
  4. Procédé de production d'une pièce perforée,
    dans lequel on produit, dans une première surface (2) principale de substrat (1) en silicium, par attaque électrochimique, des pores (4) dont la profondeur est plus petite que l'épaisseur du substrat (1),
    dans lequel on munit la première surface (2) principale, la surface des pores (4) et une deuxième surface (3) principale opposée à la première surface (2) principale d'une couche (5) de masquage,
    dans lequel on structure la couche (5) de masquage dans la zone de la deuxième surface (3) principale, de façon à dénuder la deuxième surface (3) dans une première partie (6),
    dans lequel, en utilisant la couche structurée de masquage comme masque d'attaque, on attaque le substrat (1) au moins jusqu'au fond des pores (2),
    dans lequel on élimine la couche (5) de masquage de sorte que les pores (4) disposés dans la première partie (6) traversent le substrat (1) de la première surface (2) principale à la deuxième surface (3) principale.
  5. Procédé suivant la revendication 4, dans lequel la couche (5) de masquage est en Si3N4.
  6. Procédé suivant la revendication 4 ou 5, dans lequel on effectue l'attaque de substrat (1) par de la KOH.
  7. Procédé suivant l'une des revendications 4 à 6, dans lequel on effectue l'attaque électrochimique dans un électrolyte actif contenant du fluorure, le substrat étant monté en anode d'une cellule d'électrolyse.
  8. Procédé suivant la revendication 7,
    dans lequel on utilise un électrolyte acide contenant du fluorure en une concentration comprise entre 2 % en poids d'acide fluorhydrique et 10 % en poids d'acide fluorhydrique,
    dans lequel on applique, lors de l'attaque électrochimique, une tension comprise entre 1,5 V et 3 V.
  9. Procédé suivant l'une des revendications 4 à 8,
       dans lequel on éclaire la deuxième surface (3) principale du substrat (1) lors de l'attaque électrochimique pour régler la densité de courant dans le substrat (1).
EP99929077A 1998-05-08 1999-05-03 Membrane en silicium perforee produite selon un procede d'attaque electrochimique Expired - Lifetime EP1084285B1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19820756 1998-05-08
DE19820756A DE19820756C1 (de) 1998-05-08 1998-05-08 Perforiertes Werkstück und Verfahren zu dessen Herstellung
PCT/DE1999/001292 WO1999058746A1 (fr) 1998-05-08 1999-05-03 Membrane en silicium perforee produite selon un procede d'attaque electrochimique

Publications (2)

Publication Number Publication Date
EP1084285A1 EP1084285A1 (fr) 2001-03-21
EP1084285B1 true EP1084285B1 (fr) 2003-08-06

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ID=7867190

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99929077A Expired - Lifetime EP1084285B1 (fr) 1998-05-08 1999-05-03 Membrane en silicium perforee produite selon un procede d'attaque electrochimique

Country Status (7)

Country Link
US (1) US6558770B1 (fr)
EP (1) EP1084285B1 (fr)
JP (1) JP2002514689A (fr)
KR (1) KR20010052320A (fr)
DE (2) DE19820756C1 (fr)
TW (1) TW552322B (fr)
WO (1) WO1999058746A1 (fr)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6808840B2 (en) * 1999-11-17 2004-10-26 Neah Power Systems, Inc. Silicon-based fuel cell electrode structures and fuel cell electrode stack assemblies
US6924058B2 (en) * 1999-11-17 2005-08-02 Leroy J. Ohlsen Hydrodynamic transport and flow channel passageways associated with fuel cell electrode structures and fuel cell electrode stack assemblies
EP1232533A2 (fr) * 1999-11-17 2002-08-21 Neah Power Systems, Inc. Piles a combustible ayant des substrats de silicium et/ou des structures de soutien derivees de sol-gel
US6720105B2 (en) * 1999-11-17 2004-04-13 Neah Power Systems, Inc. Metallic blocking layers integrally associated with fuel cell electrode structures and fuel cell electrode stack assemblies
DE10052007C1 (de) * 2000-10-20 2002-03-07 Infineon Technologies Ag Halbleiterbauelement mit durchgehenden Kompensationszonen
DE10122839B4 (de) * 2001-05-11 2007-11-29 Qimonda Ag Verfahren zum Vereinzeln von Halbleiterstrukturen sowie zum Vereinzeln vorbereitetes Halbleitersubstrat
EP1258937A1 (fr) * 2001-05-17 2002-11-20 STMicroelectronics S.r.l. Micropile à combustible à silicium, méthode de fabrication et dispositif semiconducteur autonome comportant une micropile à combustible
KR100451132B1 (ko) * 2001-11-08 2004-10-02 홍석인 다공성 실리콘을 이용한 효소고정화 전극 제작 방법
WO2003058734A1 (fr) * 2002-01-03 2003-07-17 Neah Power Systems, Inc. Structures d'electrode de pile a combustible poreuses recouvertes de couches electriquement conductrices enrobantes
DE10217569A1 (de) * 2002-04-19 2003-11-13 Infineon Technologies Ag Vorrichtung auf Basis von partiell oxidiertem porösen Silizium
MD2449G2 (ro) * 2003-03-14 2004-11-30 Ион ТИГИНЯНУ Procedeu de obţinere a membranelor perforate ultrasubţiri
DE10362083B4 (de) * 2003-04-25 2007-05-03 Christian-Albrechts-Universität Zu Kiel Verfahren zur Herstellung von Membranen mit durchgängigen Poren
DE10318995B4 (de) * 2003-04-25 2006-04-20 Christian-Albrechts-Universität Zu Kiel Verfahren zur Herstellung von durchgängigen Membranen
US7081158B2 (en) * 2003-11-21 2006-07-25 Imaje S.A. Ink composition for continuous deflected jet printing, especially on letters and postal articles
DE102005010080B4 (de) * 2005-03-03 2008-04-03 Qimonda Ag Verfahren zum Herstellen einer Dünnschicht-Struktur
ITVA20050034A1 (it) * 2005-05-13 2006-11-14 St Microelectronics Srl Celle a combustibile realizzate in un singolo strato di silicio monocristallino e processo di fabbricazione
US7615161B2 (en) * 2005-08-19 2009-11-10 General Electric Company Simplified way to manufacture a low cost cast type collimator assembly
EP1798799B1 (fr) * 2005-12-16 2008-09-24 STMicroelectronics S.r.l. Pile à combustible planairement intégrée sur un circuit intégré de silicium monocristallin et procédé de fabrication
KR100731549B1 (ko) * 2006-07-21 2007-06-22 이노필터 주식회사 다공성 복합 세라믹 분리막 제조방법과, 이에 의해 제조된다공성 복합 세라믹 분리막
JP4562801B2 (ja) * 2007-05-09 2010-10-13 株式会社カンタム14 シリコン基材の加工方法および加工装置
TWI464108B (zh) * 2012-01-17 2014-12-11 Nat Univ Kaohsiung The preparation of porous silicon nanowires and the prepared porous silicon nanowires
TWI500825B (zh) * 2013-05-02 2015-09-21 Nat Univ Tsing Hua V-vi族半導體之奈米片狀陣列結構之製備方法

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4044222A (en) * 1976-01-16 1977-08-23 Western Electric Company, Inc. Method of forming tapered apertures in thin films with an energy beam
US4570173A (en) * 1981-05-26 1986-02-11 General Electric Company High-aspect-ratio hollow diffused regions in a semiconductor body
US5139624A (en) * 1990-12-06 1992-08-18 Sri International Method for making porous semiconductor membranes
DE4202454C1 (fr) * 1992-01-29 1993-07-29 Siemens Ag, 8000 Muenchen, De
EP0630058A3 (fr) * 1993-05-19 1995-03-15 Siemens Ag Procédé de fabrication d'un arrangement de pyrodétecteurs par gravure électrochimique d'un substrat de silicium.
DE4426507C2 (de) * 1994-07-27 2001-04-26 Inst Chemo Biosensorik Sensoren auf der Basis von Mikrostrukturen
JP2002512737A (ja) * 1997-05-08 2002-04-23 ナノシステムズ,インコーポレイテッド マイクロチャンネルプレートを製造するためのシリコンエッチング方法

Also Published As

Publication number Publication date
DE19820756C1 (de) 1999-11-11
EP1084285A1 (fr) 2001-03-21
KR20010052320A (ko) 2001-06-25
DE59906526D1 (de) 2003-09-11
JP2002514689A (ja) 2002-05-21
TW552322B (en) 2003-09-11
WO1999058746A1 (fr) 1999-11-18
US6558770B1 (en) 2003-05-06

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