EP1115134B1 - Feldemissionsvorrichtung und Herstellungsverfahren dafür - Google Patents

Feldemissionsvorrichtung und Herstellungsverfahren dafür Download PDF

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Publication number
EP1115134B1
EP1115134B1 EP01300051A EP01300051A EP1115134B1 EP 1115134 B1 EP1115134 B1 EP 1115134B1 EP 01300051 A EP01300051 A EP 01300051A EP 01300051 A EP01300051 A EP 01300051A EP 1115134 B1 EP1115134 B1 EP 1115134B1
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EP
European Patent Office
Prior art keywords
micro
tips
gate electrode
focus
insulation layer
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Expired - Lifetime
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EP01300051A
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English (en)
French (fr)
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EP1115134A1 (de
Inventor
Jun-Hee Choi
Seung-Nam Cha
Hang-Woo Lee
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Samsung SDI Co Ltd
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Samsung SDI Co Ltd
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J3/00Details of electron-optical or ion-optical arrangements common to two or more basic types of discharge tubes or lamps
    • H01J3/02Electron guns
    • H01J3/021Electron guns using a field emission, photo emission, or secondary emission electron source
    • H01J3/022Electron guns using a field emission, photo emission, or secondary emission electron source with microengineered cathode, e.g. Spindt-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J1/00Details of electrodes, of magnetic control means, of screens, or of the mounting or spacing thereof, common to two or more basic types of discharge tubes or lamps
    • H01J1/02Main electrodes
    • H01J1/30Cold cathodes, e.g. field-emissive cathode
    • H01J1/304Field-emissive cathodes
    • H01J1/3042Field-emissive cathodes microengineered, e.g. Spindt-type
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01JELECTRIC DISCHARGE TUBES OR DISCHARGE LAMPS
    • H01J9/00Apparatus or processes specially adapted for the manufacture, installation, removal, maintenance of electric discharge tubes, discharge lamps, or parts thereof; Recovery of material from discharge tubes or lamps
    • H01J9/02Manufacture of electrodes or electrode systems
    • H01J9/022Manufacture of electrodes or electrode systems of cold cathodes
    • H01J9/025Manufacture of electrodes or electrode systems of cold cathodes of field emission cathodes

Definitions

  • the present invention relates to a field emission device (FED) which is capable of focusing an electron beam on an anode, and ensures stable operation with high anode voltages, and a method for fabricating the FED.
  • FED field emission device
  • FIG. 1 A FED panel with a conventional FED is illustrated in FIG. 1.
  • a cathode 2 is formed over a substrate 1 with a metal such as chromium (Cr), and a resistor layer 3 is formed over the cathode 2 with an amorphous silicon.
  • a micro-tip 5 formed of a metal such as molybdenum (Mo) is located in the well 4a.
  • a gate electrode 6 with a gate 6a aligned with the well 4a is formed on the gate insulation layer 4.
  • An anode 7 is located a predetermined distance above the gate electrode 6.
  • the gate electrode 6 is formed on the inner surface of a faceplate 8 that forms a vacuum cavity associated with the substrate 1.
  • the faceplate 8 and the substrate 1 are spaced apart from each other by a spacer (not shown), and sealed at the edges.
  • a phosphor screen (not shown) is placed on or near the anode 7.
  • the simple configuration of the conventional FED in which the cathode and anode are spaced apart from each other by just spacers, is not enough to ensure a reliable FED operable with high voltages.
  • the brightness of FED panel depends on the anode voltage level.
  • a high-brightness FED cannot be manufactured using the conventional FED.
  • the conventional FED cannot focus an electron beam emitted by the micro-tips on the anode, so that it is difficult to achieve a high-resolution display.
  • a color display with high-color purity cannot be implemented by such a FED.
  • a field emission device with framing structures is described in US 6,008,062. Conical electron-emitter elements are formed, and protected during formation of the focusing structure.
  • US 5,836,796 describes a process of depositing carbon diamond particles on micro-tips of a field emission source.
  • FED field emission display
  • a field emission device FED according to claim 1.
  • a resistor layer is formed over or beneath the cathode, or a resistor layers is formed over and beneath the cathode in the FED.
  • the carbonaceous polymer layer is formed of polyimide or photoresist.
  • the carbonaceous polymer layer may be etched by reactive ion etching (REI).
  • REI reactive ion etching
  • the nano-sized surface features of the micro-tips can be adjusted by varying the etch rates of the carbonaceous polymer layer and the micro-tips. It is preferable that the etch rates are adjusted by varying the oxygen-to-the gas for the micro-chips in the reaction gas, plasma power, or plasma pressure during the etching processes.
  • the micro-tips are formed of at least one selected from the group molybdenum (Mo), tungsten (W), silicon (Si) and diamond.
  • the reaction gas may be a gas mixture of O 2 and fluorine-based gas, such CF 4 /O 2 , SF 6 /O 2 , CHF 3 /O 2 , CF 4 /SF 6 /O 2 , CF 4 /CHF 3 /O 2 , or SF 6 /CHF 3 /O 2 .
  • the reaction gas may be a gas mixture of O 2 and chlorine-based gas, such Cl 2 /O 2 , CCl 4 /O 2 , or Cl 2 /CCl 4 /O 2 .
  • FIG. 2 is a plan view of a field emission device (FED) according to the present invention
  • a cathode 120 and a gate electrode 160 are arranged in a x-y matrix at the center of a substrate 100, and a focus gate electrode 190 that is a feature of the present invention is arranged over the cathode 120 and the gate electrode 160.
  • the cathode 120 and the gate electrode 140 are electrically connected to pads 121 and 161, respectively, arranged on the edges of the substrate 100.
  • the focus gate electrode 190 has a focus gate 190a through which the cross-overlapped portion of the cathode 130 and the gate electrode 160 is exposed.
  • the gate electrode 160 with the gate 160a is exposed through the post gate 190a.
  • the focus gate electrode 190 is located such that the cross-overlapped portion of the cathode 120 and the gate electrode 160, i.e., corresponding to a single pixel, is exposed through its focus gate 190a.
  • the distance between the gate electrode 190 and the pads 121 and 161 are determined in the range of 0.1-15 mm, such that the gate electrode 160 and the cathode 120 are fully covered with the focus gate electrode 190.
  • the focus gate electrode 190 is electrically coupled with an external ground, thereby providing electron emission when an arching occurs with a high voltage. As a result, the underlying layers can be protected from damage.
  • FIG. 4 is a sectional view taken long line A-A' of FIG. 3.
  • a cathode 120 is formed over a substrate 100 with a metal such as chromium (Cr), and a resistor layer 130 is formed over the cathode 120 with an amorphous silicon.
  • Use of the resistor layer 130 is optional. In other words, formation of the resistor layer 130 may be omitted so that the cathode 120 is exposed through the well 140a.
  • a micro-tip 150 which is a feature of the present invention, is formed in the well 140a on the resist layer 130 with a metal such as molybdenum (Mo).
  • Mo molybdenum
  • a micro-tip 150 is a collection of a large number of nano-tips with nano-size surface features.
  • the micro-tip 150 is formed of Mo, W, Si or diamond, or a combination of these materials.
  • a gate electrode 160 with a gate 160a aligned with the well 140a is formed on the gate insulation layer 140.
  • a focus gate insulation layer 191 is formed on the gate electrode 160 with polyimide, and the focus gate electrode 190 mentioned above is formed over the focus gate insulation layer 191.
  • the focus gate electrode 191 is formed of Al, Cr, Cr/Mo alloy, Al/Mo alloy, or Al/Cr alloy.
  • the focus gate insulation layer 191 has an opening corresponding to the focus gate 190a of the focus gate electrode 190.
  • an appropriate voltage is applied to the focus gate electrode 190, so that electric field around the gate 160a of the gate electrode 160 becomes weak, thereby preventing arcing at the sharp edges of the gate 160a.
  • an arcing occurs within the FED, ions generated due to the arcing are collected by the focus gate electrode 190 and then grounded before the cathode 120 or the resistor layer 130 are attacked by the ions.
  • an electrical short between the cathode 120 and an anode (not shown), as well as a physical damage thereof caused by arcing can be prevented.
  • An electron beam emitted by the micro-tip 150 can be focused by adjusting the thickness of the focus gate insulation layer 191, such that a small spot can be formed on the anode.
  • a high-color purity can be achieved for color displays.
  • the opening of the focus gate insulation layer 191 is formed by reactive ion etching (RIE).
  • RIE reactive ion etching
  • the RIE conditions are adjusted to appropriately vary the geometry of the micro-tip 150 exposed through the opening, i.e., to form the micro-tip 150 with nano-sized surface features. By doing so, the gate turn-on voltage can be lowered by more than 30V compared with a convention FED.
  • a cathode 120, a resistor layer 130, a gate insulation layer 140 with a well 140a, and a gate electrode 160 with a gate 160a are formed on a semiconductor wafer 100 in sequence by a conventional method, and then a micro-tip 150 is formed in the well 140a on the resistor layer 130.
  • polyimide is deposited to have a predetermined thickness over the stack by spin coating, thereby forming a focus gate insulation layer 191.
  • a focus gate electrode 190 is formed over the focus gate insulation layer 191.
  • the focus gate insulation layer 191 is formed by spin coating, soft baking and then curing, and the thickness of the focus gate insulation layer 191 ranges from 3 to 150 ⁇ m. This range of the thickness will be described in detail below.
  • a focus gate 109a or 190b is formed in the focus gate electrode 190 by photolithography.
  • a predetermined photoresist pattern 200a or 200b is formed on the focus gate electrode 190, and portions of the focus gate electrode 190 which are exposed through the photoresist pattern 200a or 100b are etched by a general dry or wet etching method using the photoresist pattern 200a or 200b as an etch mask, thereby resulting in the focus gate 190a or 190b in the focus gate electrode 190.
  • FIG. 7A illustrates a configuration in which a plurality of micro-tips 160 are exposed through the same single focus gate 190a
  • the thickness of the focus gate insulation layer 191 is in the range of 3-150 ⁇ m for the configuration of FIG. 7A, and of 6-50 ⁇ m for the configuration of FIG. 7B.
  • the thickness of the focus gate insulation layer 191 may be in the range of 3-10 ⁇ m.
  • the thickness of the focus gate insulation layer 191 may be in the range of 6-50 ⁇ m.
  • the thickness of the focus gate insulation layer 191 may be in the range of 10-150 ⁇ m.
  • the photoresist pattern 200a or 200 is stripped, and the underlying focus gate insulation layer 191 is etched using the focus electrode pattern 190' as an etch mask.
  • the focus gate insulation layer 191 may be etched by dry etching such as RIE or plasma etching.
  • RIE reactive ion etching
  • a plasma etching method is applied, a gas mixture containing O 2 as a major component, and a fluorine-based gas such as CF 4 , SF 6 or CHF 3 may be used as a reaction gas.
  • the gas mixture may be CF 4 /O 2 , SF 6 /O 2 , CHF 3 /O 2 , CF 4 /SF 6 /O 2 , CF 4 /CHF 3 /O 2 , or SF 6 /CHF 3 /O 2 .
  • a gas mixture of O 2 and a chlorine-based gas for example, Cl 2 /O 2 , CCl 4 /O 2 , or Cl 2 /CCl 4 /O 2 , can be used as a reaction gas.
  • polyimide layers are etched into a grass-like structure by dry plasma etching using O 2 .
  • the glass-like structure describes rough surface features of the resulting structure due to different etch rates over regions of the polyimide layer.
  • the addition of O 2 to the fluorine-based gas is for increasing the etch rate of the polyimide focus gate insulation layer 191, such that the micro-tip 150 below the focus gate insulation layer 191 can be etched by plasma.
  • the etch rate of the micro-tip 150 by plasma can be adjusted by varying the O 2 -to-fluorine- or chlorine-based gas ratio in a reaction gas used, plasma pressure, and plasma power in plasma etching the focus gate insulation layer 191.
  • the focus gate insulation layer 191 formed of a carbonaceous polymer such as polyimide or photoresist is etched into a grass-like structure, the polyimide or photoresist may randomly remain over the micro-tip 150.
  • the polyimide or photoresist remaining on the micro-tip 150 acts as a mask for a further etching to the micro-tip 150.
  • FIG. 9 is a scanning electron microscope (SEM) photo showing the micro-tip, gate insulation layer, and gate electrode formed on the substrate
  • FIG. 10 is a magnified view of the micro-tip of FIG. 9.
  • the micro-tip as a collection of nano-tips has nano-sized surface feature, as described previously.
  • the gate turn-on voltage of the FED fabricated by the method according to the present invention is reduced by about 20V, and the working voltage (a voltage level at a 1/90 duty ratio and a 60Hz frequency) is lowered by about 40-50V, compared with a conventional FED.
  • the height of the micro-tip and the size of the nano-tips can be varied by adjusting the etching ratios or etching rates of the focus gate insulation layer formed of a carbonaceous polymer, and the micro-tip during the plasma etching, as described previously.
  • FIG. 11 is a SEM photo of the FED illustrating the sharp vertical sidewalls of an opening in the focus gate insulation layer. As a leakage test result, a resistance between the focus gate electrode and the gate electrode is higher than 10 M ⁇ .
  • occurrence of arcing is suppressed.
  • an arcing occurs in the FED, damage of the cathode and the resistor layer is prevented. Due to the minimized arcing effect, a higher working voltage can be applied to the anode, compared with a conventional FED.
  • the micro-tips with nano-sized surface features contributes to increasing the emission current density of the FED increases, so that a high-brightness display can be achieved with the FED.
  • the gate turn-on voltage can be lowered due to the micro-tip as a collection of nano-sized tips, thereby reducing power consumption.
  • an electron beam emitted by the micro-tip can be focused on the anode through the focus gate of the focus gate electrode by varying a voltage level applied to the focus gate electrode. Even for a display with a considerably long substrate-to-faceplate distance, for example, longer than 3 mm, a high-resolution, and a high-color purity for color displays are ensured.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Cold Cathode And The Manufacture (AREA)

Claims (11)

  1. Feldemissionsvorrichtung (FED) umfassend:
    ein Substrat (100);
    eine über dem Substrat (100) ausgebildete Kathode (120);
    auf der Kathode (120) ausgebildete Mikrospitzen (150);
    eine Gateisolierschicht (140) mit Mulden (140a), in deren jeder eine einzelne Mikrospitze (150) gelegen ist, wobei die Gateisolierschicht (140) über dem Substrat (100) ausgebildet ist;
    eine Gateelektrode (160) mit Gates (160a) mit den Mulden (140a) derart ausgerichtet, dass die Mikrospitzen (150) durch ein entsprechendes Gate (160a) freigelegt sind, wobei die Gatelektrode (160) auf der Gateisolierschicht (140) gebildet ist;
    eine Fokusgateisolierschicht (191) mit Öffnungen, denen eines oder mehrere Gates (160a) entsprechen; und
    eine Fokusgateelektrode (190) mit Fokusgates (190a) ausgerichtet mit den Öffnungen der Fokusgateisolierschicht (191), wobei die Fokusgateelektrode (190) auf der Fokusgateisolierschicht (191) ausgebildet ist, dadurch gekennzeichnet, dass:
    die Mikrospitzen (150) Oberflächenmerkmale im Nanomaßstab aufweisen, die in die Oberfläche der Mikrospitzen geätzt sind; und
    die Fokusgateisolierschicht (191) auf der Gateelektrode (160) ausgebildet ist.
  2. Feldemissionsvorrichtung nach Anspruch 1, worin eine Widerstandsschicht (130) über oder unter der Kathode (120) ausgebildet ist oder Widerstandsschichten (130) über und unter der Kathode ausgebildet sind.
  3. Verfahren zur Herstellung einer Feldemissionsvorrichtung (FED) umfassend:
    Ausbilden einer Kathode (120), einer Gateisolierschicht (140) mit Mulden (140a) und einer Gateelektrode (160) mit Gates (160a) nacheinander auf einem Substrat (100) und Ausbilden von Mikrospitzen (150) auf der durch die Mulden (140a) freigelegten Kathode;
    Ausbilden einer Fokusgateisolierschicht (191) auf der Gateelektrode (160) in einer bestimmten Dicke mit einer kohlenstoffhaltigen Polymerschicht derart, dass die Mulden (140a) mit den Mikrospitzen mit der kohlenstoffhaltigen Polymerschicht (191) gefüllt werden;
    Ausbilden einer Fokusgateelektrode (190) auf der Fokusgateelektrode;
    gekennzeichnet durch Ausbilden eines bestimmten Photoresistmusters (200) auf der Fokusgateelektrode;
    Ätzen der Fokusgateelektrode (190) in ein Fokusgateelektrodenmuster unter Verwendung des Photoresistmusters (200) als Ätzmaske;
    Ätzen der durch das Fokusgateelektrodenmuster (190) freigelegten Fokusgateisolierschicht (191) durch Plasmaätzen unter Verwendung von O2 oder einer Gasmischung, die O2 enthält für die Fokusgateisolierschicht (191) und
    ein Gas für die Mikrospitzen als Reaktionsgas, wodurch Mulden in der Gateisolierschicht erhalten werden;
    Ätzen der kohlenstoffhaltigen Polymerschicht (191) in den Mulden (140a) der Gateisolierschicht (140) durch Plasmaätzen unter Verwendung von O2 oder einer Gasmischung, die O2 enthält für die Fokusgateisolierschicht und ein Gas für die Mikrospitzen als Reaktionsgas, so dass die kohlenstoffhaltige Polymerschicht teilweise auf der Oberfläche der Mikrospitzen verbleibt; und
    Ätzen der Oberfläche der Mikrospitzen (150) durch Plasmaätzen unter Verwendung der auf den Mikrospitzen verbliebenen kohlenstoffhaltigen Polymerschicht als Ätzmaske und Ätzen der kohlenstoffhaltigen Polymerschicht selbst unter Verwendung des Reaktionsgases, wodurch Mikrospitzen mit Oberflächenmerkmalen im Nanomaßstab erhalten werden.
  4. Verfahren nach Anspruch 3, worin die kohlenstoffhaltige Polymerschicht (191) aus Polyimid oder Photoresist gebildet wird.
  5. Verfahren nach Anspruch 3, worin die kohlenstoffhaltige Polymerschicht (191) durch reaktives lonenätzen (RIE) geätzt wird.
  6. Verfahren nach Anspruch 5, worin die Oberflächenmerkmale im Nanomaßstab der Mikrospitzen durch Verändern der Ätzraten der kohlenstoffhaltigen Polymerschicht und der Mikrospitzen eingestellt werden.
  7. Verfahren nach Anspruch 6, worin die Ätzraten durch Verändern von Sauerstoff im Gas für die Mikrochips im Reaktionsgas, Plasmaenergie oder Plasmadruck während der Ätzprozesse eingestellt werden.
  8. Verfahren nach Anspruch 5, worin die Mikrospitzen aus mindestens einem ausgewählt aus der Gruppe von Molybdän (Mo), Wolfram (W), Silicium (Si) und Diamant ausgebildet werden und das Reaktionsgas ein Gasgemisch aus O2 und fluorhaltigem Gas ist.
  9. Verfahren nach Anspruch 8, worin das Reaktionsgas CF4/O2, SF6/O2, CHF3/O2, CF4/SF6/O2, CF4/CHF3/O2 oder SF6/CHF3/O2 umfasst.
  10. Verfahren nach Anspruch 5, worin die Mikrospitzen aus mindestens einem ausgewählt aus der Gruppe von Molybdän (Mo), Wolfram (W), Silicium (Si) und Diamant ausgebildet werden und das Reaktionsgas ein Gasgemisch aus O2 und chlorhaltigem Gas ist.
  11. Verfahren nach Anspruch 10, worin das Reaktionsgas Cl2/O2, CCl4/O2 oder Cl2/CCl4/O2 umfasst.
EP01300051A 2000-01-05 2001-01-04 Feldemissionsvorrichtung und Herstellungsverfahren dafür Expired - Lifetime EP1115134B1 (de)

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KR2000000361 2000-01-05
KR10-2000-0000361A KR100464314B1 (ko) 2000-01-05 2000-01-05 전계방출소자 및 그 제조방법

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US (2) US6632114B2 (de)
EP (1) EP1115134B1 (de)
JP (1) JP2001216887A (de)
KR (1) KR100464314B1 (de)
DE (1) DE60118104T2 (de)

Families Citing this family (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100480772B1 (ko) * 2000-01-05 2005-04-06 삼성에스디아이 주식회사 나노 스케일의 표면 거칠기를 가지는 마이크로 구조물의형성방법
KR100480771B1 (ko) * 2000-01-05 2005-04-06 삼성에스디아이 주식회사 전계방출소자 및 그 제조방법
KR100590524B1 (ko) * 2001-12-06 2006-06-15 삼성에스디아이 주식회사 포커싱 전극을 가지는 전계방출소자 및 그 제조방법
FR2836279B1 (fr) * 2002-02-19 2004-09-24 Commissariat Energie Atomique Structure de cathode pour ecran emissif
KR100576733B1 (ko) * 2003-01-15 2006-05-03 학교법인 포항공과대학교 일체형 3극구조 전계방출디스플레이 및 그 제조 방법
US7279686B2 (en) * 2003-07-08 2007-10-09 Biomed Solutions, Llc Integrated sub-nanometer-scale electron beam systems
KR100548250B1 (ko) * 2003-08-09 2006-02-02 엘지전자 주식회사 표면 전도형 전계 방출 소자의 매트릭스 구조
KR100523840B1 (ko) * 2003-08-27 2005-10-27 한국전자통신연구원 전계 방출 소자
KR101064480B1 (ko) * 2004-06-29 2011-09-15 삼성에스디아이 주식회사 전자방출소자 및 이를 이용한 전자방출 표시장치
JP2006080046A (ja) * 2004-09-13 2006-03-23 Ngk Insulators Ltd 電子放出装置
CN100543913C (zh) * 2005-02-25 2009-09-23 清华大学 场发射显示装置
KR20070041983A (ko) * 2005-10-17 2007-04-20 삼성에스디아이 주식회사 전자 방출 표시 디바이스
KR20070044574A (ko) * 2005-10-25 2007-04-30 삼성에스디아이 주식회사 전자 방출 디바이스와 이를 이용한 전자 방출 표시디바이스
KR20070046650A (ko) * 2005-10-31 2007-05-03 삼성에스디아이 주식회사 전자 방출 디바이스
US7556550B2 (en) * 2005-11-30 2009-07-07 Motorola, Inc. Method for preventing electron emission from defects in a field emission device
FR2899572B1 (fr) * 2006-04-05 2008-09-05 Commissariat Energie Atomique Protection de cavites debouchant sur une face d'un element microstructure
JP2009054317A (ja) * 2007-08-23 2009-03-12 Nippon Hoso Kyokai <Nhk> 冷陰極電子源基板及び冷陰極ディスプレイ
US8260174B2 (en) 2008-06-30 2012-09-04 Xerox Corporation Micro-tip array as a charging device including a system of interconnected air flow channels
CN103854935B (zh) * 2012-12-06 2016-09-07 清华大学 场发射阴极装置及场发射器件
US10147745B2 (en) 2015-04-01 2018-12-04 Shanghai Tianma Micro-electronics Co., Ltd. Array substrate, display panel and display device
CN104730782B (zh) * 2015-04-01 2018-03-27 上海天马微电子有限公司 一种阵列基板、显示面板和显示装置

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3921022A (en) * 1974-09-03 1975-11-18 Rca Corp Field emitting device and method of making same
US4943343A (en) * 1989-08-14 1990-07-24 Zaher Bardai Self-aligned gate process for fabricating field emitter arrays
US5534743A (en) * 1993-03-11 1996-07-09 Fed Corporation Field emission display devices, and field emission electron beam source and isolation structure components therefor
FR2726689B1 (fr) * 1994-11-08 1996-11-29 Commissariat Energie Atomique Source d'electrons a effet de champ et procede de fabrication de cette source, application aux dispositifs de visualisation par cathodoluminescence
US5569975A (en) * 1994-11-18 1996-10-29 Texas Instruments Incorporated Cluster arrangement of field emission microtips
US5674592A (en) * 1995-05-04 1997-10-07 Minnesota Mining And Manufacturing Company Functionalized nanostructured films
TW413828B (en) * 1995-07-07 2000-12-01 Nippon Electric Co Electron gun provided with a field emission cold cathode and an improved gate structure
KR970023568A (ko) * 1995-10-31 1997-05-30 윤종용 전계 방출 표시소자와 그 구동 방법 및 제조 방법
JPH09219144A (ja) * 1996-02-08 1997-08-19 Futaba Corp 電界放出カソードとその製造方法
JPH09270228A (ja) * 1996-04-01 1997-10-14 Matsushita Electric Ind Co Ltd 電界放射型電子源の製造方法
US5726524A (en) * 1996-05-31 1998-03-10 Minnesota Mining And Manufacturing Company Field emission device having nanostructured emitters
JPH1012127A (ja) * 1996-06-24 1998-01-16 Nec Corp 電界電子放出装置
JP3171121B2 (ja) * 1996-08-29 2001-05-28 双葉電子工業株式会社 電界放出型表示装置
KR100365444B1 (ko) * 1996-09-18 2004-01-24 가부시끼가이샤 도시바 진공마이크로장치와이를이용한화상표시장치
US6020677A (en) * 1996-11-13 2000-02-01 E. I. Du Pont De Nemours And Company Carbon cone and carbon whisker field emitters
US5972235A (en) * 1997-02-28 1999-10-26 Candescent Technologies Corporation Plasma etching using polycarbonate mask and low pressure-high density plasma
JPH10269933A (ja) * 1997-03-24 1998-10-09 Sony Corp 電界放出型エミッタの製造方法
US6002199A (en) * 1997-05-30 1999-12-14 Candescent Technologies Corporation Structure and fabrication of electron-emitting device having ladder-like emitter electrode
JP3777735B2 (ja) * 1997-08-21 2006-05-24 双葉電子工業株式会社 電界放射冷陰極
US6008062A (en) * 1997-10-31 1999-12-28 Candescent Technologies Corporation Undercutting technique for creating coating in spaced-apart segments
JP2000285795A (ja) * 1999-03-31 2000-10-13 Sony Corp 電子放出源およびその製造方法ならびにディスプレイ装置
US6464842B1 (en) * 1999-06-22 2002-10-15 President And Fellows Of Harvard College Control of solid state dimensional features
JP3312008B2 (ja) * 1999-06-30 2002-08-05 岡谷電機産業株式会社 電界電子放出型サージ吸収素子の製造方法
KR100480771B1 (ko) * 2000-01-05 2005-04-06 삼성에스디아이 주식회사 전계방출소자 및 그 제조방법

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US20010006325A1 (en) 2001-07-05
KR20010068441A (ko) 2001-07-23
US6632114B2 (en) 2003-10-14
JP2001216887A (ja) 2001-08-10
EP1115134A1 (de) 2001-07-11
US20040027052A1 (en) 2004-02-12
DE60118104D1 (de) 2006-05-11
KR100464314B1 (ko) 2004-12-31
US6927534B2 (en) 2005-08-09
DE60118104T2 (de) 2006-11-09

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